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2 Precision, Rail-to-Rail, Zero-Drift, Resistor-Programmable Instrumentation Amplifier FEATRES db CMRR Independent of Gain Maximum Offset Voltage: µv Maximum Offset Voltage Drift: nv/ C Rail-to-Rail Input Rail-to-Rail Output -Resistor Programmable Gain Supply Operation:.V to ±.V Typical Noise:.µV P-P (.Hz to Hz) Typical Supply Current: µa LTC-SYNC Allows Synchronization to External Clock Available in MS and mm mm.mm DFN Packages APPLICATIO S Thermocouple Amplifiers Electronic Scales Medical Instrumentation Strain Gauge Amplifiers High Resolution Data Acquisition TYPICAL APPLICATIO Differential Bridge Amplifier V R < k LTC, R k R Ω OT GAIN = R R TA DESCRIPTIO The LTC is a high precision instrumentation amplifier. The CMRR is typically db with a single or dual V supply and is independent of gain. The input offset voltage is guaranteed below µv with a temperature drift of less than nv/ C. The LTC is easy to use; the gain is adjustable with two external resistors, like a traditional op amp. The LTC uses charge balanced sampled data techniques to convert a differential input voltage into a single ended signal that is in turn amplified by a zero-drift operational amplifier. The differential inputs operate from rail-to-rail and the single ended output swings from rail-to-rail. The LTC can be used in single supply applications, as low as.v. It can also be used with dual ±.V supplies. The LTC requires no external clock, while the LTC-SYNC has a CLK pin to synchronize to an external clock. The LTC is available in an MS surface mount package. For space limited applications, the LTC is available in a mm mm.mm dual fine pitch leadless package (DFN)., LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. INPT OFFSET VOLTAGE (µv) Typical Input Referred Offset vs Input (V S = V) V S = V V REF = V T A = C G = G = G = G = INPT COMMON MODE VOLTAGE (V) TAb syncfb

3 ABSOLTE AXI RATI GS (Note ) W W W Total Supply Voltage (V to V )... V Input Current... ±ma V IN V REF....V V IN V REF....V Output Short Circuit Duration... Indefinite Operating Temperature Range LTCC, LTCC-SYNC... C to C LTCI, LTCI-SYNC... C to C LTCH... C to C Storage Temperature Range MS Package... C to C DD Package... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR ATIO W EN/CLK IN IN V TOP VIEW V OT RG REF MS PACKAGE -LEAD PLASTIC MSOP T JMAX = C, θ JA = C/W PIN IS EN ON LTC, CLK ON LTC-SYNC ORDER PART NMBER LTCCMS LTCIMS LTCHMS LTCCMS-SYNC LTCIMS-SYNC MS PART MARKING LTVT LTJY LTAFB *LTBNP EN IN IN V TOP VIEW DD PACKAGE -LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = C/W NDERSIDE METAL INTERNALLY CONNECTED TO V (PCB CONNECTION OPTIONAL) V OT RG REF ORDER PART NMBER LTCCDD LTCIDD LTCHDD DD PART MARKING *LAEQ *The temperature grade (C, I, or H) is indicated on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V = V, V = V, REF = mv. Output voltage swing is referenced to V. All other specifications reference the OT pin to the REF pin. PARAMETER CONDITIONS MIN TYP MAX NITS Gain Error A V =.. % Gain Nonlinearity A V =, LTC ppm A V =, LTC-SYNC ppm Input Offset Voltage (Note ) V CM = mv ± µv Average Input Offset Drift (Note ) T A = C to C ± nv/ C T A = C to C. µv/ C Average Input Bias Current (Note ) V CM =.V na Average Input Offset Current (Note ) V CM =.V na Input Noise Voltage DC to Hz. µv P-P Common Mode Rejection Ratio A V =, V CM = V to V, LTCC, LTCC-SYNC db (Notes, ) A V =, V CM =.V to.9v, LTCI, LTCI-SYNC db A V =, V CM = V to V, LTCI, LTCI-SYNC 9 db A V =, V CM =.V to.9v, LTCH db A V =, V CM = V to V, LTCH db syncfb

4 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V = V, V = V, REF = mv. Output voltage swing is referenced to V. All other specifications reference the OT pin to the REF pin. PARAMETER CONDITIONS MIN TYP MAX NITS Power Supply Rejection Ratio (Note ) V S =.V to V db Output Voltage Swing High R L = k to V..9 V R L = k to V.9.9 V Output Voltage Swing Low mv Supply Current No Load. ma Supply Current, Shutdown V EN.V, LTC Only µa EN/CLK Pin Input Low Voltage, V IL. V EN/CLK Pin Input High Voltage, V IH. V EN/CLK Pin Input Current V EN/CLK = V. µa Internal Op Amp Gain Bandwidth khz Slew Rate. V/µs Internal Sampling Frequency khz The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V = V, V = V, REF = mv. Output voltage swing is referenced to V. All other specifications reference the OT pin to the REF pin. PARAMETER CONDITIONS MIN TYP MAX NITS Gain Error A V =.. % Gain Nonlinearity A V = ppm Input Offset Voltage (Note ) V CM = mv ± µv Average Input Offset Drift (Note ) T A = C to C ± nv/ C T A = C to C. µv/ C Average Input Bias Current (Note ) V CM =.V na Average Input Offset Current (Note ) V CM =.V na Common Mode Rejection Ratio A V =, V CM = V to V, LTCC db (Notes, ) A V =, V CM = V to V, LTCC-SYNC db A V =, V CM =.V to.9v, LTCI db A V =, V CM =.V to.9v, LTCI-SYNC db A V =, V CM = V to V, LTCI, LTCI-SYNC 9 db A V =, V CM =.V to.9v, LTCH db A V =, V CM = V to V, LTCH db Power Supply Rejection Ratio (Note ) V S =.V to V db Output Voltage Swing High R L = k to V..9 V R L = k to V.9.9 V Output Voltage Swing Low mv Supply Current No Load.. ma Supply Current, Shutdown V EN.V, LTC Only µa EN/CLK Pin Input Low Voltage, V IL. V EN/CLK Pin Input High Voltage, V IH. V EN/CLK Pin Input Current V EN/CLK = V µa Internal Op Amp Gain Bandwidth khz Slew Rate. V/µs Internal Sampling Frequency khz syncfb

5 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V = V, V = V, REF = V. PARAMETER CONDITIONS MIN TYP MAX NITS Gain Error A V =.. % Gain Nonlinearity A V = ppm Input Offset Voltage (Note ) V CM = V ± µv Average Input Offset Drift (Note ) T A = C to C ± nv/ C T A = C to C. µv/ C Average Input Bias Current (Note ) V CM = V na Average Input Offset Current (Note ) V CM = V na Common Mode Rejection Ratio A V =, V CM = V to V, LTCC db (Notes, ) A V =, V CM = V to V, LTCC-SYNC db (Notes, ) A V =, V CM =.9V to.9v, LTCI db A V =, V CM =.9V to.9v, LTCI-SYNC db A V =, V CM = V to V, LTCI, LTCI-SYNC 9 db A V =, V CM =.9V to.9v, LTCH db A V =, V CM = V to V, LTCH 9 db Power Supply Rejection Ratio (Note ) V S =.V to V db Maximum Output Voltage Swing R L = k to GND, C and I Grades ±. ±. V R L = k to GND, All Grades ±. ±.9 V R L = k to GND, LTCH Only ±. ±. V Supply Current No Load.9. ma Supply Current, Shutdown V EN.V, LTC Only µa EN Pin Input Low Voltage, V IL. V CLK Pin Input Low Voltage, V IL. V EN/CLK Pin Input High Voltage, V IH. V EN/CLK Pin Input Current V EN/CLK = V µa Internal Op Amp Gain Bandwidth khz Slew Rate. V/µs Internal Sampling Frequency khz Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels in high speed automatic test systems. V OS is measured to a limit determined by test equipment capability. Note : If the total source resistance is less than k, no DC errors result from the input bias currents or the mismatch of the input bias currents or the mismatch of the resistances connected to IN and IN. Note : The CMRR with a voltage gain, A V, larger than is db (typ). Note : At temperatures above C, the common mode rejection ratio lowers when the common mode input voltage is within mv of the supply rails. Note : The power supply rejection ratio (PSRR) measurement accuracy depends on the proximity of the power supply bypass capacitor to the device under test. Because of this, the PSRR is % tested to relaxed limits at final test. However, their values are guaranteed by design to meet the data sheet limits. syncfb

6 TYPICAL PERFOR A CE CHARACTERISTICS W INPT OFFSET VOLTAGE (µv) V S = V V REF = V T A = C G = G = G = G = INPT OFFSET VOLTAGE (µv) V S = V V REF = V T A = C G = G = G = G = INPT OFFSET VOLTAGE (µv) V S = ±V V REF = V T A = C G= G= G= G= INPT COMMON MODE VOLTAGE (V) INPT COMMON MODE VOLTAGE (V) INPT COMMON MODE VOLTAGE (V) G G G INPT OFFSET VOLTAGE (µv) V S = V V REF = V G = T A = C T A = C T A = C T A = C INPT COMMON MODE VOLTAGE (V) INPT OFFSET VOLTAGE (µv) V S = V V REF = V G = T A = C T A = C T A = C T A = C INPT COMMON MODE VOLTAGE (V) INPT OFFSET VOLTAGE (µv) V S = ±V V REF = V G = T A = C T A = C T A = C T A = C INPT COMMON MODE VOLTAGE (V) G G G INPT OFFSET VOLTAGE (µv) H-GRADE PARTS V S = V V REF = V G = T A = C T A = C T A = C INPT OFFSET VOLTAGE (µv) H-GRADE PARTS V S = V V REF = V G = T A = C T A = C T A = C INPT OFFSET VOLTAGE (µv) H-GRADE PARTS V S = ±V V REF = V G = T A = C T A = C T A = C INPT COMMON MODE VOLTAGE (V) INPT COMMON MODE VOLTAGE (V) INPT COMMON MODE VOLTAGE (V) G G G9 syncfb

7 TYPICAL PERFOR A CE CHARACTERISTICS W Error Due to Input R S vs Input Common Mode (C IN < pf) V S = V V REF = V R = R = R S C IN < pf G = T A = C R S SMALL C IN R S R S = k R S = k R S = k R S = k R S = k INPT COMMON MODE VOLTAGE (V) Error Due to Input R S vs Input Common Mode (C IN < pf) V S = V V REF = V R = R = R S C IN < pf G = T A = C R S = k R S = k R S = k R S = k INPT COMMON MODE VOLTAGE (V) Error Due to Input R S vs Input Common Mode (C IN < pf) V S = ±V V REF = V R = R = R S C IN < pf G = T A = C R S = k R S = k R S = k INPT COMMON MODE VOLTAGE (V) G G G Error Due to Input R S Mismatch vs Input Common Mode (C IN < pf) V S = V V REF = V C IN < pf G = R = k, R = k T A = C R = k, R = k R = k, R = k R = k, R = k R R = k, R = k SMALL C IN R R =k, R = k INPT COMMON MODE VOLTAGE (V) Error Due to Input R S Mismatch vs Input Common Mode (C IN < pf) V S = V V REF = V C IN < pf G = T A = C R IN = k, RIN = k R IN = k, RIN = k R IN = k, RIN = k R IN =k, RIN = k R IN =k, RIN = k R IN =k, RIN = k INPT COMMON MODE VOLTAGE (V) Error Due to Input R S Mismatch vs Input Common Mode (C IN < pf) V S = ±V V REF = V C IN < pf G = T A = C R = k, R = k R = k, R = k R =k, R = k R =k, R = k INPT COMMON MODE VOLTAGE (V) G G G Error Due to Input R S vs Input Common Mode (C IN > µf) V S = V V REF = V R = R = R S C IN > µf G = T A = C R S BIG C IN R S = k R S = k R S = k Error Due to Input R S vs Input Common Mode (C IN > µf) V S = V V REF = V R = R = R S C IN > µf G = T A = C R S = k R S = k R S = k R S = Ω Error Due to Input R S vs Input Common Mode (C IN > µf) V S = ±V V REF = V R = R = R S C IN > µf G = T A = C R S = k R S = k R S = k R S = Ω R S INPT COMMON MODE VOLTAGE (V) INPT COMMON MODE VOLTAGE (V) INPT COMMON MODE VOLTAGE (V) G G G syncfb

8 TYPICAL PERFOR A CE CHARACTERISTICS W Error Due to Input R S Mismatch vs Input Common Mode (C IN >µf) V S = V V REF = V T A = C R = k, R = k R = k, R = Ω R = k, R = Ω R = Ω, R = k R R = Ω, R = k BIG C IN R =k, R = k R INPT COMMON MODE VOLTAGE (V) G9 Error Due to Input R S Mismatch vs Input Common Mode (C IN >µf) V S = V V REF = V T A = C R = k, R = k R = k, R = Ω R = k, R = Ω R = Ω, R = k R = Ω, R = k R =k, R = k INPT COMMON MODE VOLTAGE (V) G Error Due to Input R S Mismatch vs Input Common Mode (C IN >µf) V S = ±V V REF = V T A = C R = k, R = k R = k, R = Ω R = k, R = Ω R = Ω, R = k R = Ω, R = k R =k, R = k INPT COMMON MODE VOLTAGE (V) G INPT OFFSET VOLTAGE (µv) Offset Voltage vs Temperature V OS vs REF (Pin ) V OS vs REF (Pin ) V S = V V S = ±V V S = V V OS (µv) V IN = V IN = REF G = TA = C V S = V V S = V VOS (µv) V IN = V IN = REF G = T A = C V S = V TEMPERATRE ( C) V REF (V) 9 V REF (V) G G G NONLINEARITY (ppm) Gain Nonlinearity, G = Gain Nonlinearity, G = CMRR vs Frequency V S = ±.V V REF = V G = R L = k T A = C OTPT VOLTAGE (V) NONLINEARITY (ppm). V S = ±.V V REF = V G = R L = k T A = C..... OTPT VOLTAGE (V) CMRR (db) 9 V S = V, V, ±V V IN = V P-P R = k, R = k R R R = R = k R = R = k R = k, R = k FREQENCY (Hz) G G G syncfb

9 TYPICAL PERFOR A CE CHARACTERISTICS W INPT REFERRED NOISE DENSITY (nv/ Hz) Input Voltage Noise Density vs Frequency G = T A = C V S = ±V V S = V V S = V FREQENCY (Hz) INPT REFERRED NOISE VOLTAGE (µv) Input Referred Noise in Hz Bandwidth V S = V T A = C TIME (s) INPT REFERRED NOISE VOLTAGE (µv) Input Referred Noise in Hz Bandwidth V S = V T A = C TIME (s) G G9 G OTPT VOLTAGE SWING (V) Output Voltage Swing vs Output Current. T A = C V S = V, SORCING V S = V, SORCING V S = V, SINKING V S = V, SINKING. OTPT CRRENT (ma) OTPT VOLTAGE SWING (V). Output Voltage Swing vs Output Current V S = ±V T A = C SORCING SINKING. OTPT CRRENT (ma) SPPLY CRRENT Supply Current vs Supply Voltage..9 T A = C.9. T A = C. T A = C. T A = C SPPLY VOLTAGE (V) G G G SETTLING TIME (ms) Low Gain Settling Time vs Settling Accuracy.... SETTLING ACCRACY (%) V S = V dv OT = V G < T A = C SETTLING TIME (ms) Settling Time vs Gain V S = V dv OT = V.% ACCRACY T A = C GAIN (V/V) CLOCK FREQENCY (khz) Internal Clock Frequency vs Supply Voltage T A = C T A = C T A = C T A = C... SPPLY VOLTAGE (V). G G G syncfb

10 PI F CTIO S EN (Pin, LTC Only): Active Low Enable Pin. CLK (Pin, LTC-SYNC Only): Clock input for synchronizing to external system clock. IN (Pin ): Inverting Input. IN (Pin ): Noninverting Input. V (Pin ): Negative Supply. REF (Pin ): Voltage Reference (V REF ) for Amplifier Output. RG (Pin ): Inverting Input of Internal Op Amp. With a resistor, R, connected between the OT pin and the RG pin and a resistor, R, between the RG pin and the REF pin, the DC gain is given by R / R. OT (Pin ): Amplifier Output. V OT = GAIN (V IN V IN ) V REF V (Pin ): Positive Supply. BLOCK DIAGRA W IN IN ZERO-DRIFT OP AMP OT C S C H V REF RG V EN/CLK* BD *NOTE: PIN IS EN ON THE LTC AND CLK ON THE LTC-SYNC. APPLICATIO S I FOR Theory of Operation ATIO W The LTC uses an internal capacitor (C S ) to sample a differential input signal riding on a DC common mode voltage (see Block Diagram). This capacitor s charge is transferred to a second internal hold capacitor (C H ) translating the common mode of the input differential signal to that of the REF pin. The resulting signal is amplified by a zero-drift op amp in the noninverting configuration. The RG pin is the negative input of this op amp and allows external programmability of the DC gain. Simple filtering can be realized by using an external capacitor across the feedback resistor. Input Voltage Range The input common mode voltage range of the LTC is rail-to-rail. However, the following equation limits the size of the differential input voltage: V (V IN V IN ) V REF V. Where V IN and V IN are the voltages of the IN and IN pins respectively, V REF is the voltage at the REF pin and V is the positive supply voltage. For example, with a V single supply and a V to mv differential input voltage, V REF must be between V and.v. ± Volt Operation When using the LTC with supplies over.v, care must be taken to limit the maximum difference between any of the input pins (IN or IN) and the REF pin to.v; if not, the device will be damaged. For example, if rail-torail input operation is desired when the supplies are at ±V, the REF pin should be V, ±.V. As a second example, if V is V and V and REF are at V, the inputs should not exceed.v. syncfb 9

11 APPLICATIO S I FOR Settling Time ATIO W The sampling rate is khz and the input sampling period during which C S is charged to the input differential voltage V IN is approximately µs. First assume that on each input sampling period, C S is charged fully to V IN. Since C S = C H (= pf), a change in the input will settle to N bits of accuracy at the op amp noninverting input after N clock cycles or µs(n). The settling time at the OT pin is also affected by the settling of the internal op amp. Since the gain bandwidth of the internal op amp is typically khz, the settling time is dominated by the switched capacitor front end for gains below (see Typical Performance Characteristics). Input Current Whenever the differential input V IN changes, C H must be charged up to the new input voltage via C S. This results in an input charging current during each input sampling period. Eventually, C H and C S will reach V IN and, ideally, the input current would go to zero for DC inputs. In reality, there are additional parasitic capacitors which disturb the charge on C S every cycle even if V IN is a DC voltage. For example, the parasitic bottom plate capacitor on C S must be charged from the voltage on the REF pin to the voltage on the IN pin every cycle. The resulting input charging current decays exponentially during each input sampling period with a time constant equal to R S C S. If the voltage disturbance due to these currents settles before the end of the sampling period, there will be no errors due to source resistance or the source resistance mismatch between IN and IN. With R S less than k, no DC errors occur due to this input current. In the Typical Performance Characteristics section of this data sheet, there are curves showing the additional error from non-zero source resistance in the inputs. If there are no large capacitors across the inputs, the amplifier is less sensitive to source resistance and source resistance mismatch. When large capacitors are placed across the inputs, the input charging currents described above result in larger DC errors, especially with source resistor mismatches. Power Supply Bypassing The LTC uses a sampled data technique and therefore contains some clocked digital circuitry. It is therefore sensistive to supply bypassing. For single or dual supply operation, a ceramic capacitor must be connected between Pin (V ) and Pin (V ) with leads as short as possible. SINGLE SPPLY, NITY GAIN DAL SPPLY V V V IN V IN V D VOT V IN V IN V D V R R VOT V REF V < V IN < V V < V IN < V V < V D <.V V OT = V D V < V IN < V AND V IN V REF <.V V < V IN < V AND V IN V REF <.V V < V D V REF <.V R V OT = ( ) V D V REF R F Figure syncfb

12 APPLICATIO S I FOR ATIO W Synchronizing to an External Clock (LTC-SYNC Only) The LTC has an internally generated sample clock that is typically khz. There is no need to provide the LTC with a clock. However, in some applications, it may be desirable for the user to control the sampling frequency more precisely to avoid undesirable aliasing. This can be done with the LTC-SYNC. This device uses PIN as a clock input whereas the LTC uses Pin as an enable pin. If CLK (PIN ) is left floating on the LTC-SYNC, the device will run on its internal oscillator, similar to the LTC. However, if not externally synchronizing to a system clock, it is recommended that the LTC be used instead of the LTC-SYNC because the LTC-SYNC is sensitive to parasitic capacitance on the CLK pin when left floating. Clocking the LTC-SYNC is accomplished by driving the CLK pin at times the desired sample clock frequency. This completely disables the internal clock. For example, to achieve the nominal LTC sample clock rate of khz, a khz external clock should be applied to the CLK pin of the LTC-SYNC. If a square wave is used to drive the CLK pin, a µs RC time constant should be placed in front of the CLK pin to maintain low offset voltage performance (see Figure ). This avoids internal and external coupling of the high frequency components of the external clock at the instant the LTC-SYNC holds the sampled input. The LTC-SYNC is tested with a sample clock of khz (f CLK = khz) to the same specifications as the LTC. In addition the LTC-SYNC is tested at / and X this frequency to verify proper operation. The curves in the Typical Performance Characteristics section of this datasheet apply to the LTC-SYNC when driving it with a khz clock at PIN (f CLK = khz, khz sample clock rate). Below are three curves that show the behavior of the LTC-SYNC as the clock frequency is varied. The offset is essentially unaffected over a : increase or decrease of the typical LTC sample clock speed. The bias current is directly proportional to the clock speed. The noise is roughly proportional to the square root of the clock frequency. For optimum noise and bias current performance, drive the LTC-SYNC with a nominal khz external clock (khz sample clock). V IN V D V IN LTC-SYNC V CLK R R Figure kω EXTERNAL CLOCK.nF V V VOT F LTC-SYNC Input Offset vs Sample Frequency LTC-SYNC Average Input Bias Current vs Sample Frequency LTC-SYNC Input Referred Noise vs Sample Frequency INPT OFFSET (µv) V S = ±V V S = V V S = V Typ LTC Sample Frequency INPT BIAS CRRENT (na) V S = V V REF = V CM = V Typ LTC Sample Frequency INPT REFERRED NOISE VOLTAGE (µv PP ) V S = V T A = C Noise in Hz Bandwidth Typ LTC Sample Frequency SAMPLE FREQENCY (Hz) (=F CLK /) SAMPLE FREQENCY (Hz) (=F CLK /) SAMPLE FREQENCY (F CLK /) F F F syncfb

13 TYPICAL APPLICATIO S V OT i R LOAD Precision Current Source V C LTC RG REF EN k V.k V i = C, i ma R < V OT < (V V C ) Precision (Low Noise.V Reference) LT µf k V LTC.V (nv/ Hz) TA TA Precision Doubler (General Purpose) V Precision Inversion (General Purpose) V V IN LTC VOT V IN LTC V OT V OT = V IN V OT = V IN V TA V TA syncfb

14 TYPICAL APPLICATIO S Differential Thermocouple Amplifier M M V C C TYPE K THERMOCOPLE (.µv/ C) YELLOW ORANGE THERMAL COPLING.µF M V M LT V O R k.µf k k V LTC LTC REF RG EN k % Ω SCALE FACTOR TRIM mv/ C 9k % TA High Side Power Supply Current Sense V REG.Ω I LOAD LOAD LTC, k OT mv/a OF LOAD CRRENT Ω TA syncfb

15 PACKAGE DESCRIPTIO MS Package -Lead Plastic MSOP (Reference LTC DWG # --).9 ±. (. ±.). (.) MIN.. (..). ±. (. ±.) TYP. (.) BSC. ±. (. ±.) (NOTE ). (.) REF RECOMMENDED SOLDER PAD LAYOT GAGE PLANE. (.). (.) DETAIL A DETAIL A NOTE:. DIMENSIONS IN MILLIMETER/(INCH). DRAWING NOT TO SCALE TYP. ±. (. ±.) SEATING PLANE.9 ±. (.9 ±.). (.) MAX.. (.9.) TYP. (.) BSC. DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED.mm (.") PER SIDE. DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED.mm (.") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.mm (.") MAX. ±. (. ±.) (NOTE ). (.) REF. ±. (. ±.) MSOP (MS) syncfb

16 PACKAGE DESCRIPTIO DD Package -Lead Plastic DFN (mm mm) (Reference LTC DWG # --9). ±.. ±.. ±.. ±. ( SIDES) PACKAGE OTLINE. ±.. BSC. ±. ( SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R =. TYP. ±. PIN TOP MARK (NOTE ). REF. ±. ( SIDES). ±.... ±. ( SIDES). ±.. ±. ( SIDES) BOTTOM VIEW EXPOSED PAD NOTE:. DRAWING TO BE MADE A JEDEC PACKAGE OTLINE M-9 VARIATION OF (WEED-). DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON TOP AND BOTTOM OF PACKAGE. BSC (DD) DFN Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. syncfb

17 TYPICAL APPLICATIO.k LTC Linearized Platinum RTD Amplifier V.k i ma V 9k LTC M.k PT* -WIRE RTD k 9.k CW GAIN CW.9k k *CONFORMING TO IEC OR DIN R T = R O (.9 T. T ), R O = Ω (e.g. Ω AT C,.9Ω AT C,.Ω AT C) k 9.9Ω LINEARITY LT-. ZERO k CW 9Ω V.9k mv/ C C C (±. C) Ω TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LT Single Resistor Gain Programmable, Precision Instrumentation Amplifier Single Gain Set Resistor: G = to,, Low Noise:.nV Hz LTC/LTC Zero-Drift Single/Dual Operation Amplifier SOT-/MS Package LTC/LTC Zero-Drift µpower Operational Amplifier SOT-/MS Package, µa/op Amp LTC Single Supply, Zero Drift, Rail-to-Rail Input and Output Instrumentation MS Package, µv Max V OS, nv/ C Max Drift Amplifier syncfb LT/TP Rev B K PRINTED IN SA Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - LINEAR TECHNOLOGY CORPORATION