FEATURES DESCRIPTIO. LTC Linear Phase, DC Accurate, Low Power, 10th Order Lowpass Filter APPLICATIO S TYPICAL APPLICATIO

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1 Linear Phase, DC Accurate, Low Power, 0th Order Lowpass Filter FEATRES One External R Sets Cutoff Frequency Root Raised Cosine Response ma Supply Current with a Single Supply p to khz Cutoff on a Single Supply 0th Order, Linear Phase Filter in an SO- DC Accurate, V OS(MAX) = 5mV Low Power Modes Differential or Single-Ended Inputs 0dB CMRR (DC) db Signal-to-Noise Ratio, V S = 5V Operates from to ±5V Supplies APPLICATIO S Data Communication Filters for Operation Linear Phase and Phase Matched Filters for I/Q Signal Processing Pin Programmable Cutoff Frequency Lowpass Filters DESCRIPTIO The LTC 59- is a 0th order lowpass filter featuring linear phase and a root raised cosine amplitude response. The high selectivity of the combined with its linear phase in the passband makes it suitable for filtering both in data communications and data acquisition sys- tems. Furthermore, its root raised cosine response offers the optimum pulse shaping for PAM data communications. The filter attenuation is 50dB at.5 f CTOFF, 0dB at f CTOFF, and in excess of 0dB at f CTOFF. DCaccuracy-sensitive applications benefit from the 5mV maximum DC offset. The sampled data filter does not require an external clock yet its cutoff frequency can be set with a single external resistor with a typical accuracy of.5% or better. The external resistor programs an internal oscillator whose frequency is divided by either, or prior to being applied to the filter network. Pin 5 determines the divider setting. Thus, up to three cutoff frequencies can be obtained for each external resistor value. sing various resistor values and divider settings, the cutoff frequency can be programmed over a range of six octaves. Alternatively, the cutoff frequency can be set with an external clock and the clock-to-cutoff frequency ratio is :. The ratio of the internal sampling rate to the filter cutoff frequency is :. The is fully tested for a cutoff frequency of khz with a single supply. The features power saving modes and it is available in an SO- surface mount package., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO Single Supply, khz/khz/khz Lowpass Filter Frequency Response, f CTOFF = khz/khz/khz 0.k k V IN IN + OT V OT IN V + 7 / 5 / EASY TO SET f CTOFF : / f CTOFF = khz (0k/R EXT), OR 00pF 59- TA0 GAIN (db) FREQENCY (khz) 59- TA0a

2 ABSOLTE AXI RATI GS W W W (Note ) Total Supply Voltage... V Power Dissipation mW Operating Temperature LTC59C... 0 C to 70 C LTC59I... 0 C to 5 C Storage Temperature... 5 C to 50 C Lead Temperature (Soldering, 0 sec) C PACKAGE/ORDER I FOR IN + IN GND V TOP VIEW 7 5 S PACKAGE -LEAD PLASTIC SO T JMAX = 5 C, θ JA = 50 C/W OT V + R X DIV/CLK W ATIO ORDER PART NMBER LTC59CS- LTC59IS- S PART MARKING 59 59I Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 5 C. V S = (V + =, V = 0V), f CTOFF = khz, R LOAD = 0k unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX NITS Filter Gain V S = 5V, f CLK =.09MHz, f IN = 0Hz = 0.0 f CTOFF db f CTOFF = khz, V IN =.V P-P, f IN =.khz = 0. f CTOFF db, Pin 5 Shorted f IN = khz = 0.5 f CTOFF db to Pin f IN = 5.kHz = 0. f CTOFF db f IN = khz = f CTOFF 5... db f IN = 97.5kHz =.5 f CTOFF (LTC59I) 0 0 db f IN = 97.5kHz =.5 f CTOFF (LTC59C) 0 db f IN = khz = f CTOFF 50 db f IN = 9kHz = f CTOFF 7 0 db V S =.7V, f CLK = MHz, f IN = Hz = 0.0 f CTOFF db f CTOFF = 5.5kHz, f IN = 5kHz = 0. f CTOFF db V IN = V P-P, Pin Shorted f IN = 7kHz = 0.5 f CTOFF db to Pin, External Clock f IN =.5kHz = 0. f CTOFF db f IN = 5.5kHz = f CTOFF... db f IN =.khz =.5 f CTOFF (LTC59I) 5 db f IN =.khz =.5 f CTOFF (LTC59C) 5 50 db f IN =.5kHz = f CTOFF (LTC59I) 0 5 db f IN =.5kHz = f CTOFF (LTC59C) 0 55 db f IN =.khz = f CTOFF 0 db Filter Phase V S =.7V, f CLK = MHz, f IN = 50Hz = 0.0 f CTOFF Deg f CTOFF =.5kHz, Pin f IN =.5kHz = 0. f CTOFF 0 Deg Shorted to Pin, f IN =.5kHz = 0.5 f CTOFF 79 5 Deg External Clock f IN = 50kHz = 0. f CTOFF Deg f IN =.5kHz = f CTOFF 5 Deg f IN = 9.75kHz =.5 f CTOFF 9 Deg Filter Cutoff Accuracy R EXT = 0.k from Pin to Pin 7,.5kHz ±% when Self-Clocked V S =, Pin 5 Shorted to Pin Filter Output DC Swing V S =, Pin =.V. V P-P (Note ).9 V P-P V S = 5V, Pin = V.9 V P-P.7 V P-P V S = ±5V, Pin 5 Shorted to Pin 7, R LOAD = 0k.5 V P-P

3 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 5 C. V S = (V + =, V = 0V), f CLK =.09MHz, f CTOFF = khz, R LOAD = 0k unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX NITS Output DC Offset, Pin 5 Shorted to Pin 7 V S = ± ±5 mv (Note ) V S = 5V ± ± mv V S = ±5V ±5 mv Output DC Offset, Pin 5 Shorted to Pin 7 V S = 5 µv/ C Drift V S = 5V 5 µv/ C V S = ±5V 75 µv/ C Clock Pin Logic Thresholds V S = Min Logical.7 V when Clocked Externally Max Logical V V S = 5V Min Logical.0 V Max Logical V V S = ±5V Min Logical.0 V Max Logical V Power Supply Current f CLK = 5kHz (0k from Pin to Pin 7, V S = ma (Note ) Pin 5 Open, ), f CTOFF = khz 5 ma V S = 5V.5 5 ma ma V S = 0V.5 7 ma ma f CLK =.09MHz (0k from Pin to Pin 7, V S = ma Pin 5 Shorted to Pin, ), f CTOFF = khz ma V S = 5V 9 ma ma V S = 0V ma 7 ma Clock Feedthrough Pin 5 Open 0. mv RMS Wideband Noise Noise BW = DC to f CTOFF 95 µv RMS THD f IN = khz,.5v P-P, f CTOFF = khz 0 db Clock-to-Cutoff Frequency Ratio Max Clock Frequency V S = 5 MHz (Note ) V S = 5V 5 MHz V S = ±5V 7 MHz Min Clock Frequency V S =, 5V, T A < 5 C.5 khz (Note 5) V S = ±5V khz Input Frequency Range Aliased Components < 5dB 0.9 f CLK Hz Note : Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note : DC offset is measured with respect to Pin. Note : If the internal oscillator is used as the clock source and the divideby- or divide-by- mode is enabled, the supply current is reduced as much as 0% relative to the divide-by- mode. Note : The maximum clock frequency is arbitrarily defined as the frequency at which the filter AC response exhibits >db of gain peaking. Note 5: The minimum clock frequency is arbitrarily defined as the frequecy at which the filter DC offset changes by more than 5mV. Note : For more details refer to the Input and Output Voltage Range paragraph in the Applications Information section.

4 TYPICAL PERFOR A CE CHARACTERISTICS W 0 Gain vs Frequency Passband Gain and Group Delay vs Frequency GAIN (db) 0 50 GAIN (db) DELAY (µs) FREQENCY (khz) 59- G FREQENCY (khz) 59- GO 0 THD vs Input Frequency 50 THD vs Input Voltage THD (db) V S = 5V PIN = V V IN =.5V P-P f CTOFF = khz IN + TO OT INPT FREQENCY (khz) 59- G0 THD (db) V S = PIN =.V V S = 5V PIN = V f IN = khz f CTOFF = khz IN + TO OT INPT VOLTAGE (V P-P ) 59- G0 0 Supply Current 5V Supply Current ±5V Supply Current I SPPY (ma) EXT CLK DIV-BY- I SPPY (ma) EXT CLK DIV-BY- I SPPY (ma) 0 EXT CLK DIV-BY- DIV-BY- DIV-BY- 5 DIV-BY- DIV-BY- DIV-BY- DIV-BY f CTOFF (khz) 59- G f CTOFF (khz) 59- G f CTOFF (khz) 59- G07

5 PIN FNCTIONS IN + /IN (Pins, ): Signals can be applied to either or both input pins. The DC gain from IN + (Pin ) to OT (Pin ) is.0, and the DC gain from Pin to Pin is. The input range, input resistance and output range are described in the Applications Information section. Input voltages which exceed the power supply voltages should be avoided. Transients will not cause latchup if the current into/out of the input pins is limited to 0mA. GND (Pin ): The GND pin is the reference voltage for the filter and should be externally biased to V (.V) to maximize the dynamic range of the filter in applications using a single 5V () supply. For single supply operation, the GND pin should be bypassed with a quality ceramic capacitor to V (Pin ). The impedance of the circuit biasing the GND pin should be less than kω as the GND pin generates a small amount of AC and DC current. For dual supply operation, connect Pin to a high quality DC ground. A ground plane should be used. A poor ground will increase DC offset, clock feedthrough, noise and distortion. V /V + (Pins, 7): For, 5V and ±5V applications a quality ceramic bypass capacitor is required from V + (Pin 7) to V (Pin ) to provide the transient energy for the internal clock drivers. The bypass should be as close as possible to the IC. In dual supply applications (Pin is grounded), an additional 0. bypass from V + (Pin 7) to GND (Pin ) and V (Pin ) to GND (Pin ) is recommended. The maximum voltage difference between GND (Pin ) and V + (Pin 7) should not exceed 5.5V. DIV/CLK (Pin 5): DIV/CLK serves two functions. When the internal oscillator is enabled, DIV/CLK can be used to engage an internal divider. The internal divider is set to : when DIV/CLK is shorted to V (Pin ). The internal divider is set to : when DIV/CLK is allowed to float (a 00pF bypass to V is recommended). The internal divider is set to : when DIV/CLK is shorted to V + (Pin 7). In the divide-by- and divide-by- modes the power supply current is reduced by as much as 0%. When the internal oscillator is disabled (R X shorted to V ) DIV/CLK becomes an input pin for applying an external clock signal. For proper filter operation, the clock waveform should be a squarewave with a duty cycle as close as possible to 50% and CMOS voltages levels (see Electrical Characteristics section for voltage levels). DIV/ CLK pin voltages which exceed the power supply voltages should be avoided. Transients will not cause latchup if the fault current into/out of the DIV/CLK pin is limited to 0mA. R X (Pin ): Connecting an external resistor between the R X pin and V + (Pin 7) enables the internal oscillator. The value of the resistor determines the frequency of oscillation. The maximum recommended resistor value is 0k and the minimum is.k. The internal oscillator is disabled by shorting the R X pin to V (Pin ). (Please refer to the Applications Information section.) OT (Pin ): Filter Output. This pin can drive 0kΩ and/or 0pF loads. For larger capacitive loads, an external 00Ω series resistor is recommended. The output pin can exceed the power supply voltages by up to ±V without latchup. 5

6 BLOCK DIAGRA W IN + IN OT 0TH ORDER LINEAR PHASE FILTER NETWORK 7 V + R EXT GND POWER CONTROL R X V DIVIDER/ BFFER 5 DIV/CLK PRECISION OSCILLATOR 59- BD APPLICATIONS INFORMATION Self-Clocking Operation W The features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor. The design is optimized for V S =, f CTOFF = khz, where the filter cutoff frequency error is typically <% when a 0.% external 0k resistor is used. With different resistor values and internal divider settings, the cutoff frequency can be accurately varied from khz to khz. As shown in Figure, the divider is controlled by the DIV/CLK (Pin 5). Table summarizes the cutoff frequency vs external resistor values for the divide-by- mode. IN + OT 7 IN V + R EXT DIVIDE-BY- 5 DIVIDE-BY- f CTOFF = khz (0k/R EXT), OR Figure 00pF DIVIDE-BY- V + V 59- F0 Table. f CTOFF vs R EXT, V S =, T A = 5 C, Divide-by- Mode R EXT Typical f CTOFF Typical Variation of f CTOFF Ω* N/A ±.0% 500Ω* N/A ±.5% 0k khz ±% 0.k khz ±.0% 0.k khz ±.5% *R EXT values less than 0k can be used only in the divide-by- mode. In the divide-by- and divide-by- modes, the cutoff frequencies in Table will be lowered by and respectively. When the is in the divide-by- and divide-by- modes the power is automatically reduced. This results in up to a 0% power savings. The power reduction in the divide-by- and divide-by- modes, however, effects the fundamental oscillator frequency. Hence, the effective divide ratio will be slightly different from : or : depending on V S, T A and R EXT. Typically this error is less than % (Figures and ). The cutoff frequency is easily estimated from the equation in Figure. Examples and illustrate how to use the graphs in Figures through 7 to get a more precise estimate of the cutoff frequency. Example :, R EXT = 0k, V S =, divide-by- mode, DIV/CLK (Pin 5) connected to V + (Pin 7), T A = 5 C.

7 APPLICATIONS INFORMATION W sing the equation in Figure, the approximate filter cutoff frequency is f CTOFF = khz (0k/0k) (/) = khz. For a more precise f CTOFF estimate, use Table to get a value of f CTOFF when R EXT = 0k and use the graph in Figure to find the correct divide ratio when V S = and R EXT = 0k. Based on Table and Figure, f CTOFF = khz (0.k/0k) (/.0) =.0kHz. From Table, the part-to-part variation of f CTOFF will be ±%. From the graph in Figure 7, the 0 C to 70 C drift of f CTOFF will be 0.% to 0.%. Example :,, V S = 5V, divide-by- mode, DIV/CLK (Pin 5) connected to V (Pin ), T A = 5 C. sing the equation in Figure, the approximate filter cutoff frequency is f CTOFF = khz (0k/0k) (/) = khz. For a more precise f CTOFF estimate, use Figure to correct for the supply voltage when V S = 5V. From Table and Figure, f CTOFF = k (0k/0k) =.khz. The oscillator is sensitive to transients on the positive supply. The IC should be soldered to the PC board and the PCB layout should include a ceramic capacitor between V + (Pin 7) and V (Pin ), as close as possible to the IC to minimize inductance. Avoid parasitic capacitance on R X and avoid routing noisy signals near R X (Pin ). se NORMALIZED FILTER CTOFF R EXT = 5k R EXT = 0k R EXT = 0k NORMALIZED FILTER CTOFF V S = V S = 5V V S = 0V V SPPLY (V) TEMPERATRE ( C) 59- F0 59- F0 Figure. Filter Cutoff vs V SPPLY, Divide-by- Mode, T A = 5 C Figure. Filter Cutoff vs Temperature, Divide-by- Mode, DIVIDE RATIO R EXT = 5k R EXT = 0k R EXT = 0k NORMALIZED FILTER CTOFF V S = V S = 5V V S = 0V V SPPLY (V) TEMPERATRE ( C) 59- F0 59- F05 Figure. Typical Divide Ratio in the Divide-by- Mode, T A = 5 C Figure 5. Filter Cutoff vs Temperature, Divide-by- Mode, 7

8 APPLICATIONS INFORMATION DIVIDE RATIO W R EXT = 5k R EXT = 0k R EXT = 0k 0 V SPPLY (V) 59- F0 NORMALIZED FILTER CTOFF V S = V S = 5V V S = 0V TEMPERATRE ( C) 59- F07 Figure. Typical Divide Ratio in the Divide-by- Mode, T A = 5 C Figure 7. Filter Cutoff vs Temperature, Divide-by- Mode, a ground plane connected to V (Pin ) for single supply applications. Connect a ground plane to GND (Pin ) for dual supply applications and connect V (Pin ) to a copper trace with low thermal resistance. Input and Output Voltage Range The input signal range includes the full power supply range. The output range is typically (V + 50mV) to (V + 0.V) when using a single supply with the GND (Pin ) voltage set to.v. In other words, the output range is typically.v P-P for a supply. Similarly, the output range is typically.9v P-P for a single 5V supply when the GND (Pin ) voltage is V. For ±5V supplies, the output range is typically.5v P-P. The can be driven with a single-ended or differential signal. When driven differentially, the voltage between IN + and IN (Pin and Pin ) is filtered with a DC gain of. The single-ended output voltage OT (Pin ) is referenced to the voltage of the GND (Pin ). The common mode voltage of IN + and IN can be any voltage that keeps the input signals within the power supply range. For noninverting single-ended applications, connect IN to GND or to a quiet DC reference voltage and apply the input signal to IN +. If the input is DC coupled then the DC gain from IN + to OT will be. This is true given IN + and OT are referenced to the same voltage, i.e., GND, V or some other DC reference. To achieve the distortion levels shown in the Typical Performance Characteristics the input signal at IN + should be centered around the DC voltage at IN. The input can also be AC coupled, as shown in the Typical Applications section. For inverting single-ended filtering, connect IN + to GND or to quiet DC reference voltage. Apply the signal to IN. The DC gain from IN to OT is, assuming IN is referenced to IN + and OT is reference to GND. Refer to the Typical Performance Characteristics section to estimate the THD for a given input level. Dynamic Input Impedance The unique input sampling structure of the has a dynamic input impedance which depends on the configuration, i.e., differential or single-ended, and the clock frequency. The equivalent circuit in Figure illustrates the input impedance when the cutoff frequency is khz. For other cutoff frequencies replace the 5k value with 5k (khz/f CTOFF ). When driven with a single-ended signal into IN with IN + tied to GND, the input impedance is very high (~0MΩ). When driven with a single-ended signal into IN + with IN tied to GND, the input impedance is a 5k resistor to GND. When driven with a complementary signal whose common mode voltage is GND, the IN + input appears to have 5k to GND and the IN input appears to have 5k to GND. To make the effective IN impedance 5k when driven differentially, place a.5k resistor from IN to GND. For other cutoff frequencies use.5k (khz/

9 APPLICATIONS INFORMATION W f CTOFF ), as shown in the Typical Applications section. The typical variation in dynamic input impedance for a given clock frequency is ±0%. Wideband Noise The wideband noise of the filter is the RMS value of the device s output noise spectral density. The wideband noise data is used to determine the operating signal-tonoise at a given distortion level. The wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. Most of the wideband noise is concentrated in the filter passband and cannot be removed with post filtering (Table ). Table lists the typical wideband noise for each supply. Table. Wideband Noise vs Supply Voltage, Single Supply Bandwidth Total Integrated Noise DC to f CTOFF 0µV RMS DC to f CTOFF DC to f CLK 95µV RMS 0µV RMS Table. Wideband Noise vs Supply Voltage, f CTOFF = khz Power Supply 5V Total Integrated Noise DC to f CTOFF 95µV RMS 00µV RMS ±5V 05µV RMS Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter s OT pin (Pin ). The clock feedthrough is measured with IN + and IN (Pins and ) grounded and depends on the PC board layout and the power supply decoupling. Table shows the clock feedthrough (the RMS sum of the first harmonics) when the is self-clocked with, DIV/CLK (Pin 5) open (divide-by- mode). The clock feedthrough can be reduced with a simple RC post filter. Table. Clock Feedthrough Power Supply Feedthrough 0.mV RMS 5V 0.mV RMS ±5V 0.9mV RMS DC Accuracy DC accuracy is defined as the error in the output voltage after DC offset and DC gain errors are removed. This is similar to the definition of the integral nonlinearity in A/D converters. For example, after measuring values of V OT(DC) vs V IN(DC) for a typical, a linear regression shows that V OT(DC) = V IN(DC) V is the straight line that best fits the data. The DC accuracy describes how much the actual data deviates from this straight line (i.e., DCERROR = V OT(DC) (V IN(DC) V). In a -bit system with a full-scale value of V, the LSB is µv. Therefore, if the DCERROR of the filter is less than µv over a V range, the filter has -bit DC accuracy. Figure 9 illustrates the typical DC accuracy of the on a single 5V supply. DC Offset The output DC offset of the is trimmed to less than ±5mV. The trimming is performed with V S =.9V,.V with the filter cutoff frequency set to khz (R EXT = 0k, DIV/CLK shorted to V + ). To obtain optimum DC offset performance, appropriate PC layout techniques should be used. The filter IC should be soldered to the PC board. The power supplies should be well decoupled including a ceramic capacitor from V + (Pin 7) to V (Pin ). A ground plane should be used. Noisy signals should be isolated from the filter input pins. When the power supply is, the output DC offset should change less than ±mv when the clock frequency varies from khz to 09kHz. When the clock frequency is fixed, the output DC offset will typically change by less than ±mv (±5mV) when the power supply varies from to 5V (±5V) in the divide-by- mode. In the divide-by- or divide-by- modes, the output DC offset will typically change less than 9mV ( 7mV) when the power supply varies from to 5V (±5V). The offset is measured with respect to GND (Pin ). Aliasing Aliasing is an inherent phenomenon of sampled data filters. In lowpass filters significant aliasing only occurs when the frequency of the input signal approaches the sampling frequency or multiples of the sampling fre- 9

10 APPLICATIONS INFORMATION W quency. The samples the input signal twice every clock period. Therefore, the sampling frequency is twice the clock frequency and times the filter cutoff frequency. Input signals with frequencies near f CLK ± f CTOFF will be aliased to the passband of the filter and appear at the output unattenuated. IN + i = IN+ GND 5k IN + GND 5k + 5k + OT 59- F0 DC ERROR (µv) 0 V S = 5V T A = 5 C V IN DC (V) 59- F09 Figure Figure 9 TYPICAL APPLICATIO S Single Operation, AC Coupled Input, khz Cutoff Frequency Single, AC Coupled Input, khz Cutoff Frequency V IN.k k 0. IN + OT V OT IN V k ( )( ) khz f CTOFF = n = R EXT n =,, FOR PIN 5 AT GROND, OPEN, V TA0 GAIN (db) µs µs 0 µs 0 0k 0k 0k 0k 50k 0k 70k k 50k 0k 70k 0k 90k 00k 0k 0k 0k 0k 50k FREQENCY (Hz) GROP DELAY 59- TA0a 0

11 TYPICAL APPLICATIO S Single Supply Operation, DC Coupled, khz Cutoff Frequency Single 5V Operation, 50kHz Cutoff Frequency, DC Coupled Differential Inputs with Balanced Input Impedance.k k V IN IN + OT V OT IN V k ( )( ) khz f CTOFF = n = R EXT n =,, FOR PIN 5 AT GROND, OPEN, V + 00pF 59- TA0 5V IN LT 0-.5 OT (SOT-) GND V IN + V IN IN + OT V OT IN V + 7 R EXT =.k 0.k 5 0k ( )( ) khz f CTOFF ~ n =.k n =,, FOR PIN 5 AT GROND, OPEN, V + 5V 59- TA0 ±5V Supply Operation, DC Coupled Filter with External Clock Source 5V V IN IN + OT IN V V OT f CTOFF = f CLK / 5V 0. 5V 5V 0V f CLK 5MHz 59- TA05 Pulse Shaping Circuit for Single Operation, kbps -Level Data, khz Cutoff Filter -Level, kbps Eye Diagram ksps DATA 7.k* 0k 0k.k IN + OT 7 IN V + V OT 00mV/DIV k TA0 * SEE APPLICATIONS INFORMATION, INPT AND OTPT VOLTAGE RANGE µs/div 59- TA0 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

12 TYPICAL APPLICATIO S Pulse Shaping Circuit for Single Operation, 00kbps (00ksps) -Level Data, khz Cutoff Filter -Level, 00kbps (00ksps) Eye Diagram D 00ksps DATA D0.9k* 9.k* 0k 0k.k IN + OT 7 IN V + V OT 00mV/DIV k TA0 * SEE APPLICATIONS INFORMATION, INPT AND OTPT VOLTAGE RANGE µs/div 59- TA09 PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S Package -Lead Plastic Small Outline (Narrow 0.50) (LTC DWG # ) * ( ) ( ) ( ) 5 0 TYP (..75) ( ) (0.0.70) ( ) TYP * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.00" (0.5mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.00" (0.5mm) PER SIDE (.70) BSC ( ) ** (.0.9) SO 9 RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC0- Linear Phase, Bessel th Order Filter f CLK /f CTOFF = 75/ or 50/, Very Low Noise LTC0-7 Linear Phase, th Order Lowpass Filter f CLK /f CTOFF = 50/ or 00/, f CTOFF(MAX) = 00kHz LTC09-7 Linear Phase, th Order Lowpass Filter f CLK /f CTOFF = 5/, f CTOFF(MAX) = 00kHz, SO- LTC-7 Low Power, Linear Phase Lowpass Filter f CLK /f CTOFF = 50/ or 00/, I S =.5mA, V S = 5V LTC-7 Linear Phase, th Order Lowpass Filter f CLK /f CTOFF = 5/ or 50/, f CTOFF(MAX) = 00kHz LTC5/LTC5- niversal, th Order Active RC Filter f CTOFF(MAX) = 50kHz (LTC5) f CTOFF(MAX) = 00kHz (LTC5-) LTC5-/LTC5- Active RC, th Order Lowpass f CTOFF(MAX) = 00kHz, Very Low Noise LTC59-7 Linear Phase DC Accurate, 0th Order f CTOFF(MAX) = 00kHz, No Clock Required Linear Technology Corporation 0 McCarthy Blvd., Milpitas, CA (0)-900 FAX: (0) f LT/TP 0500 K PRINTED IN THE SA LINEAR TECHNOLOGY CORPORATION 999