FEATURES APPLICATIO S TYPICAL APPLICATIO. LT1102 High Speed, Precision, JFET Input Instrumentation Amplifier (Fixed Gain = 10 or 100) DESCRIPTIO

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1 FEATRES Slew Rate: V/μs Gain-Bandwidth Product: MHz Settling Time (.%): μs Overdrive Recovery:.μs Gain Error:.% Max Gain Drift: ppm/ C Gain Nonlinearity: ppm Max Offset Voltage (Input Output): μv Max Drift with Temperature: μv/ C Input Bias Current: pa Max Input Offset Current: pa Max Drift with Temperature (to 7 C):.pA/ C APPLICATIO S Fast Settling Analog Signal Processing Multiplexed Input Data Acquisition Systems High Source Impedance Signal Amplification from High Resistance Bridges, Capacitance Sensors, Photodetector Sensors Bridge Amplifier with < Hz Lowpass Filtering LT High Speed, Precision, JFET Input Instrumentation Amplifier (Fixed Gain = or ) DESCRIPTIO The LT is the first fast FET input instrumentation amplifier offered in the low cost, space saving -pin packages. Fixed gains of and are provided with excellent gain accuracy (.%) and non-linearity (ppm). No external gain setting resistor is required. Slew rate, settling time, gain-bandwidth product, overdrive recovery time are all improved compared to competitive high speed instrumentation amplifiers. Industry best speed performance is combined with impressive precision specifications: less than pa input bias and offset currents, μv offset voltage. nlike other FET input instrumentation amplifiers, on the LT there is no output offset voltage contribution to total error, and input bias currents do not double with every C rise in temperature. Indeed, at 7 C ambient temperature the input bias current is only pa., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO Wideband Instrumentation Amplifier with ±ma Output Current Slew Rate V = V LT 7 LT R BIAS V/DIV FPO V = V PT = ±V INTO 7Ω TO khz (R = Ω) ±V INTO Ω TO khz (R = Ω) DRIVES.nF CAP LOAD GAIN =, DEGRADED.% DE TO LT G =.μs/div FPOLT TA LT TA fb

2 LT ABSOLTE AXI RATI GS W W W Supply Voltage... ±V Differential Input Voltage... ±V Input Voltage... ±V Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: (Note ) Output Short-Circuit Duration... Indefinite Operating Temperature Range LTI... C to C LTAC/LTC... C to 7 C LTAM/LTM (OBSOLETE)... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C W PACKAGE/ORDER I FOR ATIO GROND (REF) REF G = IN 9R R 9R TOP VIEW PT 9R R V (CASE) 7 G = 9R V IN ORDER PART NMBER LTAMH LTMH LTACH LTCH GROND (REF) REF G = IN V 9R 9R R TOP VIEW LT 9 =.k 9R 9R R N PACKAGE -LEAD PDIP T JMAX = C, θ JA = C/W 7 PT G = IN V ORDER PART NMBER LTIN LTACN LTCN H PACKAGE -LEAD TO- METAL CAN OBSOLETE PACKAGE Consider the N Package for Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. J PACKAGE -LEAD CERDIP OBSOLETE PACKAGE Consider the N Package for Alternate Source LTMJ LTCJ LT POI fb

3 LT ELECTRICAL CHARACTERISTICS V S = ±V, V CM = V,, Gain = or, unless otherwise noted. LTAM/AC LTM/I/C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS G E Gain Error V O = ±V, R L = k or k....7 % G NL Gain Nonlinearity G =, R L = k ppm G =, R L = k ppm G =, RL = k or k 7 7 ppm V OS Input Offset Voltage 9 μv I OS Input Offset Current pa I B Input Bias Current ± ± ± ± pa Input Resistance Common Mode V CM = V to V Ω V CM = V to V Ω Differential Mode Ω e n Input Noise Voltage.Hz to Hz.. μv P-P Input Noise Voltage f O = Hz 7 7 nv/ Hz Density f O = Hz (Note ) 9 nv/ Hz Input Noise Current f O = Hz, Hz (Note ). fa/ Hz Density lnput Voltage Range ±. ±. ±. ±. V CMRR Common Mode k Source Imbalance, V CM = ±.V 9 97 db Rejection Ratio PSRR Power Supply V S = ± 9V to ±V db Rejection Ratio I S Supply Current.... ma V O Maximum Output R L = k ±. ±. ±. ±. V Voltage Swing R L = k ±. ±. ±. ±. V BW Bandwidth G = (Note ) khz G = (Note )...7. MHz SR Slew Rate G =, V IN = ±.V, V O = ±V 7 7 V/μs G =, V IN = ±V, V O = ±V V/μs Overdrive Recovery % Overdrive (Note ) ns Settling Time V O = V Step (Note ) G = to.%.... μs G = to.%.... μs G = to.% 7 7 μs G = to.% 9 9 μs fb

4 LT ELECTRICAL CHARACTERISTICS V S = ±V, V CM = V, Gain = or, C T A C for AM/M grades, C T A C for I grades, unless otherwise noted. LTAM LTM/I SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS G E Gain Error G =, V O = ±V, R L = k or k.... % G =, V O = ±V, R L = k or k.... % TCG E Gain Error Drift G =, R L = k or k 9 ppm/ C (Note ) G =, R L = k or k ppm/ C G NL Gain Nonlinearity G =, R L = k 7 9 ppm G =, R L = k ppm G =, R L = k or k 9 9 ppm V OS Input Offset Voltage μv ΔV OS /ΔT Input Offset Voltage Drift (Note ) μv/ C l OS Input Offset Current.. na I B Input Bias Current ± ± ±. ± na CMRR Common Mode V CM = ±.V 97 9 db Rejection Ratio PSRR Power Supply V S = ±V to ±7V 99 db Rejection Ratio I S Supply Current.. ma V O Maximal Output R L = k ±. ±. ±. ±. V Voltage Swing R L = k ±. ±. ±. ±. V V S = ±V, V CM = V, Gain = or, C T A 7 C, unless otherwise noted. LTAC LTC SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS G E Gain Error G =, V O = ±V, R L = k or k.... % G =, V O = ±V, R L = k or k..9.. % TCG E Gain Error Drift G =, R L = k or k 9 ppm/ C (Note ) G =, R L = k or k ppm/ C G NL Gain Nonlinearity G =, R L = k 9 ppm G =, R L = k ppm G =, R L = k or k ppm V OS Input Offset Voltage μv ΔV OS /ΔT Input Offset Voltage Drift (Note ) μv/ C I OS Input Offset Current pa ΔI OS /ΔT Input Offset Current Drift (Note ).. pa/ C I B Input Bias Current ± ± ± ± pa ΔI B /ΔT lnput Bias Current Drift (Note ) pa/ C CMRR Common Mode V CM = ±.V 9 97 db Rejection Ratio PSRR Power Supply V S = ±V to ±7V 7 db Rejection Ratio I S Supply Current T A = 7 C..9 ma V O Maximum Output R L = k ±. ±. ±. ±. V Voltage Swing R L = k ±. ±. ±. ±. V fb

5 LT ELECTRICAL CHARACTERISTICS Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : This parameter is tested on a sample basis only. Note : Current noise is calculated from the formula: i n = (qi B ) / where q =. 9 coulomb. The noise of source resistors up to GΩ swamps the contribution of current noise. Note : This parameter is not tested. It is guaranteed by design and by inference from the slew rate measurement. Note : Overdrive recovery is defined as the time delay from the removal of an input overdrive to the output s return from saturation to linear operation. % overdrive equals V IN = ±V (G = ) or V IN = ±mv (G = ). Note : This parameter is not tested. It is guaranteed by design and by inference from other tests. TYPICAL PERFOR A CE CHARACTERISTICS W Small Signal Response, G = (Input = mv Pulse) Small Signal Response, G = (Input = mv Pulse) Slew Rate, G = (Input = ±mv Pulse) mv/div mv/div V/DIV μs/div μs/div μs/div FPOLT TPC FPOLT TPC FPOLT TPC Settling Time, G = (Input From V to V) Settling Time, G = (Input From V to V) Settling Time, G = (Input From V to V) mv/div AT SM NODE mv/div AT SM NODE mv/div AT SM NODE μs/div μs/div FPOLT TPC FPOLT TPC Settling Time, G = (Input From V to V) mv/div AT SM NODE FPOLT TPC μs/div FPOLT TPC7 μs/div fb

6 LT TYPICAL PERFOR A CE CHARACTERISTICS W Capacitive Load Handling Output Impedance vs Frequency Gain vs Frequency OVERSHOOT (%) V S = ±V G = G = PT IMPEDANCE (Ω) V S = ±V G = G = GAIN ERROR (%)..... G = G = V S = ±V GAIN (db).. CAPACITIVE LOAD (nf). k k k M FREQENCY (Hz). k k M M FREQENCY (Hz) LT TPC LT TPC9 LT TPC PEAK-TO-PEAK PT SWING (V) k ndistorted Output vs Frequency G = R L = k k M M FREQENCY (Hz) V S = ±V G = R L = k OR k G = R L = k LT TPC RMS VOLTAGE NOISE DENSITY (nv Hz) 7 Voltage Noise vs Frequency V S = ±V /f CORNER = Hz k k k FREQENCY (Hz) LT TPC INPT BIAS CRRENT, (na) Input Bias Current Over the Common Mode Range V S = ±V T A = 7 C. COMMON MODE VOLTAGE (V) LT TPC INPT BIAS CRRENT, TO 7 C (pa) CHANGE IN OFFSET VOLTAGE (μv) Warm-p Drift V S = ±V N PACKAGE H AND J PACKAGE COMMON MODE RANGE (V) Common Mode Range vs Temperature V S = ±V G = G = G = OR SPPLY CRRENT (ma) Supply Current vs Temperature V S = ±V V S = ±V TIME AFTER POWER ON (MINTES) TEMPERATRE ( C) 7 TEMPERATRE ( C) LT TPC LT TPC LT TPC fb

7 LT TYPICAL PERFOR A CE CHARACTERISTICS W SHORT-CIRCIT CRRENT (ma) Short-Circuit Current vs Time V S = ±V T A = C T A = C TIME FROM PT SHORT TO GROND (MINTES) LT TPC7 PERCENT OF NITS Distribution of Offset Voltage V S = ±V 9 NITS TESTED IN ALL PACKAGES.... INPT OFFSET VOLTAGE (mv) LT TPC GAIN ERROR (%)..... Gain Error vs Temperature V S = ±V R L k G = G = GAIN NONLINEARITY (ppm) Gain Nonlinearity Over Temperature G = R L = k G = R L = k OR k G = R L = k 7 TEMPERATRE ( C) 7 TEMPERATRE ( C) LT TPC9 LT TPC fb 7

8 LT APPLICATIO S I FOR ATIO W In the two op amp instrumentation amplifier configuration, the first amplifier is basically in unity gain, and the second amplifier provides all the voltage gain. In the LT, the second amplifier is decompensated for gain of stability, therefore high slew rate and bandwidth are achieved. Common mode rejection versus frequency is also optimized in the G = mode, because the bandwidths of the two op amps are similar. When G =, this statement is no longer true; however, by connecting an pf capacitor between pins and, a common mode AC gain is created to cancel the inherent roll-off. From Hz to khz, CMRR versus frequency is improved by an order of magnitude. Input Protection Instrumentation amplifiers are often used in harsh environments where overload conditions can occur. The LT employs FET input transistors, consequently the differential input voltage can be ±V (with ±V supplies, ±V with ±V supplies). Some competitive instrumentation amplifiers have NPN inputs which are protected by back-to-back diodes. When the differential input Voltage exceeds ±V on these competitive devices, input current increases to milliampere level; more than ±V differential voltage can cause permanent damage. When the LT inputs are pulled below the negative supply or above the positive supply, the inputs will clamp a diode voltage below or above the supplies. No damage will occur if the input current is limited to ma. COMMON MODE REJECTION RATIO (db) Common Mode Rejection Ratio vs Frequency Gains Between and Gains between and can be achieved by connecting two equal resistors (= R X ) between pins and and pins 7 and. Gain = G = V S = ±V k k k M FREQENCY (Hz) R X R R X /9 G = pf PIN TO PIN G = LT AI The nominal value of R is.kω. The usefulness of this method is limited by the fact that R is not controlled to better than ±% absolute accuracy in production. However, on any specific unit, 9R can be measured between Pins and. fb

9 LT APPLICATIO S I FOR ATIO W Gain =,, or Instrumentation Amplifiers Differential Output Single Ended Output IN LT LT LT IN LT GAIN =, AS SHOWN GAIN =, SHORT PIN TO PIN, PIN 7 TO PIN ON BOTH DEVICES GAIN =, SHORT PIN TO PIN, PIN 7 TO PIN ON ONE DEVICE, NOT ON THE OTHER INPT REFERRED NOISE IS REDCED BY (G = OR ) LT AI Multiplexed Input Data Acquisition CHANNELS OF DIFFERENTIAL INPT SA SA SB SB 9 OR EQIVALENT DA DB LT PT DECODER AO A EN khz SIGNALS CAN BE MLTIPLEXED WITH LT IN G = LT AI Voltage Programmable Current Source is Simple and Precise Dynamic Response of the Current Source V IN ±V LT.μF A = V/DIV B = ma/div k LT A = R Ω* I K V I K = IN R HORIZ. = μs/div FPOLT AI LOAD LT AI fb 9

10 LT TYPICAL APPLICATIO S Basic Connections V NC 7 INPT LT NC V REF GAIN = V 7 INPT LT V REF GAIN = LT TA Settling Time Test Circuit Offset Nulling V P-P FLAT-TOP INPT HP-.k R Ω V V LT Ω.k V LT k.k R k FET PROBE k R = 9Ω, G = R = k, G = LT TA V R =.Ω, G = R = Ω, G = NLL RANGE = ±mv GAIN DEGRADATION.% LT TA fb

11 LT PACKAGE DESCRIPTIO H Package -Lead TO- Metal Can (. Inch PCD) (Reference LTC DWG # --) SEATING PLANE..* (..)..7 (.9 9.9) DIA.. (7.77.9). (.) MAX. (.7) MAX.. (.9.99)..** (..) GAGE PLANE REFERENCE PLANE..7 (.7 9.) TYP.. (.7.).7. (..) PIN. (.) TYP.. (.79.) INSLATING STANDOFF * LEAD DIAMETER IS NCONTROLLED BETWEEN THE REFERENCE PLANE AND THE SEATING PLANE.. ** FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS (..) H (TO-). PCD J Package -Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # --).. (..) FLL LEAD OPTION. BSC (7. BSC) CORNER LEADS OPTION ( PLCS).. (..) HALF LEAD OPTION. (.7) MIN. (.) RAD TYP. (.7) MAX 7.. (. 7.7). (.) MAX.. (..).. (..7) NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.. (..).. (..) OBSOLETE PACKAGES. (.) BSC..7 MIN J Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fb

12 LT PACKAGE DESCRIPTIO N Package -Lead PDIP (Narrow. Inch) (Reference LTC DWG # --).* (.) MAX 7. ±.* (.77 ±.).. (7..).. (..). ±. (. ±.7).. (..) ( ). (.) TYP. (.) BSC NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) MIN. ±. (.7 ±.7). (.) MIN N Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9-77 () -9 FAX: () -7 fb LT 7 REV B PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 99

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