DESCRIPTIO FEATURES TYPICAL APPLICATIO. LT1469 Dual 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier APPLICATIO S

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1 FEATURES 9MHz Gain Bandwidth, f = khz Maximum Input Offset Voltage: 5µV Settling Time: 9ns (A V =, 5µV, V Step) V/µs Slew Rate Low Distortion: 96.5dB for khz, V P-P Maximum Input Offset Voltage Drift: 3µV/ C Maximum Inverting Input Bias Current: na Minimum DC Gain: 3V/mV Minimum Output Swing into k: ±.8V Unity-Gain Stable Input Noise Voltage: 5nV/ Hz Input Noise Current:.6pA/ Hz Total Input Noise Optimized for kω < R S < kω Specified at ±5V and ±5V Supplies APPLICATIO S U Precision Instrumentation High Accuracy Data Acquisition Systems 6-Bit DAC Current-to-Voltage Converter ADC Buffer Low Distortion Active Filters LT69 Dual 9MHz, V/µs 6-Bit Accurate Operational Amplifier The LT 69 is a dual, precision high speed operational amplifier with 6-bit accuracy and 9ns settling to 5µV for V steps. This unique blend of precision and AC performance makes the LT69 the optimum choice for high accuracy applications such as DAC current-to-voltage conversion and ADC buffers. The initial accuracy and drift characteristics of the input offset voltage and inverting input bias current are tailored for inverting applications. The 9MHz gain bandwidth ensures high open-loop gain at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and DC accuracy allow full 6-bit AC and DC performance. The V/µs slew rate of the LT69 improves large signal performance compared to other precision op amps in applications such as active filters and instrumentation amplifiers. The LT69 is manufactured on Linear Technology s complementary bipolar process and is available in 8-pin PDIP and SO packages. A single version, the LT68, is also available. Photodiode Amplifiers, LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO U DESCRIPTIO 6-Bit DAC I-to-V Converter and Reference Inverter for Bipolar Output Swing (V OUT = V to V) U V REF 6 BITS DAC INPUTS k 5V / LT69 5pF k LTC597 k.µs SETTLING TIME TO LSB ON V STEP k 5pF / LT69 5V R LPF V OUT C LPF 69 TA SIGNAL/(NOISE DISTORTION) (db) Bipolar Multiplying Mode Signal-to-(Noise Distortion) DAC INPUT CODE = ALL ZEROS V REF = V P-P 5kHz FILTER 8kHz FILTER 3kHz FILTER k k k 69 TAa

2 ABSOLUTE AXI U RATI GS (Note ) W W W Total Supply Voltage (V to V )... 36V Input Current (Note )... ±ma Output Short-Circuit Duration (Note 3)... Indefinite Operating Temperature Range (Note ).. C to 85 C Specified Temperature Range (Note 5)... C to 85 C Maximum Junction Temperature... 5 C Storage Temperature Range C to 5 C Lead Temperature (Soldering, sec)... 3 C U U U W PACKAGE/ORDER I FOR ATIO OUT A IN A IN A 3 V A N PACKAGE 8-LEAD PDIP TOP VIEW B V OUT B IN B IN B S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 5 C, θ JA = 3 C/W (N8) T JMAX = 5 C, θ JA = 9 C/W (S8) Consult factory for Military grade parts. ORDER PART NUMBER LT69CS8 LT69IS8 LT69CN8 LT69IN8 S8 PART MARKING 69 69I ELECTRICAL CHARACTERISTICS, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V SUPPLY MIN TYP MAX UNITS V OS Input Offset Voltage ±5V 5 5 µv ±5V 5 µv I OS Input Offset Current ±5V to ±5V 3 ±5 na I B Inverting Input Bias Current ±5V to ±5V 3 ± na I B Noninverting Input Bias Current ±5V to ±5V ± na Input Noise Voltage.Hz to Hz ±5V to ±5V.3 µv P-P e n Input Noise Voltage Density f = khz ±5V to ±5V 5 nv/ Hz i n Input Noise Current Density f = khz ±5V to ±5V.6 pa/ Hz R IN Input Resistance Common Mode, V CM = ±.5V ±5V MΩ Differential ±5V 5 5 kω C IN Input Capacitance ±5V pf V CM Input Voltage Range (Positive) Guaranteed by CMRR ±5V V ±5V V Input Voltage Range (Negative) Guaranteed by CMRR ±5V.3.5 V ±5V..5 V CMRR Common Mode Rejection Ratio V CM = ±.5V ±5V 96 db V CM = ±.5V ±5V 96 db Minimum Supply Voltage Guaranteed by PSRR ±.5 ±.5 V PSRR Power Supply Rejection Ratio V S = ±.5V to ±5V db A VOL Large-Signal Voltage Gain V OUT = ±.5V, R L = k ±5V 3 V/mV V OUT = ±.5V, ±5V 3 V/mV V OUT = ±.5V, R L = k ±5V 8 V/mV V OUT = ±.5V, ±5V 8 V/mV V OUT Maximum Output Swing R L = k, mv Overdrive ±5V ±3. ±3.6 V, mv Overdrive ±5V ±.8 ±3.5 V R L = k, mv Overdrive ±5V ±3. ±3.7 V, mv Overdrive ±5V ±.8 ±3.6 V I OUT Maximum Output Current V OUT = ±.5V, mv Overdrive ±5V ±5 ± ma V OUT = ±.5V, mv Overdrive ±5V ±5 ± ma I SC Output Short-Circuit Current V OUT = V,.V Overdrive (Note 3) ±5V ±5 ± ma

3 ELECTRICAL CHARACTERISTICS, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V SUPPLY MIN TYP MAX UNITS SR Slew Rate A V =, (Note 6) ±5V 5 V/µs ±5V 7 V/µs FPBW Full-Power Bandwidth V Peak, (Note 7) ±5V 35 khz 3V Peak, (Note 7) ±5V 9 khz GBW Gain Bandwidth Product f = khz, ±5V 6 9 MHz ±5V MHz t r, t f Rise Time, Fall Time A V =, % to 9%,.V Step ±5V ns ±5V ns OS Overshoot A V =,.V Step ±5V 3 % ±5V 35 % t PD Propagation Delay A V =, 5% V IN to 5% V OUT,.V Step ±5V 9 ns ±5V ns t S Settling Time V Step,.%, A V = ±5V 76 ns V Step, 5µV, A V = ±5V 9 ns 5V Step,.%, A V = ±5V 77 ns THD Total Harmonic Distortion A V =, V OUT = V P-P, f = khz ±5V 96.5 db A V =, V OUT = V P-P, f = khz ±5V 5 db R OUT Output Resistance A V =, f = khz ±5V. Ω Channel Separation V OUT = ±.5V, ±5V 3 db V OUT = ±.5V, ±5V 3 db I S Supply Current Per Amplifier ±5V. 5. ma ±5V ma V OS Input Offset Voltage Match ±5V 3 5 µv ±5V 5 35 µv I B Inverting Input Bias Current Match ±5V to ±5V 8 na I B Noninverting Input Bias Current Match ±5V to ±5V 5 78 na CMRR Common Mode Rejection Match V CM = ±.5V (Note 9) ±5V 93 3 db V CM = ±.5V (Note 9) ±5V 93 5 db PSRR Power Supply Rejection Match V S = ±.5V to ±5V (Note 9) 97 5 db The denotes the specifications which apply over the temperature range C T A 7 C, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V SUPPLY MIN TYP MAX UNITS V OS Input Offset Voltage ±5V 35 µv ±5V 35 µv V OS / T Input Offset Voltage Drift (Note 8) ±5V 5 µv/ C ±5V 3 µv/ C I OS Input Offset Current ±5V to ±5V ±8 na I OS / T Input Offset Current Drift (Note 8) ±5V to ±5V 6 pa/ C I B Inverting Input Bias Current ±5V to ±5V ± na I B / T Inverting Input Bias Current Drift (Note 8) ±5V to ±5V pa/ C I B Noninverting Input Bias Current ±5V to ±5V ±6 na V CM Input Voltage Range (Positive) Guaranteed by CMRR ±5V.5 V ±5V.5 V Input Voltage Range (Negative) Guaranteed by CMRR ±5V.5 V ±5V.5 V 3

4 ELECTRICAL CHARACTERISTICS C T A 7 C, V CM = V unless otherwise noted. The denotes the specifications which apply over the temperature range SYMBOL PARAMETER CONDITIONS V SUPPLY MIN TYP MAX UNITS CMRR Common Mode Rejection Ratio V CM = ±.5V ±5V 9 db V CM = ±.5V ±5V 9 db Minimum Supply Voltage Guaranteed by PSRR ±.5 V PSRR Power Supply Rejection Ratio V S = ±.5V to ±5V 95 db A VOL Large-Signal Voltage Gain V OUT = ±.5V, R L = k ±5V V/mV V OUT = ±.5V, ±5V V/mV V OUT = ±.5V, R L = k ±5V V/mV V OUT = ±.5V, ±5V V/mV V OUT Maximum Output Swing R L = k, mv Overdrive ±5V ±.9 V, mv Overdrive ±5V ±.7 V R L = k, mv Overdrive ±5V ±.9 V, mv Overdrive ±5V ±.7 V I OUT Maximum Output Current V OUT = ±.5V, mv Overdrive ±5V ±.5 ma V OUT = ±.5V, mv Overdrive ±5V ±.5 ma I SC Output Short-Circuit Current V OUT = V,.V Overdrive (Note 3) ±5V ±7 ma SR Slew Rate A V =, (Note 6) ±5V 3 V/µs ±5V 9 V/µs GBW Gain Bandwidth Product f = khz, ±5V 55 MHz ±5V 5 MHz Channel Separation V OUT = ±.5V, ±5V 98 db V OUT = ±.5V, ±5V 98 db I S Supply Current Per Amplifier ±5V 6.5 ma ±5V 6.3 ma V OS Input Offset Voltage Match ±5V 6 µv ±5V 6 µv I B Inverting Input Bias Current Match ±5V to ±5V 38 na I B Noninverting Input Bias Current Match ±5V to ±5V 8 na CMRR Common Mode Rejection Match V CM = ±.5V (Note 9) ±5V 9 db V CM = ±.5V (Note 9) ±5V 9 db PSRR Power Supply Rejection Match V S = ±.5V to ±5V (Note 9) 9 db The denotes the specifications which apply over the temperature range C T A 85 C, V CM = V unless otherwise noted. (Note 5) SYMBOL PARAMETER CONDITIONS V SUPPLY MIN TYP MAX UNITS V OS Input Offset Voltage ±5V 5 µv ±5V 5 µv V OS / T Input Offset Voltage Drift (Note 8) ±5V 6 µv/ C ±5V 5 µv/ C I OS Input Offset Current ±5V to ±5V ± na I OS / T Input Offset Current Drift (Note 8) ±5V to ±5V pa/ C I B Inverting Input Bias Current ±5V to ±5V ± na I B / T Inverting Input Bias Current Drift (Note 8) ±5V to ±5V 8 pa/ C I B Noninverting Input Bias Current ±5V to ±5V ±8 na

5 ELECTRICAL CHARACTERISTICS LT69 The denotes the specifications which apply over the temperature range C T A 85 C, V CM = V unless otherwise noted. (Note 5) SYMBOL PARAMETER CONDITIONS V SUPPLY MIN TYP MAX UNITS V CM Input Voltage Range (Positive) Guaranteed by CMRR ±5V.5 V ±5V.5 V Input Voltage Range (Negative) Guaranteed by CMRR ±5V.5 V ±5V.5 V CMRR Common Mode Rejection Ratio V CM = ±.5V ±5V 9 db V CM = ±.5V ±5V 9 db Minimum Supply Voltage Guaranteed by PSRR ±.5 V PSRR Power Supply Rejection Ratio V S = ±.5V to ±5V 93 db A VOL Large-Signal Voltage Gain V OUT = ±,5V, R L = k ±5V 75 V/mV V OUT = ±.5V, ±5V 75 V/mV V OUT = ±.5V, R L = k ±5V 75 V/mV V OUT = ±.5V, ±5V 75 V/mV V OUT Maximum Output Swing R L = k, mv Overdrive ±5V ±.8 V, mv Overdrive ±5V ±.6 V R L = k, mv Overdrive ±5V ±.8 V, mv Overdrive ±5V ±.6 V I OUT Maximum Output Current V OUT = ±.5V, mv Overdrive ±5V ±7 ma V OUT = ±.5V, mv Overdrive ±5V ±7 ma I SC Output Short-Circuit Current V OUT = V,.V Overdrive (Note 3) ±5V ± ma SR Slew Rate A V =, (Note 6) ±5V 9 V/µs ±5V 6 V/µs GBW Gain Bandwidth Product f = khz, ±5V 5 MHz ±5V MHz Channel Separation V OUT = ±.5V, ±5V 96 db V OUT = ±.5V, ±5V 96 db I S Supply Current Per Amplifier ±5V 7 ma ±5V 6.8 ma V OS Input Offset Voltage Match ±5V 8 µv ±5V 8 µv I B Inverting Input Bias Current Match ±5V to ±5V 78 na I B Noninverting Input Bias Current Match ±5V to ±5V 58 na CMRR Common Mode Rejection Match V CM = ±.5V (Note 9) ±5V 89 db V CM = ±.5V (Note 9) ±5V 89 db PSRR Power Supply Rejection Match V S = ±.5V to ±5V (Note 9) 9 db Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : The inputs are protected by back-to-back diodes and two Ω series resistors. If the differential input voltage exceeds.7v, the input current should be limited to less than ma. Input voltages outside the supplies will be clamped by ESD protection devices and input currents should also be limited to less than ma. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. Note : The LT69C and LT69I are guaranteed functional over the operating temperature range of C to 85 C. Note 5: The LT69C is guaranteed to meet specified performance from C to 7 C and is designed, characterized and expected to meet specified performance from C to 85 C but is not tested or QA sampled at these temperatures. The LT69I is guaranteed to meet specified performance from C to 85 C. Note 6: Slew rate is measured between ±8V on the output with ±V swing for ±5V supplies and ±V on the output with ±3V swing for ±5V supplies. Note 7: Full-power bandwidth is calculated from the slew rate. FPBW = SR/πV P. Note 8: This parameter is not % tested. Note 9: CMRR and PSRR are defined as follows: ) CMRR and PSRR are measured in µv/v on each amplifier; ) the difference between the two sides is calculated in µv/v; 3) the result is converted to db. 5

6 TYPICAL PERFOR A CE CHARACTERISTICS U W Distribution of Input Offset Voltage Distribution of Inverting Input Bias Current Supply Current vs Supply Voltage and Temperature PERCENTAGE OF UNITS (%) 5 3 PERCENTAGE OF UNITS (%) 3 SUPPLY CURRENT (ma) C 5 C C INPUT OFFSET VOLTAGE (µv) INVERTING INPUT BIAS CURRENT (na) 5 5 SUPPLY VOLTAGE (±V) 69 G37 69 G38 69 G INPUT VOLTAGE NOISE (nv/ Hz) Input Noise Spectral Density i n e n A V = R S = k FOR i n. INPUT CURRENT NOISE (pa/ Hz) VOLTAGE NOISE (nv/div).hz to Hz Voltage Noise TOTAL NOISE VOLTAGE (nv/ Hz) Total Noise vs Unmatched Source Resistance f = khz TOTAL NOISE R S RESISTOR NOISE ONLY. k k k TIME (s/div) 69 G6. k k k SOURCE RESISTANCE, R S (Ω) 69 G5 69 G36 INPUT BIAS CURRENT (na) 3 3 Input Bias Current vs Temperature I B I B TEMPERATURE ( C) INPUT BIAS CURRENT (na) Input Bias Current vs Input Common Mode Voltage I B I B 5 5 INPUT COMMON MODE VOLTAGE (V) 5 COMMON MODE RANGE (V) V V Input Common Mode Range vs Supply Voltage V OS < µv SUPPLY VOLTAGE (±V) G 69 G3 69 G 6

7 TYPICAL PERFOR A CE CHARACTERISTICS U W OUTPUT VOLTAGE SWING (V) V 3 3 V Output Voltage Swing vs Supply Voltage R L = k R L = k 5 5 SUPPLY VOLTAGE (±V) V.5 OUTPUT VOLTAGE SWING (V) V.5 Output Voltage Swing vs Load Current 5 C 85 C C C 85 C 5 C OUTPUT CURRENT (ma) OUTPUT SHORT-CIRCUIT CURRENT (ma) Output Short-Circuit Current vs Temperature V IN = ±.V SOURCE SINK TEMPERATURE ( C) 69 G 69 G 69 G Settling Time to.% vs Output Step, Settling Time to.% vs Output Step, Settling Time to 5µV vs Output Step OUTPUT STEP (V) R L = k A V = A V = A V = A V = OUTPUT STEP (V) R L = k A V = A V = A V = A V = OUTPUT STEP (V) A V = R F = R G = k C F = 8pF 6 8 SETTLING TIME (ns) SETTLING TIME (ns) 6 8 SETTLING TIME (ns) 69 G3 69 G 69 G5 OPEN-LOOP GAIN (db) Open-Loop Gain vs Resistive Load OPEN-LOOP GAIN (db) Open-Loop Gain vs Temperature GAIN (db) 8 6 Open-Loop Gain vs Frequency A V = R F = R G = 5.k C F = 5pF k k LOAD RESISTANCE (Ω) TEMPERATURE ( C) k k k M M M 69 G8 69 G9 69 G39 7

8 TYPICAL PERFOR A CE CHARACTERISTICS GAIN (db) Open-Loop Gain and Phase vs Frequency PHASE U W ±5V ±5V 3 GAIN ±5V A V = R F = R G = 5.k ±5V C F = 5pF 6 k k M M M 69 G6 8 6 PHASE (DEG) GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Supply Voltage A V = R F = R G = 5.k C F = 5pF GAIN BANDWIDTH PHASE MARGIN 5 5 SUPPLY VOLTAGE (±V) 69 G PHASE MARGIN (DEG) GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Temperature PHASE MARGIN GAIN BANDWIDTH TEMPERATURE ( C) 69 G PHASE MARGIN (DEG) GAIN (db) Gain vs Frequency, A V = Gain vs Frequency, A V = Gain vs Frequency, A V = 5 TA = 5 C A V = R 3 L = k 3 5 k M M M 69 G GAIN (db) A V = C F = 5pF 5 k R F = R G = 5.k R F = R G = k M M M 69 G3 GAIN (db) VS = ±5V A V = NO R L k pf 5pF pf M M M pf 69 G Gain vs Frequency, A V = Slew Rate vs Supply Voltage Slew Rate vs Temperature GAIN (db) VS = ±5V A V = R F = R G = 5.k 8 C F = 5pF NO R L 6 pf 5pF 3pF pf SLEW RATE (V/µs) A V = SR SR SLEW RATE (V/µs) A V = SR SR 6 k M M M 5 5 SUPPLY VOLTAGE (±V) TEMPERATURE ( C) 69 G5 69 G6 69 G7 8

9 TYPICAL PERFOR A CE CHARACTERISTICS U W POWER SUPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency PSRR PSRR k k k M M M 69 G COMMON MODE REJECTION RATIO (db) 8 6 Common Mode Rejection Ratio vs Frequency k k k M M 69 G M CHANNEL SEPARATION (db) 8 6 Channel Separation vs Frequency k k k M M M 69 G39 OUTPUT VOLTAGE SWING (V P-P ) Undistorted Output Swing vs Frequency, THD < % A V = FREQUENCY (khz) A V = OUTPUT VOLTAGE SWING (VP-P) Undistorted Output Swing vs Frequency, 5 THD < % A V = A V = FREQUENCY (khz) OUTPUT IMPEDANCE (Ω).. Output Impedance vs Frequency A V = A V = A V =. k k M M M 69 G33 69 G3 69 G9 TOTAL HARMONIC DISTORTION (db) Total Harmonic Distortion vs Frequency A V = V OUT = V P-P k k k 69 G8 THD NOISE (db) Total Harmonic Distortion Noise vs Amplitude A V = R L = 6Ω f = khz NOISE BW = 8kHz. OUTPUT SIGNAL (V RMS ) 69 G9 OFFSET VOLTAGE DRIFT (µv) Warm-Up Drift vs Time N8 ±5V S-8 ±5V N8 ±5V S-8 ±5V 6 8 TIME AFTER POWER UP (s) 69 G7 9

10 TYPICAL PERFOR A CE CHARACTERISTICS U W Small-Signal Transient, A V = Small-Signal Transient, A V = 69 G3 69 G3 Large-Signal Transient, A V = Large-Signal Transient, A V = 69 G3 69 G35 APPLICATIO S I FOR Layout and Passive Components ATIO U W U U The LT69 requires attention to detail in board layout in order to maximize DC and AC performance. For best AC results (for example, fast settling time) use a ground plane, short lead lengths and RF quality bypass capacitors (.µf to.µf) in parallel with low ESR bypass capacitors (µf to µf tantalum). For best DC performance, use star grounding techniques, equalize input trace lengths and minimize leakage (e.g.,.5gω of leakage between an input and a 5V supply will generate na equal to the maximum I B specification). Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: for inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below). Microvolt level error voltages can also be generated in the external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the contacts to the inputs can exceed the inherent drift of the amplifier. Air currents over device leads should be minimized, package leads should be short and the two input leads should be as close together as possible and maintained at the same temperature.

11 APPLICATIO S I FOR ATIO U W U U The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause peaking or even oscillations. For feedback resistors greater than k, a feedback capacitor of value C F > R G C IN /R F should be used to cancel the input pole and optimize dynamic performance. For applications where the DC noise gain is one, and a large feedback resistor is used, C F should be greater than or equal to C IN. An example would be a DAC I-to-V converter as shown on the front page of the data sheet where the DAC can have many tens of picofarads of output capacitance. Another example would be a gain of with 5k resistors; a 5pF to pf capacitor should be added across the feedback resistor. Input Considerations Each input of the LT69 is protected with a Ω series resistor and back-to-back diodes across the bases of the input devices. If large differential input voltages are anticipated, limit the input current to less than ma with an external series resistor. Each input also has two ESD clamp diodes one to each supply. If an input is driven beyond the supply, limit the current with an external resistor to less than ma. The LT69 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common mode voltage to minimize errors in inverting applications such as I-to-V converters. The noninverting input current is not trimmed and has a wider variation and therefore a larger maximum value. As the input offset current can be greater than either input current, the use of balanced source resistance is NOT recommended as it actually degrades DC accuracy and also increases noise. The input bias currents vary with common mode voltage. The cancellation circuitry was not designed to track this common mode voltage because the settling time would have been adversely affected. The LT69 inputs can be driven to the negative supply and to within.5v of the positive supply without phase reversal. As the input moves closer than.5v to the positive supply, the output reverses phase. Total Input Noise The total input noise of the LT69 is optimized for a source resistance between k and k. Within this range, the total input noise is dominated by the noise of the source resistance itself. When the source resistance is below k, voltage noise of the amplifier dominates. When the source resistance is above k, the input noise current is the dominant contributor. C F V R G R F V IN C IN / LT69 V OUT 69 F IN R Ω Q Q R Ω IN Figure. Nulling Input Capacitance V 69 F Figure. Input Stage Protection

12 APPLICATIO S I FOR ATIO U W U U Capacitive Loading The LT69 drives capacitive loads of up to pf in unitygain and 3pF in a gain of. When there is a need to drive a larger capacitive load, a small series resistor should be inserted between the output and the load. In addition, a capacitor should be added between the output and the inverting input as shown in Figure 3. Settling Time The LT69 is a single stage amplifier with an optimal thermal layout that leads to outstanding settling performance. Measuring settling even at the -bit level is very challenging, and at the 6-bit level requires a great deal of subtlety and expertise. Fortunately, there are two excellent Linear Technology reference sources for settling measurements Application Notes 7 and 7. Appendix B of AN7 is a vital primer on -bit settling measurements and AN7 extends the state-of-the-art while concentrating on settling time with a 6-bit current output DAC input. The settling of the DAC I-to-V converter on the front page was measured using the exact methods of AN7. The optimum nulling of the DAC output capacitance requires 5pF across the k feedback resistor. The theoretical limit for 6-bit settling is. times this RC time constant or µs. The actual settling time is.µs at the output of the LT69. The RC output noise filter adds a slight settling time delay but reduces the noise bandwidth to.6mhz which increases the output resolution for 6-bit accuracy. R F R O ( R F /R G )/(π C L 5MHz) R F R O C F = (R O /R F )C L R G V IN C F / LT69 RO V OUT C L 69 F3 Figure 3. Driving Capacitive Loads

13 TYPICAL APPLICATIO S U Ultralow Distortion Balanced Audio Line Driver k / LT36.k pf 33.Ω INPUT k / LT69 pf k 3.Ω 8pF 5 FEET SHIELDED TWISTED PAIR CABLE 6Ω Z IN = kω k / LT69 3.Ω 8pF THD N MEASURED HERE.k GAIN = 6dB pf 33.Ω PARALLEL COMPOSITE TOPOLOGY: LT36 PROVIDES OUTPUT CURRENT; LT69 PRESERVES LINEARITY k / LT36.3k pf TOTAL HARMONIC DISTORTION NOISE V OUT FREQUENCY MEASUREMENT BANDWIDTH.5% V RMS khz khz.8% V RMS Hz TO khz 8kHz.6% 6dBu khz khz *dbu = milliwatt into 6Ω 69 TA3 3

14 TYPICAL APPLICATIO S U Extending 6-Bit DAC Performance to V Output Swing µf 5V 5Ω 33Ω V REF 6 BITS LTC597 R FB V OUT = V P-P I OUT = 5mA THD N = 9dB at Hz pf / LT69 R SELECT *** TYPICAL 6Ω k 9.99k** 5V 33pF / LT69 5V 5k 5k M M Q N55 Q5 N N8 N8 Q6 N97 k k Q3 N3* 7Ω 7Ω Q3 N55* OUTPUT * HEAT SINK ** VISHAY S RESISTOR.% *** % METAL FILM RESISTOR 5Ω Q N3 33Ω NOTE: FOR FURTHER EXPLANATION, REFER TO APPLICATION NOTE 7, APPENDIX H µf 5V 5k** 5k** 5k** 5k** 5pF 69 TA W SI PLIFIED SCHE ATIC W V I I I5 Q8 Q9 Q OUT IN Q Q IN Q5 Q6 Q7 Q Q3 Q BIAS C I3 I I6 V 69 SS

15 PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow.3) (LTC DWG # 5-8-5).* (.6) MAX ±.5* (6.77 ±.38) ( ).5.65 (.3.65).3 ±.5 (3.3 ±.7).9.5 (.9.38) ( ).65 (.65) TYP. (.5) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED. INCH (.5mm).5 (3.75) MIN.8 ±.3 (.57 ±.76). (.58) MIN N8 98 S8 Package 8-Lead Plastic Small Outline (Narrow.5) (LTC DWG # 5-8-6).89.97* (.8 5.) ( ).5.57** ( ) 3.8. (.3.5).. (.5.58) 5 8 TYP (.36.75).. (..5).6.5 (.6.7) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.5mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.5mm) PER SIDE..9 ( ) TYP.5 (.7) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 98 5

16 TYPICAL APPLICATIO U 6-Bit Accurate Single Ended to Differential ADC Buffer V IN k R S 5V / LT69 5V pf k / LT69 Ω 3pF 3pF Ω IN IN 5V LTC6 5V 69 TA 6 BITS 333ksps ADC OUTPUTS AMPLITUDE (db) Point FFT of ADC Output f SAMPLE = 333ksps V IN = ±.5V f IN = khz FREQUENCY (khz) 69 TAa RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT67 Precision Instrumentation Amplifier Single Resistor Gain Set,.% Max Gain Error, ppm Max Gain Nonlinearity LT68 Single 9MHz, V/µs, 6-Bit Accurate Op Amp 75µV Max V OS, Single Version of LT69 LTC595/LTC596 6-Bit Serial Multiplying I OUT DAC ±LSB Max INL/DNL, Low Glitch, DAC83 6-Bit Upgrade LTC597 6-Bit Parallel Multiplying I OUT DAC ±LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors LTC6 6-Bit, 333ksps Sampling ADC ±.5V Input, SINAD = 9dB, THD = db LTC65 Single 5V, 6-Bit, ksps Sampling ADC Low Power, ±V Inputs, Parallel/Byte Interface 6 69f LT/TP 8 K PRINTED IN USA Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA (8)3-9 FAX: (8) LINEAR TECHNOLOGY CORPORATION