FEATURES DESCRIPTIO Low Noise Voltage: 0.95nV/ Hz (100kHz) Gain Bandwidth Product: LT6200/LT MHz AV = 1 LT MHz LT

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1 LT62/LT62- LT62-1/LT621 16MHz, Rail-to-Rail Input and Output,.9nV/ Hz Low Noise, Op Amp Family FEATURES Low Noise Voltage:.9nV/ Hz (1kHz) Gain Bandwidth Product: LT62/LT621 16MHz A V = 1 LT62-8MHz A V LT GHz A V 1 Low Distortion: 8dB at 1MHz, R L = 1Ω Dual LT621 in Tiny DFN Package Input Common Mode Range Includes Both Rails Output Swings Rail-to-Rail Low Offset Voltage: 1mV Max Wide Supply Range: 2.V to 12.6V Output Current: 6mA Min SOT-23 and SO-8 Packages Operating Temperature Range 4 C to 8 C Power Shutdown, Thermal Shutdown APPLICATIO S U Transimpedance Amplifiers Low Noise Signal Processing Active Filters Rail-to-Rail Buffer Amplifiers Driving A/D Converters DESCRIPTIO U The LT 62/LT621 are single and dual ultralow noise, rail-to-rail input and output unity gain stable op amps that feature.9nv/ Hz noise voltage. These amplifiers combine very low noise with a 16MHz gain bandwidth, V/µs slew rate and are optimized for low voltage signal conditioning systems. A shutdown pin reduces supply current during standby conditions and thermal shutdown protects the part from overload conditions. The LT62-/LT62-1 are single amplifiers optimized for higher gain applications resulting in higher gain bandwidth and slew rate. The LT62 family maintains its performance for supplies from 2.V to 12.6V and are specified at 3V, V and ±V. For compact layouts the LT62/LT62-/LT62-1 are available in the 6-lead ThinSOT TM and the 8-pin SO package. The dual LT621 is available in an 8-pin SO package with standard pinouts as well as a tiny, dual fine pitch leadless package (DFN). These amplifiers can be used as plug-in replacements for many high speed op amps to improve input/output range and noise performance., LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO U Single Supply, 1.nV/ Hz, Photodiode Amplifier V C F 6 A V = 1 V O = 2V P-P V S = ±2.V Distortion vs Frequency PHOTO DIODE I PD PHILIPS BF862 1k 1k + LT62 R F V OUT 2V +I PD R F DISTORTION (dbc) HD2, HD2, R L = 1Ω HD3, HD3, R L = 1Ω 1k.1µF 11 1k 1M 1M 62 TA1 62 G3 621fa 1

2 LT62/LT62- LT62-1/LT621 ABSOLUTE AXI U RATI GS W W W Total Supply Voltage (V + to V ) V Total Supply Voltage (V + to V ) (LT621DD)... 7V Input Current (Note 2)... ±4mA Output Short-Circuit Duration (Note 3)... Indefinite Pin Current While Exceeding Supplies (Note 12)... ±3mA Operating Temperature Range (Note 4)... 4 C to 8 C U (Note 1) Specified Temperature Range (Note )... 4 C to 8 C Junction Temperature... 1 C Junction Temperature (DD Package) C Storage Temperature Range... 6 C to 1 C Storage Temperature Range (DD Package)... 6 C to 12 C Lead Temperature (Soldering, 1 sec)... 3 C U U W PACKAGE/ORDER I FOR ATIO OUT 1 V 2 +IN 3 TOP VIEW 6 V + S6 PACKAGE 6-LEAD PLASTIC SOT-23 SHDN 4 IN T JMAX = 1 C, θ JA = 16 C/W (Note 1) OUT A IN A +IN A V A TOP VIEW DD PACKAGE 8-LEAD (3mm 3mm) PLASTIC DFN V + OUT B IN B +IN B T JMAX = 12 C, θ JA = 16 C/W (NOTE 3) UNDERSIDE METAL CONNECTED TO V B ORDER PART NUMBER LT62CS6 LT62IS6 LT62CS6- LT62IS6- LT62CS6-1 LT62IS6-1 S6 PART MARKING* LTJZ LTACB LTACC ORDER PART NUMBER LT621CDD DD PART MARKING* LADG SHDN IN +IN V OUT A IN A +IN A V TOP VIEW S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 1 C, θ JA = 1 C/W TOP VIEW S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 1 C, θ JA = 1 C/W + NC V + OUT NC V + OUT B IN B +IN B ORDER PART NUMBER LT62CS8 LT62IS8 LT62CS8- LT62IS8- LT62CS8-1 LT62IS8-1 S8 PART MARKING 62 62I 62 62I 621 2I1 ORDER PART NUMBER LT621CS8 LT621IS8 S8 PART MARKING I *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges fa

3 ELECTRICAL CHARACTERISTICS LT62/LT62- LT62-1/LT621, V S = V, V; V S = 3V, V; V CM = V OUT = half supply, V SHDN = OPEN, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V S = V, V CM =Half Supply.1 1 mv V S = 3V, V CM = Half Supply.9 2. mv V S = V, V CM = V + to V.6 2 mv V S = 3V, V CM = V + to V mv Input Offset Voltage Match V CM = Half Supply mv (Channel-to-Channel) (Note 11) V CM = V to V mv I B Input Bias Current V CM = Half Supply 4 1 µa V CM = V µa V CM = V 23 µa I B I B Shift V CM = V to V µa I B Match (Channel-to-Channel) (Note 11) V CM = V to V +.3 µa I OS Input Offset Current V CM = Half Supply.1 4 µa V CM = V µa V CM = V.4 µa Input Noise Voltage.1Hz to 1Hz 6 nv P-P e n Input Noise Voltage Density f = 1kHz, V S = V 1.1 nv/ Hz f = 1kHz, V S = V nv/ Hz i n Input Noise Current Density, Balanced Source f = 1kHz, V S = V 2.2 pa/ Hz Unbalanced Source f = 1kHz, V S = V 3. pa/ Hz Input Resistance Common Mode.7 MΩ Differential Mode 2.1 kω C IN Input Capacitance Common Mode 3.1 pf Differential Mode 4.2 pf A VOL Large-Signal Gain V S = V, V O =.V to 4.V, to V S / V/mV V S = V, V O = 1V to 4V, R L = 1Ω to V S / V/mV V S = 3V, V O =.V to 2.V, to V S / V/mV CMRR Common Mode Rejection Ratio V S = V, V CM = V to V db V S = V, V CM = 1.V to 3.V db V S = 3V, V CM = V to V db CMRR Match (Channel-to-Channel) (Note 11) V S = V, V CM = 1.V to 3.V 8 1 db PSRR Power Supply Rejection Ratio V S = 2.V to 1V, LT621DD V S = 2.V to 7V 6 68 db PSRR Match (Channel-to-Channel) (Note 11) V S = 2.V to 1V, LT621DD V S = 2.V to 7V 6 1 db Minimum Supply Voltage (Note 6) 2. V V OL Output Voltage Swing LOW (Note 7) No Load 9 mv I SINK = ma 1 mv V S = V, I SINK = 2mA 1 29 mv V S = 3V, I SINK = 2mA 16 3 mv V OH Output Voltage Swing HIGH (Note 7) No Load 11 mv I SOURCE = ma 9 19 mv V S = V, I SOURCE = 2mA 22 4 mv V S = 3V, I SOURCE = 2mA 24 4 mv I SC Short-Circuit Current V S = V ±6 ±9 ma V S = 3V ± ±8 ma I S Supply Current per Amplifier V S = V ma V S = 3V 1 18 ma Disabled Supply Current per Amplifier V SHDN =.3V ma I SHDN SHDN Pin Current V SHDN =.3V 2 28 µa V L V SHDN Pin Input Voltage LOW.3 V V H V SHDN Pin Input Voltage HIGH V +. V 621fa 3

4 LT62/LT62- LT62-1/LT621 ELECTRICAL CHARACTERISTICS, V S = V, V; V S = 3V, V; V CM = V OUT = half supply, V SHDN = OPEN, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Shutdown Output Leakage Current V SHDN =.3V.1 7 µa t ON Turn-On Time V SHDN =.3V to 4.V, R L = 1Ω, V S = V 13 ns t OFF Turn-Off Time V SHDN = 4.V to.3v, R L = 1Ω, V S = V 18 ns GBW Gain Bandwidth Product Frequency = 1MHz, V S = V 14 MHz LT62-7 MHz LT MHz SR Slew Rate V S = V, A V = 1,, V O = 4V V/µs 4 V S = V, A V = 1,, V O = 4V LT62-21 V/µs LT V/µs FPBW Full Power Bandwidth (Note 9) V S = V, V OUT = 3V P-P (LT62) MHz t S Settling Time (LT62, LT621).1%, V S = V, V STEP = 2V, A V = 1, 16 ns The denotes the specifications which apply over C < T A < 7 C temperature range. V S = V, V; V S = 3V, V; V CM = V OUT = half supply, V SHDN = OPEN, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V S = V, V CM = Half Supply mv V S = 3V, V CM = Half Supply mv V S = V, V CM = V + to V.3 3 mv V S = 3V, V CM = V + to V 1. 4 mv Input Offset Voltage Match V CM = Half Supply mv (Channel-to-Channel) (Note 11) V CM = V to V mv V OS TC Input Offset Voltage Drift (Note 8) V CM = Half Supply 2. 8 µv/ C I B Input Bias Current V CM = Half Supply 4 1 µa V CM = V µa V CM = V 23 µa I B Match (Channel-to-Channel) (Note 11) V CM = V to V +. 6 µa I B I B Shift V CM = V to V µa I OS Input Offset Current V CM = Half Supply.1 4 µa V CM = V µa V CM = V.4 µa A VOL Large-Signal Gain V S = V, V O =.V to 4.V, to V S / V/mV V S = V, V O = 1.V to 3.V,R L = 1Ω to V S / V/mV V S = 3V, V O =.V to 2.V, to V S / V/mV CMRR Common Mode Rejection Ratio V S = V, V CM = V to V db V S = V, V CM = 1.V to 3.V 8 1 db V S = 3V, V CM = V to V db CMRR Match (Channel-to-Channel) (Note 11) V S = V, V CM = 1.V to 3.V 8 1 db PSRR Power Supply Rejection Ratio V S = 3V to 1V, LT621DD V S = 3V to 7V 6 6 db PSRR Match (Channel-to-Channel) (Note 11) V S = 3V to 1V, LT621DD V S = 3V to 7V 6 1 db Minimum Supply Voltage (Note 6) 3 V V OL Output Voltage Swing LOW (Note 7) No Load 12 6 mv I SINK = ma 11 mv V S = V, I SINK = 2mA mv V S = 3V, I SINK = 2mA mv V OH Output Voltage Swing HIGH (Note 7) No Load 6 12 mv I SOURCE = ma mv V S = V, I SOURCE = 2mA mv V S = 3V, I SOURCE = 2mA mv 621fa

5 LT62/LT62- LT62-1/LT621 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over C < T A < 7 C temperature range. V S = V, V; V S = 3V, V; V CM = V OUT = half supply, V SHDN = OPEN, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I SC Short-Circuit Current V S = V ±6 ±9 ma V S = 3V ±4 ±7 ma I S Supply Current per Amplifier V S = V 2 23 ma V S = 3V ma Disabled Supply Current per Amplifier V SHDN =.3V ma I SHDN SHDN Pin Current V SHDN =.3V µa V L V SHDN Pin Input Voltage LOW.3 V V H V SHDN Pin Input Voltage HIGH V +. V Shutdown Output Leakage Current V SHDN =.3V.1 7 µa t ON Turn-On Time V SHDN =.3V to 4.V, R L = 1Ω, V S = V 13 ns t OFF Turn-Off Time V SHDN = 4.V to.3v, R L = 1Ω, V S = V 18 ns SR Slew Rate V S = V, A V = 1,, V O = 4V V/µs A V = 1,, V O = 4V LT62-19 V/µs LT V/µs FPBW Full Power Bandwidth (Note 9) V S = V, V OUT = 3V P-P (LT62) MHz The denotes the specifications which apply over 4 C < T A < 8 C temperature range. Excludes the LT621 in the DD package (Note 3). V S = V, V; V S = 3V, V; V CM = V OUT = half supply, V SHDN = OPEN, unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V S = V, V CM = Half Supply.2 1. mv V S = 3V, V CM = Half Supply mv V S = V, V CM = V + to V.3 3. mv V S = 3V, V CM = V + to V mv Input Offset Voltage Match V CM = Half Supply.2 2 mv (Channel-to-Channel) (Note 11) V CM = V to V mv V OS TC Input Offset Voltage Drift (Note 8) V CM = Half Supply µv/ C I B Input Bias Current V CM = Half Supply 4 1 µa V CM = V µa V CM = V 23 µa I B I B Shift V CM = V to V µa I B Match (Channel-to-Channel) (Note 11) V CM = V to V µa I OS Input Offset Current V CM = Half Supply.1 4 µa V CM = V µa V CM = V.4 µa A VOL Large-Signal Gain V S = V, V O =.V to 4.V, to V S /2 4 7 V/mV V S = V, V O = 1.V to 3.V, R L = 1Ω to V S / V/mV V S = 3V, V O =.V to 2.V, to V S / V/mV CMRR Common Mode Rejection Ratio V S = V, V CM = V to V db V S = V, V CM = 1.V to 3.V 8 1 db V S = 3V, V CM = V to V db CMRR Match (Channel-to-Channel) (Note 11) V S = V, V CM = 1.V to 3.V 7 1 db PSRR Power Supply Rejection Ratio V S = 3V to 1V 6 68 db PSRR Match (Channel-to-Channel) (Note 11) V S = 3V to 1V 6 1 db Minimum Supply Voltage (Note 6) 3 V V OL Output Voltage Swing LOW (Note 7) No Load 18 7 mv I SINK = ma 6 12 mv V S = V, I SINK = 2mA mv V S = 3V, I SINK = 2mA mv 621fa

6 LT62/LT62- LT62-1/LT621 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over 4 C < T A < 8 C temperature range. Excludes the LT621 in the DD package (Note 3). V S = V, V; V S = 3V, V; V CM = V OUT = half supply, V SHDN = OPEN, unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OH Output Voltage Swing HIGH (Note 7) No Load 6 12 mv I SOURCE = ma mv V S = V, I SOURCE = 2mA 27 4 mv V S = 3V, I SOURCE = 2mA 28 mv I SC Short-Circuit Current V S = V ± ±8 ma V S = 3V ±3 ±6 ma I S Supply Current per Amplifier V S = V ma V S = 3V 2 23 ma Disabled Supply Current per Amplifier V SHDN =.3V ma I SHDN SHDN Pin Current V SHDN =.3V 22 3 µa V L V SHDN Pin Input Voltage LOW.3 V V H V SHDN Pin Input Voltage HIGH V +. V Shutdown Output Leakage Current V SHDN =.3V.1 7 µa t ON Turn-On Time V SHDN =.3V to 4.V, R L = 1Ω, V S = V 13 ns t OFF Turn-Off Time V SHDN = 4.V to.3v, R L = 1Ω, V S = V 18 ns SR Slew Rate V S = V, A V = 1,, V O = 4V V/µs A V = 1,, V O = 4V LT62-16 V/µs LT V/µs FPBW Full Power Bandwidth (Note 9) V S = V, V OUT = 3V P-P (LT62) MHz,, V CM = V OUT = V, V SHDN = OPEN, unless otherwise noted. Excludes the LT621 in the DD package (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = Half Supply mv V CM = V mv V CM = V 2. 6 mv Input Offset Voltage Match V CM = V mv (Channel-to-Channel) (Note 11) V CM = V to V mv I B Input Bias Current V CM = Half Supply 4 1 µa V CM = V µa V CM = V 23 µa I B I B Shift V CM = V to V µa I B Match (Channel-to-Channel) (Note 11) V CM = V to V µa I OS Input Offset Current V CM = Half Supply µa V CM = V µa V CM = V 3 12 µa Input Noise Voltage.1Hz to 1Hz 6 nv P-P e n Input Noise Voltage Density f = 1kHz.9 nv/ Hz f = 1kHz nv/ Hz i n Input Noise Current Density, Balanced Source f = 1kHz 2.2 pa/ Hz Unbalanced Source f = 1kHz 3. pa/ Hz Input Resistance Common Mode.7 MΩ Differential Mode 2.1 kω C IN Input Capacitance Common Mode 3.1 pf Differential Mode 4.2 pf A VOL Large-Signal Gain V O = ±4.V, 11 2 V/mV V O = ±2V, R L = V/mV 6 621fa

7 LT62/LT62- LT62-1/LT621 ELECTRICAL CHARACTERISTICS,, V CM = V OUT = V, V SHDN = OPEN, unless otherwise noted. Excludes the LT621 in the DD package (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMRR Common Mode Rejection Ratio V CM = V to V db V CM = 2V to 2V 7 1 db CMRR Match (Channel-to-Channel) (Note 11) V CM = 2V to 2V 8 1 db PSRR Power Supply Rejection Ratio V S = ±1.2V to ±V 6 68 db PSRR Match (Channel-to-Channel) (Note 6) V S = ±1.2V to ±V 6 1 db V OL Output Voltage Swing LOW (Note 7) No Load 12 mv I SINK = ma 11 mv I SINK = 2mA 1 29 mv V OH Output Voltage Swing HIGH (Note 7) No Load 7 13 mv I SOURCE = ma mv I SOURCE = 2mA mv I SC Short-Circuit Current ±6 ±9 ma I S Supply Current per Amplifier 2 23 ma Disabled Supply Current per Amplifier V SHDN =.3V ma I SHDN SHDN Pin Current V SHDN =.3V 2 28 µa V L V SHDN Pin Input Voltage LOW.3 V V H V SHDN Pin Input Voltage HIGH V +. V Shutdown Output Leakage Current V SHDN =.3V.1 7 µa t ON Turn-On Time V SHDN =.3V to 4.V, R L = 1Ω, V S = V 13 ns t OFF Turn-Off Time V SHDN = 4.V to.3v, R L = 1Ω, V S = V 18 ns GBW Gain Bandwidth Product Frequency = 1MHz MHz LT MHz LT MHz SR Slew Rate A V = 1,, V O = 4V 3 V/µs A V = 1,, V O = 4V LT V/µs LT V/µs FPBW Full Power Bandwidth (Note 9) V OUT = 3V P-P (LT62-1) MHz t S Settling Time (LT62, LT621).1%, V STEP = 2V, A V = 1, 14 ns 621fa 7

8 LT62/LT62- LT62-1/LT621 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over C < T A < 7 C temperature range. Excludes the LT621 in the DD package (Note 3)., V CM = V OUT = V, V SHDN = OPEN, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = Half Supply mv V CM = V mv V CM = V mv Input Offset Voltage Match V CM = V mv (Channel-to-Channel) (Note 11) V CM = V to V mv V OS TC Input Offset Voltage Drift (Note 8) V CM = Half Supply µv/ C I B Input Bias Current V CM = Half Supply 4 1 µa V CM = V µa V CM = V 23 µa I B I B Shift V CM = V to V µa I B Match (Channel-to-Channel) (Note 11) V CM = V to V µa I OS Input Offset Current V CM = Half Supply µa V CM = V µa V CM = V 3. 1 µa A VOL Large-Signal Gain V O = ±4.V, 46 8 V/mV V O = ±2V, R L = V/mV CMRR Common Mode Rejection Ratio V CM = V to V db V CM = 2V to 2V 7 1 db CMRR Match (Channel-to-Channel) (Note 11) V CM = 2V to 2V 7 1 db PSRR Power Supply Rejection Ratio V S = ±1.V to ±V 6 6 db PSRR Match (Channel-to-Channel) (Note 6) V S = ±1.V to ±V 6 1 db V OL Output Voltage Swing LOW (Note 7) No Load 16 7 mv I SINK = ma 6 12 mv I SINK = 2mA mv V OH Output Voltage Swing HIGH (Note 7) No Load 8 1 mv I SOURCE = ma mv I SOURCE = 2mA mv I SC Short-Circuit Current ±6 ±9 ma I S Supply Current per Amplifier 2 29 ma Disabled Supply Current per Amplifier V SHDN =.3V ma I SHDN SHDN Pin Current V SHDN =.3V µa V L V SHDN Pin Input Voltage LOW.3 V V H V SHDN Pin Input Voltage HIGH V +. V Shutdown Output Leakage Current V SHDN =.3V.1 7 µa t ON Turn-On Time V SHDN =.3V to 4.V, R L = 1Ω, V S = V 13 ns t OFF Turn-Off Time V SHDN = 4.V to.3v, R L = 1Ω, V S = V 18 ns SR Slew Rate A V = 1,, V O = 4V V/µs A V = 1,, V O = 4V LT V/µs LT V/µs FPBW Full Power Bandwidth (Note 9) V OUT = 3V P-P (LT62-1) 3 43 MHz 8 621fa

9 LT62/LT62- LT62-1/LT621 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over 4 C < T A < 8 C temperature range. Excludes the LT621 in the DD package (Note 3)., V CM = V OUT = V, V SHDN = OPEN, unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = Half Supply mv V CM = V mv V CM = V mv Input Offset Voltage Match V CM = V.2 2. mv (Channel-to-Channel) (Note 11) V CM = V to V mv V OS TC Input Offset Voltage Drift (Note 8) V CM = Half Supply µv/ C I B Input Bias Current V CM = Half Supply 4 1 µa V CM = V µa V CM = V 23 µa I B I B Shift V CM = V to V µa I B Match (Channel-to-Channel) (Note 11) 4 12 µa I OS Input Offset Current V CM = Half Supply µa V CM = V µa V CM = V 3. 1 µa A VOL Large-Signal Gain V O = ±4.V, 46 8 V/mV V O = ±2V R L = V/mV CMRR Common Mode Rejection Ratio V CM = V to V db V CM = 2V to 2V 7 1 db CMRR Match (Channel-to-Channel) (Note 11) V CM = 2V to 2V 7 1 db PSRR Power Supply Rejection Ratio V S = ±1.V to ±V 6 6 db PSRR Match (Channel-to-Channel) (Note 6) V S = ±1.V to ±V 6 1 db V OL Output Voltage Swing LOW (Note 7) No Load 16 7 mv I SINK = ma 6 12 mv I SINK = 2mA mv V OH Output Voltage Swing HIGH (Note 7) No Load 8 1 mv I SOURCE = ma mv I SOURCE = 2mA mv I SC Short-Circuit Current ±6 ±9 ma I S Supply Current 2 29 ma Disabled Supply Current V SHDN =.3V ma I SHDN SHDN Pin Current V SHDN =.3V µa V L V SHDN Pin Input Voltage LOW.3 V V H V SHDN Pin Input Voltage HIGH V +. V Shutdown Output Leakage Current V SHDN =.3V.1 7 µa t ON Turn-On Time V SHDN =.3V to 4.V, R L = 1Ω, V S = V 13 ns t OFF Turn-Off Time V SHDN = 4.V to.3v, R L = 1Ω, V S = V 18 ns SR Slew Rate A V = 1,, V O = 4V V/µs A V = 1,, V O = 4V LT V/µs LT V/µs FPBW Full Power Bandwidth (Note 9) V OUT = 3V P-P (LT62-1) MHz Note 1: Absolute maximum ratings are those values beyond which the life of the device may be impaired. Note 2: Inputs are protected by back-to-back diodes. If the differential input voltage exceeds.7v, the input current must be limited to less than 4mA. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. The LT621 in the DD package is limited by power dissipation to V S V, V over the commercial temperature range only. Note 4: The LT62C/LT62I and LT621C/LT621I are guaranteed functional over the temperature range of 4 C and 8 C (LT621DD excluded). 621fa 9

10 LT62/LT62- LT62-1/LT621 ELECTRICAL CHARACTERISTICS Note : The LT62C/LT621C are guaranteed to meet specified performance from C to 7 C. The LT62C/LT621C are designed, characterized and expected to meet specified performance from 4 C to 8 C, but are not tested or QA sampled at these temperatures. The LT62I is guaranteed to meet specified performance from 4 C to 8 C. Note 6: Minimum supply voltage is guaranteed by power supply rejection ratio test. Note 7: Output voltage swings are measured between the output and power supply rails. Note 8: This parameter is not 1% tested. Note 9: Full-power bandwidth is calculated from the slew rate: FPBW = SR/2πV P Note 1: Thermal resistance varies depending upon the amount of PC board metal attached to the V pin of the device. θ JA is specified for a certain amount of 2oz copper metal trace connecting to the V pin as described in the thermal resistance tables in the Application Information section. Note 11: Matching parameters on the LT621 are the difference between the two amplifiers. CMRR and PSRR match are defined as follows: CMRR and PSRR are measured in µv/v on the identical amplifiers. The difference is calculated in µv/v. The result is converted to db. Note 12: There are reverse biased ESD diodes on all inputs and outputs as shown in Figure 1. If these pins are forced beyond either supply, unlimited current will flow through these diodes. If the current is transient in nature and limited to less than 3mA, no damage to the device will occur. TYPICAL PERFOR A CE CHARACTERISTICS UW 8 7 V OS Distribution, V CM = V + /2 V S = V, V SO V OS Distribution, V CM = V + V OS Distribution, V CM = V V S = V, V SO V S = V, V SO NUMBER OF UNITS NUMBER OF UNITS NUMBER OF UNITS INPUT OFFSET VOLTAGE (µv) INPUT OFFSET VOLTAGE (µv) INPUT OFFSET VOLTAGE (µv) 62 G1 62 G2 62 G3 SUPPLY CURRENT (ma) Supply Current vs Supply Voltage 3 T A = 12 C T A = C 1 OFFSET VOLTAGE (mv) Offset Voltage vs Input Common Mode Voltage T A = 12 C T A = C V S = V, V TYPICAL PART INPUT BIAS CURRENT (µa) Input Bias Current vs Common Mode Voltage V S = V, V T A = 12 C T A = C TOTAL SUPPLY VOLTAGE (V) INPUT COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V) 62 G4 62 G 62 G fa

11 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW INPUT BIAS CURRENT (µa) CHANGE IN OFFSET VOTLAGE (mv) Input Bias Current vs Temperature V S = V, V V CM = V V CM = V TEMPERATURE ( C) Minimum Supply Voltage V CM = V S /2 T A = C 62 G7 T A = 12 C TOTAL SUPPLY VOLTAGE (V) 62 G1 OUTPUT SATURATION VOLTAGE (V) OUTPUT SHORT-CIRCUIT CURRENT (ma) Output Saturation Voltage vs Load Current (Output Low) V S = V, V T A = 12 C T A = C LOAD CURRENT (ma) Output Short-Circuit Current vs Power Supply Voltage SOURCING SINKING T A = 12 C T A = C T A = 12 C T A = C 62 G POWER SUPPLY VOLTAGE (±V) 62 G11 OUTPUT SATURATION VOLTAGE (V) INPUT VOLTAGE (mv) Output Saturation Voltage vs Load Current (Output High) V S = V, V T A = 12 C Open-Loop Gain T A = C LOAD CURRENT (ma) R L = 1Ω OUTPUT VOLTAGE (V) G9 V S = 3V, V 62 G12 3 INPUT VOLTAGE (mv) Open-Loop Gain Open-Loop Gain Offset Voltage vs Output Current R L = 1Ω OUTPUT VOLTAGE (V) V S = V, V 62 G13 INPUT VOLTAGE (mv) OUTPUT VOLTAGE (V) R L = 1Ω 62 G14 OFFSET VOLTAGE (mv) T A = 12 C T A = C OUTPUT CURRENT (ma) 62 G fa 11

12 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS CHANGE IN OFFSET VOLTAGE (µv) UW Warm-Up Drift vs Time (LT62S8) Total Noise vs Source Resistance Input Noise Voltage vs Frequency V S = ±1.V V S = ±2.V TIME AFTER POWER-UP (SEC) 62 G16 TOTAL NOISE VOLTAGE (nv/ Hz) V CM = V f = 1kHz UNBALANCED SOURCE RESISTORS LT62 TOTAL NOISE RESISTOR NOISE LT62 AMPLIFIER NOISE VOLTAGE k 1k 1k SOURCE RESISTANCE (Ω) 62 G17 NOISE VOLTAGE (nv/ Hz) PNP ACTIVE V CM =.V NPN ACTIVE V CM = 4.V BOTH ACTIVE V CM = 2.V 1 1k 1k V S = V, V 62 G18 1k BALANCED NOISE CURRENT (pa/ Hz) Balanced Noise Current vs Frequency PNP ACTIVE V CM =.V BOTH ACTIVE V CM = 2.V NPN ACTIVE V CM = 4.V V S = V, V BALANCED SOURCE RESISTANCE UNBALANCED NOISE CURRENT (pa/ Hz) Unbalanced Noise Current vs Frequency PNP ACTIVE V CM =.V BOTH ACTIVE V CM = 2.V NPN ACTIVE V CM = 4.V V S = V, V UNBALANCED SOURCE RESISTANCE OUTPUT VOLTAGE NOISE (nv) Hz to 1Hz Output Noise Voltage V S = V, V V CM = V S / k 1k 1k 1 1 1k 1k 1k 8 TIME (SEC/DIV) 62 G19 62 G2 62 G21 SUPPLY CURRENT (ma) Supply Current vs SHDN Pin Voltage V S = V, V T A = C T A = 12 C SHDN PIN CURRENT (µa) SHDN Pin Current vs SHDN Pin Voltage V S = V, V T A = 12 C T A = C SHDN PIN VOLTAGE (V) SHDN PIN VOLTAGE (V) 62 G43 62 G fa

13 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW LT62, LT621 GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Temperature V S = 3V, V PHASE MARGIN V S = 3V, V GAIN BANDWIDTH TEMPERATURE ( C) 62 G PHASE MARGIN (DEG) GAIN (db) Open-Loop Gain vs Frequency PHASE GAIN V CM = 4.V V CM = 4.V V CM =.V V CM =.V V S = V, V 4 1 C L = pf k 1M 1M 1M 1G 62 G PHASE (DEG) GAIN (db) Open-Loop Gain vs Frequency PHASE GAIN V S = ±1.V V S = ±1.V V CM = V 4 1 C L = pf k 1M 1M 1M 1G 62 G PHASE (DEG) GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Supply Voltage C L = pf PHASE MARGIN GAIN BANDWIDTH TOTAL SUPPLY VOLTAGE (V) 62 G PHASE MARGIN (DEG) SLEW RATE (V/µs) Slew Rate vs Temperature A V = 1 R F = R G = 1k FALLING RISING V S = ±2.V RISING V S = ±2.V FALLING TEMPERATURE ( C) 62 G26 12 OUTPUT IMPEDANCE (Ω) Output Impedance vs Frequency 1 V S = V, V 1 1 A V = 1 1 A V = 2 A V = FREQUENCY (MHz) 62 G27 COMMON MODE REJECTION RATIO (db) Common Mode Rejection Ratio vs Frequency V S = V, V V CM = V S /2 1k 1k 1M 1M 1M 1G 62 G28 621fa 13

14 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW LT62, LT621 POWER SUPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency NEGATIVE SUPPLY V S = V, V V CM = V S /2 POSITIVE SUPPLY OVERSHOOT (%) Overshoot vs Capacitive Load V S = V, V A V = 1 R S = Ω R L = Ω R S = 2Ω R S = 1Ω OVERSHOOT (%) Overshoot vs Capacitive Load V S = V, V A V = 2 R S = 2Ω R S = Ω R L = Ω R S = 1Ω 1k 1k 1k 1M 1M 1M CAPACITIVE LOAD (pf) CAPACITIVE LOAD (pf) 62 G29 62 G3 62 G31 SETTLING TIME (ns) Settling Time vs Output Step (Noninverting) A V = 1 1mV 1mV V IN V OUT Ω OUTPUT STEP (V) + 1mV 1mV SETTLING TIME (ns) Settling Time vs Output Step (Inverting) 4 A V = 1 1mV 1mV Ω V IN Ω V OUT 1mV OUTPUT STEP (V) + 1mV OUTPUT VOLTAGE SWING (V P-P ) Maximum Undistorted Output Signal vs Frequency A V = 1 A V = 2 3 HD2, HD3 < 4dBc 2 1k 1k 1M 1M 62 G32 62 G33 62 G34 6 Distortion vs Frequency, A V = 1 A V = 1 V O = 2V P-P V S = ±2.V 6 Distortion vs Frequency, A V = 1 A V = 1 V O = 2V P-P 4 Distortion vs Frequency, A V = 2 A V = 2 V O = 2V P-P V S = ±2.V DISTORTION (dbc) k HD2, HD2, R L = 1Ω HD3, R L = 1Ω 1M HD3, 62 G3 1M DISTORTION (dbc) k HD2, HD2, R L = 1Ω HD3, R L = 1Ω 1M HD3, 62 G36 1M DISTORTION (dbc) k HD2, R L = 1Ω HD3, R L = 1Ω HD2, HD3, 1M 1M 62 G fa

15 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW LT62, LT621 DISTORTION (dbc) k Distortion vs Frequency, A V = 2 A V = 2 V O = 2V P-P HD2, R L = 1Ω HD2, HD3, R L = 1Ω 1M HD3, V Large-Signal Response 62 G38 1M VOLTAGE GAIN (db) Channel Separation vs Frequency A V = FREQUENCY (MHz) ±V Large-Signal Response 62 G77 V 1V/DIV 2V/DIV V V V S = V, V 2ns/DIV 62 G39 A V = 1 2ns/DIV 62 G41 A V = 1 Output Overdrive Recovery V Small-Signal Response V IN 1V/DIV V mv/div V OUT 2V/DIV V V S = V, V 2ns/DIV 62 G42 A V = 2 V S = V, V 2ns/DIV 62 G4 A V = 1 621fa 1

16 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW LT62- GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Temperature PHASE MARGIN GAIN BANDWIDTH V S = 3V, V V S = 3V, V TEMPERATURE ( C) 62 G PHASE MARGIN (DEG) SLEW RATE (V/µs) Slew Rate vs Temperature A V = R F = R G = 2Ω FALLING RISING V S = ±2.V FALLING V S = ±2.V RISING TEMPERATURE ( C) 62 G46 12 OVERSHOOT (%) Overshoot vs Capacitive Load V S = V, V A V = R S = Ω R S = Ω R S = 2Ω R S = 1Ω 1 1 CAPACITIVE LOAD (pf) 62 G47 POWER SUPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency POSITIVE SUPPLY NEGATIVE SUPPLY V S = V, V V CM = V S /2 1k 1k 1k 1M 1M 1M 62 G48 OUTPUT IMPEDANCE (Ω) Output Impedance vs Frequency V S = V, V A V = A V =.1 1k 1M 1M 62 G49 1M GAIN (db) Open-Loop Gain vs Frequency GAIN PHASE V S = ±1.V 1 V CM = V V S = ±1.V C L = pf 1 1k 1M 1M 1M 1G 62 G PHASE (DEG) GAIN (db) Open-Loop Gain vs Frequency PHASE 1 8 V CM =.V V CM = 4.V GAIN V CM =.V 2 4 V CM = 4.V 1 V S = V, V 6 C L = pf k 1M 1M 1M 1G 62 G1 PHASE (DEG) GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Supply Voltage C L = pf PHASE MARGIN GAIN BANDWIDTH TOTAL SUPPLY VOLTAGE (V) G PHASE MARGIN (DEG) GAIN BANDWIDTH (MHz) Gain Bandwidth vs Resistor Load 2 R F = 1k 1 R G = 1k RESISTOR LOAD (Ω) G2 G fa

17 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW LT62- COMMON MODE REJECTION RATIO (db) Common Mode Rejection Ratio vs Frequency V S = V, V V CM = V S /2 1k 1k 1M 1M 1M 1G OUTPUT VOLTAGE SWING (VP-P) Maximum Undistorted Output Signal vs Frequency 2 1 A V = 1k 1k 1M 1M 1M DISTORTION (db) k 2nd and 3rd Harmonic Distortion vs Frequency A V = V O = 2V P-P V S = ±2.V R L = 1Ω, 3RD R L = 1Ω, 2ND, 2ND, 3RD 1k 1M 1M 62 G4 62 G 62 G6 DISTORTION (db) nd and 3rd Harmonic Distortion vs Frequency ±V Large-Signal Response Output-Overdrive Recovery A V = V O = 2V P-P R L = 1Ω, 3RD, 2ND R L = 1Ω, 2ND V 2V/DIV V V V IN 1V/DIV V OUT 2V/DIV V V k, 3RD 1k 1M 1M ns/div 62 G8 A V = C L = 1.8pF SCOPE PROBE V S = V, V ns/div 62 G9 A V = C L = 1.8pF SCOPE PROBE 62 G7 V Small-Signal Response 1nV Input Referred High Frequency Noise Spectrum mv/div V 1nV/ Hz/DIV V S = V, V ns/div 62 G61 A V = C L = 1.8pF SCOPE PROBE nv 1kHz 1MHz/DIV 1MHz NOISE LIMITED BY INSTRUMENT NOISE FLOOR 62 G6 621fa 17

18 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW LT62-1 GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Temperature Slew Rate vs Temperature Overshoot vs Capacitive Load PHASE MARGIN GAIN BANDWIDTH V S = 3V, V V S = 3V, V TEMPERATURE ( C) 62 G PHASE MARGIN (DEG) SLEW RATE (v/µs) A V = 1 R F = R G = 1Ω FALLING RISING V S = ±2.V RISING V S = ±2.V FALLING TEMPERATURE ( C) 62 G63 OVERSHOOT (%) V S = V, V A V = 1 R S = Ω R S = 2Ω R S = Ω R S = 1Ω 1 1 CAPACITIVE LOAD (pf) 62 G64 POWER SUPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency Output Impedance vs Frequency Open-Loop Gain vs Frequency POSITIVE SUPPLY NEGATIVE SUPPLY V S = V, V V CM = V S /2 1k 1k 1k 1M 1M 1M 62 G6 OUTPUT IMPEDANCE (Ω) V S = V, V A V = 1.1 1k 1M 1M A V = 1 62 G66 1M GAIN (db) GAIN PHASE V S = ±1.V V S = ±1.V 1 V CM = V C L = pf 1 1k 1M 1M 1M 1G 62 G PHASE (DEG) GAIN (db) Open-Loop Gain vs Frequency PHASE GAIN V CM = 4.V V CM =.V V CM = 4.V V CM =.V 1 V S = V, V 6 C L = pf k 1M 1M 1M 1G 62 G PHASE (DEG) GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Supply Voltage C L = pf PHASE MARGIN GAIN BANDWIDTH TOTAL SUPPLY VOLTAGE (V) G PHASE MARGIN (DEG) GAIN BANDWIDTH (MHz) Gain Bandwidth vs Resistor Load 4 R F = 1k 2 R G = 1k RESISTOR LOAD (Ω) G2 G fa

19 LT62/LT62- LT62-1/LT621 TYPICAL PERFOR A CE CHARACTERISTICS UW LT62-1 COMMON MODE REJECTION RATIO (db) Common Mode Rejection Ratio vs Frequency V S = V, V V CM = V S /2 1k 1k 1M 1M 1M 1G OUTPUT VOLTAGE SWING (VP-P) Maximum Undistorted Output Signal vs Frequency 2 1 A V = 1 1k 1k 1M 1M 1M DISTORTION (db) k 2nd and 3rd Harmonic Distortion vs Frequency A V = 1 V O = 2V P-P V S = ±2.V, 3RD R L = 1Ω, 2ND R L = 1Ω, 3RD, 2ND 1k 1M 1M 62 G71 62 G72 62 G73 DISTORTION (db) nd and 3rd Harmonic Distortion vs Frequency ±V Large-Signal Response Output-Overdrive Recovery A V = 1 V O = 2V P-P R L = 1Ω, 3RD, 3RD R L = 1Ω, 2ND V 2V/DIV V V V IN 1V/DIV V OUT 2V/DIV V V k, 2ND 1k 1M 1M ns/div 62 G7 A V = 1 C L = 1.8pF SCOPE PROBE V S = V, V ns/div 62 G76 A V = 1 C L = 1.8pF SCOPE PROBE 62 G74 V Small-Signal Response 1nV Input Referred High Frequency Noise Spectrum mv/div V 1nV/ Hz/DIV V S = V, V ns/div 62 G78 A V = 1 C L = 1.8pF SCOPE PROBE nv 1kHz 1MHz/DIV 1MHz 62 G77 621fa 19

20 LT62/LT62- LT62-1/LT621 APPLICATIO S I FOR ATIO U W U U Amplifier Characteristics Figure 1 shows a simplified schematic of the LT62 family, which has two input differential amplifiers in parallel that are biased on simultaneously when the common mode voltage is at least 1.V from either rail. This topology allows the input stage to swing from the positive supply voltage to the negative supply voltage. As the common mode voltage swings beyond V CC 1.V, current source I 1 saturates and current in Q1/Q4 is zero. Feedback is maintained through the Q2/Q3 differential amplifier, but with an input g m reduction of 1/2. A similar effect occurs with I 2 when the common mode voltage swings within 1.V of the negative rail. The effect of the g m reduction is a shift in the V OS as I 1 or I 2 saturate. Input bias current normally flows out of the + and inputs. The magnitude of this current increases when the input common mode voltage is within 1.V of the negative rail, and only Q1/Q4 are active. The polarity of this current reverses when the input common mode voltage is within 1.V of the positive rail and only Q2/Q3 are active. The second stage is a folded cascode and current mirror that converts the input stage differential signals to a single ended output. Capacitor C1 reduces the unity cross frequency and improves the frequency stability without degrading the gain bandwidth of the amplifier. The differential drive generator supplies current to the output transistors that swing from rail-to-rail. The LT62-/LT62-1 are decompensated op amps for higher gain applications. These amplifiers maintain identical DC specifications with the LT62, but have a reduced Miller compensation capacitor C M. This results in a significantly higher slew rate and gain bandwidth product. Input Protection There are back-to-back diodes, D1 and D2, across the + and inputs of these amplifiers to limit the differential input voltage to ±.7V. The inputs of the LT62 family do not have internal resistors in series with the input transistors. This technique is often used to protect the input devices from overvoltage that causes excessive currents to flow. The addition of these resistors would significantly degrade the low noise voltage of these amplifiers. For instance, a 1Ω resistor in series with each input would generate 1.8nV/ Hz of noise, and the total amplifier noise voltage would rise from.9nv/ Hz to 2.3nV/ Hz. Once the input differential voltage exceeds ±.7V, steady-state current conducted though the protection diodes should be limited to ±4mA. This implies 2Ω of protection resistance per volt of continuous overdrive beyond ±.7V. The input diodes are rugged enough to handle transient currents due to amplifier slew rate overdrive or momentary clipping without these resistors. Figure 2 shows the input and output waveforms of the LT62 driven into clipping while connected in a gain of V DESD1 + DESD3 V V+ R1 R2 DESD7 I 1 BIAS V SHDN Q11 DESD8 +V Q6 Q C M V DESD2 Q1 Q4 +V Q2 Q3 C1 +V D1 D2 DIFFERENTIAL DESD Q9 DRIVE DESD4 GENERATOR Q8 Q7 DESD6 +V Q1 V R3 R4 R 2 I 2 D3 Figure 1. Simplified Schematic V 623/4 F1 621fa

21 LT62/LT62- LT62-1/LT621 APPLICATIO S I FOR A V = 1. In this photo, the input signal generator is clipping at ±3mA, and the output transistors supply this generator current through the protection diodes. V ATIO U W U U Figure 2. V S = ±2.V, A V = 1 with Large Overdrive V CC 2.V V EE 2.V ESD The LT62 has reverse-biased ESD protection diodes on all inputs and outputs as shown in Figure 1. If these pins are forced beyond either supply, unlimited current will flow through these diodes. If the current is transient and limited to 3mA or less, no damage to the device will occur. Noise The noise voltage of the LT62 is equivalent to that of a 6Ω resistor, and for the lowest possible noise it is desirable to keep the source and feedback resistance at or below this value, i.e., R S + R G //R FB 6Ω. With R S + R G //R FB = 6Ω the total noise of the amplifier is: e n = (.9nV) 2 + (.9nV) 2 = 1.3nV. Below this resistance value, the amplifier dominates the noise, but in the resistance region between 6Ω and approximately 6kΩ, the noise is dominated by the resistor thermal noise. As the total resistance is further increased, beyond 6k, the noise current multiplied by the total resistance eventually dominates the noise. For a complete discussion of amplifier noise, see the LT128 data sheet. Power Dissipation The LT62 combines high speed with large output current in a small package, so there is a need to ensure that the die s junction temperature does not exceed 1 C. The LT62 is housed in a 6-lead TSOT-23 package. The package has the V supply pin fused to the lead frame to enhance the thermal conductance when connecting to a ground plane or a large metal trace. Metal trace and plated through-holes can be used to spread the heat generated by the device to the backside of the PC board. For example, on a 3/32" FR-4 board with 2oz copper, a total of 27 square millimeters connects to Pin 2 of the LT62 in an TSOT-23 package will bring the thermal resistance, θ JA, to about 13 C/W. Without extra metal trace beside the power line connecting to the V pin to provide a heat sink, the thermal resistance will be around 2 C/W. More information on thermal resistance with various metal areas connecting to the V pin is provided in Table 1. Table 1. LT62 6-Lead TSOT-23 Package COPPER AREA BOARD AREA THERMAL RESISTANCE TOPSIDE (mm 2 ) (mm 2 ) (JUNCTION-TO-AMBIENT) C/W C/W C/W 2 2 C/W Device is mounted on topside. Junction temperature T J is calculated from the ambient temperature T A and power dissipation P D as follows: T J = T A + (P D θ JA ) The power dissipation in the IC is the function of the supply voltage, output voltage and the load resistance. For a given supply voltage, the worst-case power dissipation P D(MAX) occurs at the maximum quiescent supply current and at the output voltage which is half of either supply voltage (or the maximum swing if it is less than 1/2 the supply voltage). P D(MAX) is given by: P D(MAX) = (V S I S(MAX) ) + (V S /2) 2 /R L Example: An LT62 in TSOT-23 mounted on a 2mm 2 area of PC board without any extra heat spreading plane connected to its V pin has a thermal resistance of 621fa 21

22 LT62/LT62- LT62-1/LT621 APPLICATIO S I FOR ATIO U W U U 2 C/W, θ JA. Operating on ±V supplies driving Ω loads, the worst-case power dissipation is given by: P D(MAX) = (1 23mA) + (2.) 2 / = =.3W The maximum ambient temperature that the part is allowed to operate is: T A = T J (P D(MAX) 2 C/W) = 1 C (.3W 2 C/W) = 79 C To operate the device at higher ambient temperature, connect more metal area to the V pin to reduce the thermal resistance of the package as indicated in Table 1. DD Package Heat Sinking The underside of the DD package has exposed metal (4mm 2 ) from the lead frame where the die is attached. This provides for the direct transfer of heat from the die junction to printed circuit board metal to help control the maximum operating junction temperature. The dual-inline pin arrangement allows for extended metal beyond the ends of the package on the topside (component side) of a PCB. Table 2 summarizes the thermal resistance from the die junction-to-ambient that can be obtained using various amounts of topside metal (2oz copper) area. On mulitlayer boards, further reductions can be obtained using additional metal on inner PCB layers connected through vias beneath the package. Table 2. LT62 8-Lead DD Package COPPER AREA THERMAL RESISTANCE TOPSIDE (mm 2 ) (JUNCTION-TO-AMBIENT) 4 16 C/W C/W C/W 64 9 C/W 13 7 C/W The LT62 amplifier family has thermal shutdown to protect the part from excessive junction temperature. The amplifier will shut down to approximately 1.2mA supply current per amplifier if the maximum temperature is exceeded. The LT62 will remain off until the junction temperature reduces to about 13 C, at which point the amplifier will return to normal operation. PACKAGE DESCRIPTIO U DD Package 8-Lead Plastic DFN (3mm 3mm) (Reference LTC DWG # ).67 ±. R =.11 TYP 8.38 ±.1 3. ±. 2.1 ± ±. (2 SIDES).28 ±.. BSC 2.38 ±. (2 SIDES) PACKAGE OUTLINE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK.2 REF 3. ±.1 (4 SIDES).7 ± ±.1 (2 SIDES) 4.28 ± ±.1 (2 SIDES) BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-229 VARIATION OF (WEED-1) 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.1mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED 621fa 1. BSC (DD8) DFN 23

23 LT62/LT62- LT62-1/LT621 PACKAGE DESCRIPTIO U S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # ).62 MAX.9 REF 2.9 BSC (NOTE 4) 1.22 REF 3.8 MAX 2.62 REF 1.4 MIN 2.8 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR.9 BSC PLCS (NOTE 3).2 BSC DATUM A 1. MAX REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING BSC (NOTE 3) S6 TSOT DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR. MOLD FLASH SHALL NOT EXCEED.24mm 6. JEDEC PACKAGE REFERENCE IS MO-193 S8 Package 8-Lead Plastic Small Outline (Narrow.1 Inch) (Reference LTC DWG # ). BSC.4 ± (4.81.4) NOTE MIN.16 ± ( ).1.17 ( ) NOTE 3.3 ±. TYP RECOMMENDED SOLDER PAD LAYOUT (.23.24).1.2 (.24.8) 4 8 TYP.3.69 ( ).4.1 (.11.24) ( ) (.3.483) NOTE: INCHES TYP 1. DIMENSIONS IN (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.6" (.1mm). (1.27) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO fa 23

24 LT62/LT62- LT62-1/LT621 TYPICAL APPLICATIO U Rail-to-Rail High Speed Low Noise Instrumentation Amplifier + LT Ω 1Ω 1k 1pF 49.9Ω 49.9Ω 64Ω + LT Ω V OUT 1k LT62-1 1Ω A V = 1 A V = TA3 + Instrumentation Amplifier Frequency Response 42.3dB 3dB/DIV 1 1 FREQUENCY (MHz) A V = 13 BW 3dB = 8MHz SLEW RATE = V/µs CMRR = db at 1MHz 62 TA4 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT128 Single, Ultra Low Noise MHz Op Amp 1.1nV/ Hz LT1677 Single, Low Noise Rail-to-Rail Amplifier 3V Operation, 2.mA, 4.nV/ Hz, 6µV Max V S LT1722/LT1723/LT1724 Single/Dual/Quad Low Noise Precision Op Amp 7V/µs Slew Rate, 4µV Max V OS, 3.8nV/ Hz, 3.7mA LT186/LT187 Single/Dual, Low Noise 32MHz Rail-to-Rail Amplifier 2.V Operation, µv Max V OS, 3.nV/ Hz LT623 Dual, Low Noise, Low Current Rail-to-Rail Amplifier 1.9nV/ Hz, 3mA Max, 1MHz Gain Bandwidth 24 LT/TP 113 1K REV A PRINTED IN USA Linear Technology Corporation 163 McCarthy Blvd., Milpitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION fa