LT622/LT6221/LT6222 ABSOLTE AXI RATI GS W W W Total Supply Voltage ( to ) V Input Voltage (Note 2)... ± Input Current (Note 2)... ±1mA Output S

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1 FEATRES Gain Bandwidth Product: 6MHz Input Common Mode Range Includes Both Rails Output Swings Rail-to-Rail Low Quiescent Current: 1mA Max Input Offset Voltage: 3µV Max Input Bias Current: na Max Wide Supply Range: 2.2V to 12.6V Large Output Current: ma Typ Low Voltage Noise: 1nV Hz Typ Slew Rate: 2V/µs Typ Common Mode Rejection: 12dB Typ Power Supply Rejection: db Typ Open-Loop Gain: 1V/mV Typ Operating Temperature Range: 4 C to 8 C Single in the 8-Pin SO and -Pin Low Profile (1mm) ThinSOT TM Packages Dual in the 8-Pin SO and (3mm x 3mm) DFN Packages Quad in the 16-Pin SSOP Package APPLICATIO S Low Voltage, High Frequency Signal Processing Driving A/D Converters Rail-to-Rail Buffer Amplifiers Active Filters Video Amplifiers Fast Current Sensing Amplifiers LT622/LT6221/LT6222 Single/Dual/Quad 6MHz, 2V/µs, Low Power, Rail-to-Rail Input and Output Precision Op Amps DESCRIPTIO The LT 622/LT6221/LT6222 are single/dual/quad, low power, high speed rail-to-rail input and output operational amplifiers with excellent DC performance. The LT622/ LT6221/LT6222 feature reduced supply current, lower input offset voltage, lower input bias current and higher DC gain than other devices with comparable bandwidth. Typically, the LT622/LT6221/LT6222 have an input offset voltage of less than 1µV, an input bias current of less than na and an open-loop gain of 1V/mV. The parts have an input range that includes both supply rails and an output that swings within 1mV of either supply rail to maximize the signal dynamic range in low supply applications. The LT622/LT6221/LT6222 maintain performance for supplies from 2.2V to 12.6V and are specified at 3V, V and ±V supplies. The inputs can be driven beyond the supplies without damage or phase reversal of the output. The LT622 is housed in the 8-pin SO package with the standard op amp pinout as well as the -pin SOT-23 package. The LT6221 is available in 8-pin SO and DFN (3mm 3mm low profile dual fine pitch leadless) packages with the standard op amp pinout. The LT6222 features the standard quad op amp configuration and is available in the 16-Pin SSOP package. The LT622/ LT6221/ LT6222 can be used as plug-in replacements for many op amps to improve input/output range and performance., LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO I PD PHOTODIODE ~4pF Stepped-Gain Photodiode Amplifier 3.24k 1k LT622 3pF 1pF = ±1.V TO ±V 33k 1k LT V OT TA1 PERCENT OF NITS (%) V OS Distribution, V CM = V (S8, PNP Stage) = V, V V CM = V 2 INPT OFFSET VOLTAGE (µv) G fa 1

2 LT622/LT6221/LT6222 ABSOLTE AXI RATI GS W W W Total Supply Voltage ( to ) V Input Voltage (Note 2)... ± Input Current (Note 2)... ±1mA Output Short Circuit Duration (Note 3)... Indefinite Operating Temperature Range (Note 4)...4 C to 8 C Specified Temperature Range (Note )...4 C to 8 C (Note 1) Maximum Junction Temperature... C (DD Package) C Storage Temperature...6 C to C (DD Package)...6 C to 12 C Lead Temperature (Soldering, 1 sec.)... 3 C PACKAGE/ORDER I FOR ATIO W V OT 1 V S 2 IN 3 TOP VIEW 4 IN S PACKAGE -LEAD PLASTIC TSOT-23 ORDER PART NMBER LT622CS LT622IS S PART* MARKING LTAFP NC IN IN T JMAX = C, θ JA = 2 C/W (NOTE 1) T JMAX = C, θ JA = 19 C/W TOP VIEW TOP VIEW OT A 1 16 OT D TOP VIEW OT A 1 8 IN A 2 IN D A OT A 1 8 V D IN A 2 7 OT B S IN A 3 14 IN D A IN A 3 6 IN B IN A 2 7 OT B 4 13 A B 4 IN B IN A 3 6 IN B IN B 12 IN C B B C V S 4 IN B IN B 6 11 IN C DD PACKAGE OT B 7 1 OT C 8-LEAD (3mm 3mm) PLASTIC DFN S8 PACKAGE 8-LEAD PLASTIC SO NC 8 9 NC T JMAX = 12 C, θ JA = 16 C/W (NOTE 1) T EXPOSED PAD INTERNALLY CONNECTED TO V JMAX = C, θ JA = 19 C/W S GN PACKAGE (PCB CONNECTION OPTIONAL) 16-LEAD NARROW PLASTIC SSOP TOP VIEW S8 PACKAGE 8-LEAD PLASTIC SO NC V OT NC T JMAX = C, θ JA = 13 C/W ORDER PART NMBER LT622CS8 LT622IS8 S8 PART MARKING I ORDER PART NMBER LT6221CDD LT6221IDD DD PART* MARKING ORDER PART NMBER LT6221CS8 LT6221IS8 S8 PART MARKING I ORDER PART NMBER LT6222CGN LT6222IGN SSOP PART MARKING LADZ I Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container fa

3 ELECTRICAL CHARACTERISTICS T A = 2 C, = V, V; = 3V, V; V CM = V OT = half supply, unless otherwise noted LT622/LT6221/LT6222 SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage V CM = V 7 3 µv V CM = V (DD Package) 7 µv V CM = V (S Package) 2 8 µv V CM =. 2. mv V CM = (S Package). 3 mv V OS Input Offset Voltage Shift = V, V CM = V to 3.V 3 19 µv = 3V, V CM = V to 1.V 12 µv Input Offset Voltage Match (Channel-to-Channel) V CM = V 1 6 µv (Note 9) V CM = V (DD Package) 11 µv I B Input Bias Current V CM = 1V na V CM = 2 6 na Input Bias Current Match (Channel-to-Channel) V CM = 1V 17 na (Note 9) V CM = 2 2 na I OS Input Offset Current V CM = 1V 1 na V CM = 1 na Input Noise Voltage.1Hz to 1Hz. µv P-P e n Input Noise Voltage Density f = 1kHz 1 nv/ Hz i n Input Noise Current Density f = 1kHz.8 pa/ Hz C IN Input Capacitance 2 pf A VOL Large Signal Voltage Gain = V, V O =.V to 4.V, at /2 3 1 V/mV = V, V O = 1V to 4V, R L = 1Ω at / V/mV = 3V, V O =.V to 2.V, at /2 3 9 V/mV CMRR Common Mode Rejection Ratio = V, V CM = V to 3.V 8 12 db = 3V, V CM = V to 1.V db CMRR Match (Channel-to-Channel) (Note 9) = V, V CM = V to 3.V 79 1 db = 3V, V CM = V to 1.V 76 1 db Input Common Mode Range V PSRR Power Supply Rejection Ratio = 2.V to 1V, V CM = V 84 db PSRR Match (Channel-to-Channel) (Note 9) 79 db Minimum Supply Voltage (Note 6) V V OL Output Voltage Swing LOW (Note 7) No Load 4 mv I SINK = ma 1 2 mv I SINK = 2mA 32 6 mv V OH Output Voltage Swing HIGH (Note 7) No Load 4 mv I SORCE = ma 13 2 mv I SORCE = 2mA 47 9 mv I SC Short-Circuit Current = V 2 4 ma = 3V 2 3 ma I S Supply Current Per Amplifier.9 1 ma GBW Gain-Bandwidth Product = V, Frequency = 1MHz 3 6 MHz SR Slew Rate = V, A V = 1,, V O = 4V 1 2 V/µs FPBW Full Power Bandwidth = V, A V = 1, V O = 4V p-p 1.6 MHz HD Harmonic Distortion = V, A V = 1,, V O = 2V P-P, f C = khz 77. dbc t S Settling Time.1%, = V, TEP = 2V, A V = 1, 3 ns G Differential Gain (NTSC) = V, A V = 2,.3 % θ Differential Phase (NTSC) = V, A V = 2,.3 Deg 62212fa 3

4 LT622/LT6221/LT6222 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the C T A 7 C temperature range. = V, V; = 3V, V; V CM = V OT = half supply, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage V CM = V 9 µv V CM = V (DD Package) 18 8 µv V CM = V (S Package) µv V CM =. 3 mv V CM = (S Package). 3. mv V OS Input Offset Voltage Shift = V, V CM = V to 3.V 3 28 µv = 3V, V CM = V to 1.V 19 µv Input Offset Voltage Match (Channel-to-Channel) V CM = V 11 8 µv (Note 9) V CM = V (DD Package) µv V OS TC Input Offset Voltage Drift (Note 8) 1. µv/ C (S Package) 3. 1 µv/ C I B Input Bias Current V CM = 1V 2 17 na V CM =.2V 27 8 na Input Bias Current Match (Channel-to-Channel) V CM = 1V 2 na (Note 9) V CM =.2V 2 3 na I OS Input Offset Current V CM = 1V 12 na V CM =.2V 12 na A VOL Large Signal Voltage Gain = V, V O =.V to 4.V, at /2 3 9 V/mV = V, V O = 1V to 4V, R L = 1Ω at /2 3 9 V/mV = 3V, V O =.V to 2.V, at /2 2 8 V/mV CMRR Common Mode Rejection Ratio = V, V CM = V to 3.V 82 1 db = 3V, V CM = V to 1.V 78 1 db CMRR Match (Channel-to-Channel) (Note 9) = V, V CM = V to 3.V 77 1 db = 3V, V CM = V to 1.V 73 1 db Input Common Mode Range V PSRR Power Supply Rejection Ratio = 2.V to 1V, V CM = V db PSRR Match (Channel-to-Channel) (Note 9) db Minimum Supply Voltage (Note 6) V V OL Output Voltage Swing LOW (Note 7) No Load 8 mv I SINK = ma mv I SINK = 2mA 37 7 mv V OH Output Voltage Swing HIGH (Note 7) No Load 8 mv I SORCE = ma 3 mv I SORCE = 2mA 6 11 mv I SC Short-Circuit Current = V 2 4 ma = 3V 2 3 ma I S Supply Current Per Amplifier ma GBW Gain-Bandwidth Product = V, Frequency = 1MHz 3 6 MHz SR Slew Rate = V, A V = 1,, V O = 4V P-P 9 18 V/µs fa

5 LT622/LT6221/LT6222 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the 4 C T A 8 C temperature range. = V, V; = 3V, V; V CM = V OT = half supply unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage V CM = V 12 7 µv V CM = V (DD Package) 3 13 µv V CM = V (S Package) 3 2 µv V CM =.7 3. mv V CM = (S Package) 1 4. mv V OS Input Offset Voltage Shift = V, V CM = V to 3.V 3 3 µv = 3V, V CM = V to 1.V 3 21 µv Input Offset Voltage Match (Channel-to-Channel) V CM = V µv (Note 9) V CM = V (DD Package) 3 22 µv V OS TC Input Offset Voltage Drift (Note 8) µv/ C (S Package) 3. µv/ C I B Input Bias Current V CM = 1V 2 2 na V CM =.2V 3 9 na Input Bias Current Match (Channel-to-Channel) V CM = 1V 2 na (Note 9) V CM =.2V 2 3 na I OS Input Offset Current V CM = 1V 2 na V CM =.2V 2 na A VOL Large Signal Voltage Gain = V, V O =.V to 4.V, at /2 2 7 V/mV = V, V O = 1.V to 3.V, R L = 1Ω at / V/mV = 3V, V O =.V to 2.V, at /2 2 6 V/mV CMRR Common Mode Rejection Ratio = V, V CM = V to 3.V 81 1 db = 3V, V CM = V to 1.V 77 1 db CMRR Match (Channel-to-Channel) (Note 9) = V, V CM = V to 3.V 76 1 db = 3V, V CM = V to 1.V 72 1 db Input Common Mode Range V PSRR Power Supply Rejection Ratio = 2.V to 1V, V CM = V db PSRR Match (Channel-to-Channel) (Note 9) db Minimum Supply Voltage (Note 6) V V OL Output Voltage Swing LOW (Note 7) No Load 1 6 mv I SINK = ma mv I SINK = 1mA 22 4 mv V OH Output Voltage Swing HIGH (Note 7) No Load 1 6 mv I SORCE = ma mv I SORCE = 1mA 32 6 mv I SC Short-Circuit Current = V ma = 3V ma I S Supply Current Per Amplifier ma GBW Gain-Bandwidth Product = V, Frequency = 1MHz 2 MHz SR Slew Rate = V, A V = 1,, V O = 4V 8 V/µs 62212fa

6 LT622/LT6221/LT6222 ELECTRICAL CHARACTERISTICS T A = 2 C, = ±V, V CM = V, V OT = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage V CM = V 8 µv V CM = V (DD Package) 7 µv V CM = V (S Package) 2 9 µv V CM = V.7 2. mv V CM = V (S Package).7 3 mv V OS Input Offset Voltage Shift V CM = V to 3.V 7 67 µv Input Offset Voltage Match (Channel-to-Channel) V CM = V 1 8 µv V CM = V (DD Package) 13 µv I B Input Bias Current V CM = 4V 2 na V CM = V 2 7 na Input Bias Current Match (Channel-to-Channel) V CM = 4V 17 na V CM = V 2 2 na I OS Input Offset Current V CM = 4V 1 na V CM = V 1 na Input Noise Voltage.1Hz to 1Hz. µv P-P e n Input Noise Voltage Density f = 1kHz 1 nv/ Hz i n Input Noise Current Density f = 1kHz.8 pa/ Hz C IN Input Capacitance f = 1kHz 2 pf A VOL Large Signal Voltage Gain V O = 4V to 4V, 3 9 V/mV V O = 2V to 2V, R L = 1Ω 3. 1 V/mV CMRR Common Mode Rejection Ratio V CM = V to 3.V db CMRR Match (Channel-to-Channel) 77 1 db Input Common Mode Range V PSRR Power Supply Rejection Ratio = 2.V to 1V, = V, V CM = V 84 db PSRR Match (Channel-to-Channel) 79 db V OL Output Voltage Swing LOW (Note 7) No Load 4 mv I SINK = ma 1 2 mv I SINK = 2mA 32 6 mv V OH Output Voltage Swing HIGH (Note 7) No Load 4 mv I SORCE = ma 13 2 mv I SORCE = 2mA 47 9 mv I SC Short-Circuit Current 2 ma I S Supply Current Per Amplifier 1 1. ma GBW Gain-Bandwidth Product Frequency = 1MHz 6 MHz SR Slew Rate A V = 1,, V O = ±4V, 2 V/µs Measure at V O = ±2V FPBW Full Power Bandwidth V O = 8V P-P.8 MHz HD Harmonic Distortion A V = 1,, V O = 2V p-p, f c = khz 77. dbc t S Settling Time.1%, TEP = V, A V = 1, 37 ns G Differential Gain (NTSC) A V = 2,. % θ Differential Phase (NTSC) A V = 2,.6 Deg fa

7 LT622/LT6221/LT6222 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the C TA 7 C temperature range. = ±V, V CM = V, V OT = V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage V CM = V 1 6 µv V CM = V (DD Package) 18 9 µv V CM = V (S Package) µv V CM = V.7 3 mv V CM = V (S Package).7 3. mv V OS Input Offset Voltage Shift V CM = V to 3.V 9 8 µv Input Offset Voltage Match (Channel-to-Channel) V CM = V 9 11 µv (Note 9) V CM = V (DD Package) 18 µv V OS TC Input Offset Voltage Drift (Note 8) 1. µv/ C (S Package) 3. 1 µv/ C I B Input Bias Current V CM = 4V 2 17 na V CM = 4.8V 27 8 na Input Bias Current Match (Channel-to-Channel) V CM = 4V 2 na (Note 9) V CM = 4.8V 2 3 na I OS Input Offset Current V CM = 4V 12 na V CM = 4.8V 12 na A VOL Large Signal Voltage Gain V O = 4V to 4V, 3 9 V/mV V O = 2V to 2V, R L =1Ω 3 9 V/mV CMRR Common Mode Rejection Ratio V CM = V to 3.V 8 1 db CMRR Match (Channel-to-Channel) (Note 9) 7 1 db Input Common Mode Range V PSRR Power Supply Rejection Ratio = 2.V to 1V, = V, V CM = V db PSRR Match (Channel-to-Channel) (Note 9) db V OL Output Voltage Swing LOW (Note 7) No Load 8 mv I SINK = ma mv I SINK = 2mA 37 7 mv V OH Output Voltage Swing HIGH (Note 7) No Load 8 mv I SORCE = ma 3 mv I SORCE = 2mA 6 11 mv I SC Short-Circuit Current 2 4 ma I S Supply Current Per Amplifier ma GBW Gain-Bandwidth Product Frequency = 1MHz 6 MHz SR Slew Rate A V = 1,, V O = ±4V, 18 V/µs Measure at V O = ±2V 62212fa 7

8 LT622/LT6221/LT6222 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the 4 C T A 8 C temperature range. = ±V, V CM = V, V OT = V, unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage V CM = V 8 µv V CM = V (DD Package) 3 13 µv V CM = V (S Package) 3 2 µv V CM = V.7 3. mv V CM = V (S Package) 1 4. mv V OS Input Offset Voltage Shift V CM = V to 3.V 9 9 µv Input Offset Voltage Match (Channel-to-Channel) V CM = V µv (Note 9) V CM = V (DD Package) 3 22 µv V OS TC Input Offset Voltage Drift (Note 8) µv/ C (S Package) 3. µv/ C I B Input Bias Current V CM = 4V 2 2 na V CM = 4.8V 3 9 na Input Bias Current Match (Channel-to-Channel) V CM = 4V 2 na (Note 9) V CM = 4.8V 2 3 na I OS Input Offset Current V CM = 4V 2 na V CM = 4.8V 2 na A VOL Large Signal Voltage Gain V O = 4V to 4V, 2 7 V/mV V O = 1V to 1V, R L = 1Ω 2. 8 V/mV CMRR Common Mode Rejection Ratio V CM = V to 3.V 79 1 db CMRR Match (Channel-to-Channel) (Note 9) 74 1 db Input Common Mode Range V PSRR Power Supply Rejection Ratio = 2.V to 1V, = V, V CM = V db PSRR Match (Channel-to-Channel) (Note 9) db V OL Output Voltage Swing LOW (Note 7) No Load 1 6 mv I SINK = ma mv I SINK = 1mA 22 4 mv V OH Output Voltage Swing HIGH (Note 7) No Load 1 6 mv I SORCE = ma mv I SORCE = 1mA 32 6 mv I SC Short-Circuit Current ma I S Supply Current ma GBW Gain-Bandwidth Product Frequency = 1MHz MHz SR Slew Rate A V = 1,, V O = ±4V, V/µs Measure at V O = ±2V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected by back-to-back diodes. If the differential input voltage exceeds 1.4V, the input current should be limited to less than 1mA. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 4: The LT622C/LT6221C/LT6222C and LT622I/LT6221I/LT6222I are guaranteed functional over the temperature range of 4 C and 8 C. Note : The LT622C/LT6221C/LT6222C are guaranteed to meet specified performance from C to 7 C. The LT622C/LT6221C/LT6222C are designed, characterized and expected to meet specified performance from 4 C to 8 C but is not tested or QA sampled at these temperatures. The LT622I/LT6221I/LT6222I are guaranteed to meet specified performance from 4 C to 8 C. Note 6: Minimum supply voltage is guaranteed by power supply rejection ratio test. Note 7: Output voltage swings are measured between the output and power supply rails. Note 8: This parameter is not 1% tested. Note 9: Matching parameters are the difference between amplifiers A and D and between B and C on the LT6222; between the two amplifiers on the LT6221. Note 1: Thermal resistance (θ JA ) varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. If desired, the thermal resistance can be substantially reduced by connecting Pin 2 of the LT622CS/LT622IS or the underside metal of DD packages to a larger metal area ( trace) fa

9 LT622/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS W V OS Distribution, V CM = V (S8, PNP Stage) V OS Distribution, V CM = V (SOT, PNP Stage) V OS Distribution, V CM = V (S8, NPN Stage) 4 = V, V V CM = V 4 = V, V V CM = V 4 = V, V V CM = V PERCENT OF NITS (%) PERCENT OF NITS (%) PERCENT OF NITS (%) INPT OFFSET VOLTAGE (µv) INPT OFFSET VOLTAGE (µv) INPT OFFSET VOLTAGE (µv) G G G3 PERCENT OF NITS (%) V OS Distribution, V CM = V (SOT, NPN Stage) 3 = V, V V CM = V INPT OFFSET VOLTAGE (µv) SPPLY CRRENT PER AMPLIFIER (ma) Supply Current vs Supply Voltage TOTAL SPPLY VOLTAGE (V) Offset Voltage vs Input Common Mode Voltage 3 7 = V, V TYPICAL PART 3 2 T A = C T A = 12 C 1 T A = 2 C T A = 2 C 1 1 T A = 12 C 3 T A = C OFFSET VOLTAGE (µv) INPT COMMON MODE VOLTAGE (V) G G G6 INPT BIAS CRRENT (na) Input Bias Current vs Common Mode Voltage = V, V T A = C T A = 2 C T A = 12 C COMMON MODE VOLTAGE (V) G7 INPT BIAS CRRENT (µa) Input Bias Current vs Temperature = V, V NPN ACTIVE V CM = V PNP ACTIVE V CM = 1V TEMPERATRE ( C) G8 OTPT SATRATION VOLTAGE (V) Output Saturation Voltage vs Load Current (Output Low) = V, V T A = 2 C T A = C T A = 12 C LOAD CRRENT (ma) G fa 9

10 LT622/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS W OTPT SATRATION VOLTAGE (V) Output Saturation Voltage vs Load Current (Output High) = V, V T A = 2 C T A = 12 C T A = C LOAD CRRENT (ma) G1 CHANGE IN OFFSET VOLTAGE (mv) Minimum Supply Voltage T A = C T A = 2 C T A = 12 C TOTAL SPPLY VOLTAGE (V) G11 OTPT SHORT-CIRCIT CRRENT (ma) Output Short-Circuit Current vs Power Supply Voltage 7 6 T A = 2 C T A = 12 C 4 3 T A = C SINKING T A = C SORCING 6 T A = 2 C T A = 12 C POWER SPPLY VOLTAGE (±V) G12 CHANGE IN OFFSET VOLTAGE (µv) Open-Loop Gain R L = 1Ω OTPT VOLTAGE (V) = 3V, V R L TO GND 2. 3 CHANGE IN OFFSET VOLTAGE (µv) Open-Loop Gain R L = 1Ω OTPT VOLTAGE (V) = V, V R L TO GND CHANGE IN OFFSET VOLTAGE (µv) Open-Loop Gain R L = 1Ω OTPT VOLTAGE (V) = ±V R L TO GND G G G CHANGE IN OFFSET VOLTAGE (mv) Offset Voltage vs Output Current Warm-p Drift vs Time Input Noise Voltage vs Frequency = ±V T A = C T A = 12 C OTPT CRRENT (ma) T A = 2 C G16 CHANGE IN OFFSET VOLTAGE (µv) LT6222 GN16 = ±2.V LT6222 GN16 = ±V LT622 SOT = ±2.V LT622 SOT = ±V LT6221 S8 = ±2.V LT6221 S8 = ±V TIME AFTER POWER-P (SECONDS) G17 NOISE VOLTAGE (nv/ Hz) = V, V NPN ACTIVE V CM = 4.2V PNP ACTIVE V CM = 2.V FREQENCY (khz) G fa

11 LT622/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS W NOISE CRRENT (pa/ Hz) Input Current Noise vs Frequency = V, V PNP ACTIVE V CM = 2.V NPN ACTIVE V CM = 4.2V OTPT NOISE VOLTAGE (nv).1hz to 1Hz Output Voltage Noise 8 = V, V GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Supply Voltage 9 T A = 2 C GAIN BANDWIDTH PRODCT PHASE MARGIN PHASE MARGIN (DEG) FREQENCY (khz) G TIME (SECONDS) G TOTAL SPPLY VOLTAGE (V) G21 GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Temperature A V = R F = R G = 1k GAIN BANDWIDTH PRODCT PHASE R = ±2.V 6 8 L = 1k = ±V 6 = ±V = ±V 2 4 V 4 S = ±2.V PHASE MARGIN = ±V GAIN = ±2.V 6 2 = ±V 2 V 1 2 S = ±2.V = ±2.V k 1k 1M 1M 1M TEMPERATRE ( C) FREQENCY (Hz) TEMPERATRE ( C) G22 PHASE MARGIN (DEG) GAIN (db) Gain and Phase vs Frequency G23 PHASE (DEG) SLEW RATE (V/µs) Slew Rate vs Temperature G24 GAIN (db) Gain vs Frequency (A V = 1) A V = 1 C L = 1pF FREQENCY (MHz) = ±2.V = ±V G2 GAIN (db) Gain vs Frequency (A V = 2) = ±2.V = ±V 3 6 A V = 2 9 R F = R G = 1k C F = 2pF 12 C L = 1pF FREQENCY (MHz) G26 OTPT IMPEDACNE (Ω) Output Impedance vs Frequency 1 = ±2.V 1 A 1 V = 1 1 A V = 2.1 A V = FREQENCY (MHz) 6212 G fa 11

12 LT622/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS W COMMON MODE REJECTION RATIO (db) Common Mode Rejection Ratio vs Frequency = V, V FREQENCY (MHz) G28 POWER SPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency = V, V NEGATIVE SPPLY POSITIVE SPPLY FREQENCY (MHz) G29 OVERSHOOT (%) Series Output Resistor vs Capacitive Load VS = V, V 4 A V = 1 4 R L =, NLESS NOTED 1 R OS = R L = Ω R OS = 2Ω R OS = 1Ω CAPACITIVE LOAD (pf) G31 OVERSHOOT (%) Series Output Resistor vs Capacitive Load 1 = V, V A V = 2 R L =, NLESS NOTED G32 DISTORTION (dbc) 3 Distortion vs Frequency = V, V = V, V 4 A V = 1 4 A V = 2 V OT = 2V P-P V OT = 2V P-P R L = Ω, R L = Ω, 6 2ND 6 3RD, R L = Ω, 2ND R L = Ω, 7 3RD 7 2ND R OS = 1Ω R 8 L = 1k, 2ND 8, 3RD 9, 9 R OS = 2Ω 1 3RD 1 R OS = R L = Ω CAPACITIVE LOAD (pf) FREQENCY (MHz) FREQENCY (MHz) G33 DISTORTION (dbc) 3 Distortion vs Frequency G34 OTPT VOLTAGE SWING (VP-P) Maximum ndistorted Output Signal vs Frequency A V = 1 A V = 2 1. VS = V, V FREQENCY (MHz) G3 1V/DIV V V Large-Signal Response = V, V 1ns/DIV G36 A V = 1 mv/div 2.V mall-signal Response = V, V ns/div G37 A V = fa

13 LT622/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS W ±V Large-Signal Response ±mall-signal Response Output Overdriven Recovery 2V/DIV V mv/div V V IN 1V/DIV V V OT 2V/DIV V = ±V 2ns/DIV G38 A V = 1 = ±V ns/div G39 A V = 1 = V, V 2ns/DIV G4 A V = 2 APPLICATIO S I FOR ATIO Circuit Description W The LT622/LT6221/LT6222 have an input and output signal range that covers from the negative power supply to the positive power supply. Figure 1 depicts a simplified schematic of the amplifier. The input stage comprises two differential amplifiers, a PNP stage, Q1/Q2, and an NPN stage, Q3/Q4, that are active over different ranges of common mode input voltage. The PNP stage is active between the negative supply to approximately 1.2V below the positive supply. As the input voltage moves closer toward the positive supply, the transistor Q will steer the tail current, I 1, to the current mirror, Q6/Q7, activating the NPN differential pair and the PNP pair becomes inactive for the rest of the input common mode range up to the positive supply. Also, at the input stage, devices Q17 to Q19 act to cancel the bias current of the PNP input pair. When Q1/Q2 are active, the current in Q16 is controlled to be the same as the current Q1/Q2. Thus, the base current of Q16 is nominally equal to the base current of the input devices. The base current of Q16 is then mirrored by devices Q17-Q19 to cancel the base current of the input devices Q1/Q2. V V V R3 R4 R I 2 IN ESDD1 ESDD2 D6 D D8 D7 D1 D2 Q V BIAS I 1 Q11 Q12 C C V Q13 I 3 C2 Q OT IN Q4 Q3 Q1 Q2 Q16 Q17 ESDD4 Q18 V ESDD3 V Q19 Q7 Q6 D3 D4 Q1 Q9 Q8 BFFER AND OTPT BIAS C1 Q14 V R1 R F1 Figure 1. LT622/LT6221/LT6222 Simplified Schematic Diagram 62212fa 13

14 LT622/LT6221/LT6222 APPLICATIO S I FOR ATIO A pair of complementary common emitter stages Q14/Q that enable the output to swing from rail-to-rail construct the output stage. The capacitors C2 and C3 form the local feedback loops that lower the output impedance at high frequency. These devices are fabricated by Linear Technology s proprietary high speed complementary bipolar process. Power Dissipation The LT6222, with four amplifiers, is housed in a small 16-lead SSOP package and typically has a thermal resistance (θ JA ) of 13 C/W. It is necessary to ensure that the die s junction temperature does not exceed C. The junction temperature, T J, is calculated from the ambient temperature, T A, power dissipation, P D, and thermal resistance, θ JA : T J = T A (P D θ JA ) W The power dissipation in the IC is the function of the supply voltage, output voltage and the load resistance. For a given supply voltage, the worst-case power dissipation P D(MAX) occurs when the maximum supply current and the output voltage is at half of either supply voltage for a given load resistance. P D(MAX) is given by: VS PD ( MAX) = ( VS IS( MAX) ) / R 2 Example: For an LT6222 in a 16-lead SSOP package operating on ±V supplies and driving a 1Ω load, the worst-case power dissipation is given by: PDMAX ( )/ Amp mA 2. / 1 = = 8. mw = ( ) ( ) If all four amplifiers are loaded simultaneously, then the total power dissipation is 322mW. The maximum ambient temperature at which the part is allowed to operate is: T A = T J (P D(MAX) 13 C/W) = C (.322W 13 C/W) = 16. C 2 L 2 Input Offset Voltage The offset voltage will change depending upon which input stage is active. The PNP input stage is active from the negative supply rail to 1.2V below the positive supply rail, then the NPN input stage is activated for the remaining input range up to the positive supply rail during which the PNP stage remains inactive. The offset voltage is typically less than 7µV in the range that the PNP input stage is active. Input Bias Current The LT622/LT6221/LT6222 employ a patent pending technique to trim the input bias current to less than na for the input common mode voltage of.2v above the negative supply rail to 1.2V below the positive rail. The low input offset voltage and low input bias current of the LT622/LT6221/LT6222 provide precision performance especially for high source impedance applications. Output The LT622/LT6221/LT6222 can deliver a large output current, so the short-circuit current limit is set around ma to prevent damage to the device. Attention must be paid to keep the junction temperature of the IC below the absolute maximum rating of C (refer to the Power Dissipation section) when the output is in continuous short circuit. The output of the amplifier has reversebiased diodes connected to each supply. If the output is forced beyond either supply, unlimited current will flow through these diodes. If the current is transient and limited to several hundred milliamperes, no damage will occur to the device. Overdrive Protection When the input voltage exceeds the power supplies, two pair of crossing diodes, D1 to D4, will prevent the output from reversing polarity. If the input voltage exceeds either power supply by 7mV, diode D1/D2 or D3/D4 will turn on to keep the output at the proper polarity. For the phase reversal protection to perform properly, the input current must be limited to less than ma. If the amplifier is fa

15 APPLICATIO S I FOR ATIO W severely overdriven, an external resistor should be used to limit the overdriven current. The LT622/LT6221/LT6222 s input stages are also protected against a large differential input voltage of 1.4V or higher by a pair of back-to-back diodes, D/D8, to prevent the emitter-base breakdown of the input transistors. The current in these diodes should be limited to less than 1mA when they are active. The worse-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity-gain configuration. In addition, the amplifier is protected against ESD strikes up to 3kV on all pins by a pair of protection diodes on each pin that are connected to the power supplies as shown in Figure 1. Capacitive Load The LT622/LT6221/LT6222 are optimized for high bandwidth, low power and precision applications. They can drive a capacitive load up to 1pF in a unity-gain configuration and more for higher gain. When driving a larger LT622/LT6221/LT6222 capacitive load, a resistor of 1Ω to Ω should be connected between the output and the capacitive load to avoid ringing or oscillation. The feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. Graphs on capacitive loads show the transient response of the amplifier when driving capacitive load with specified series resistors. Feedback Components When feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. For instance, the LT622/ LT6221/LT6222, set up with a noninverting gain of 2, two k resistors and a capacitance of pf (part plus PC board), will probably oscillate. The pole is formed at 12.7MHz that will reduce phase margin by 2 degrees when the crossover frequency of the amplifier is around 1MHz. A capacitor of 1pF or higher connecting across the feedback resistor will eliminate any ringing or oscillation. TYPICAL APPLICATIO S Stepped-Gain Photodiode Amplifier The circuit of Figure 2 is a stepped gain transimpedance photodiode amplifier. At low signal levels, the circuit has a high 1kΩ gain, but at high signal levels the circuit automatically and smoothly changes to a low 3.2kΩ gain. The benefit of a stepped gain approach is that it maximizes dynamic range, which is very useful on limited supplies. Put another way, in order to get 1kΩ sensitivity and still handle a 1mA signal level without resorting to gain reduction, the circuit would need a 1V negative voltage supply. The operation of the circuit is quite simple. At low photodiode currents (below 1µA) the output and inverting input of the op amp will be no more than 1V below ground. The LT1634 in parallel with R3 and Q2 keep a constant current though Q2 of about 2µA. R4 maintains quiescent current through the LT1634 and pulls Q2 s emitter above ground, so Q1 is reverse biased and no current flows through R2. So for small signals, the only feedback path is R1 (and C1) and the circuit is a simple transimpedance amplifier with 1kΩ gain. I PD PHOTODIODE ~4pF R2 3.24k R1 1k LT622 C2 3pF C1 1pF 2 R3 33k Figure 2. Stepped-Gain Photodiode Amplifier Q1 PHILIPS BCV = ±1.V TO ±V Q2 R4 1k LT V OT F fa

16 LT622/LT6221/LT6222 PACKAGE DESCRIPTIO As the signal level increases though, the output of the op amp goes more negative. At 12.µA of photodiode current, the 1kΩ gain dictates that the LT622 output will be about 1.2V below ground. However, at that point the emitter of Q2 will be at ground, and the base of Q1 will be 1V below ground. Thus, Q1 turns on and photodiode current starts to flow through R2. The transimpedance gain is therefore now reduced to R1 R2, or about 3.1kΩ. The circuit response is shown in Figure 3. Note the smooth transition between the two operating gains, as well as the linearity. GAIN (db) k 1k 1k 1M 1M 1M FREQENCY (Hz) F PHOTO CRRENT 1µA/DIV V OT.V/DIV Figure 3. Stepped-Gain Photodiode Amplifier Response Figure. Frequency Response of Filter Differential-In/Differential-Out Amplifier The circuit of Figure 6 shows the LT6222 applied as a buffered differential-in differential-out amplifier with a gain of 2. Op amps A and B are configured as simple unitygain buffers, offering high input impedance to upstream circuitry. Resistors R1 and R2 perform an averaging function on the common mode input voltage and R3 attenuates it by a factor of 2/3 and references it to the voltage source V OCM. The resultant voltage, V MID = 2/3 V ICM, is placed at the noninverting inputs of op amps C and D. The other four resistors set gains of 3 from the noninverting input and 2 through the inverting path. Thus the output voltage of the upper path is: F3 µs/div Single 3upply, 1MHz, 4th Order Butterworth Filter The circuit shown in Figure 4 makes use of the low voltage operation and the wide bandwidth of the LT6221 to create a DC accurate 1MHz 4th order lowpass filter powered from a 3V supply. The amplifiers are configured in the inverting mode for the lowest distortion and the output can swing rail-to-rail for maximum dynamic range. Figure displays the frequency response of the filter. Stopband attenuation is greater than 1dB at MHz. OT = 3 (2/3 V ICM 1/3 V OCM ) 2 (V ICM V DIFF /2) = 2V ICM V OCM 2V ICM V DIFF = V OCM V DIFF 99Ω 47pF V IN 99Ω 2.67k 22pF 1/2 LT k 1.1k 2.21k 47pF 22pF 3V 1/2 LT6221 V OT / F4 16 Figure 4. 3V, 1MHz, 4th Order Butterworth Filter 62212fa

17 LT622/LT6221/LT6222 PACKAGE DESCRIPTIO and the output of the lower path is: OT = 3 (2/3 V ICM 1/3 V OCM ) 2 (V ICM V DIFF /2) = 2V ICM V OCM 2V ICM V DIFF = V OCM V DIFF Note that the input common mode voltage does not appear in the output as either a common mode or a difference mode term. However the voltage V OCM does appear in the output terms, and with the same polarity, so it sets up the output DC level. Also, the differential input voltage V DIFF appears fully at both outputs with opposite polarity, giving rise to the effective differential gain of 2. Calculations show that using 1% resistors gives worst-case input common mode feedthrough better than 31dB, whether looking at the output common mode or difference mode. Considering the 6dB of gain, worst-case common mode rejection ratio is 37dB. (Remember this is assuming 1% resistors. Of course, this can be improved with more precise resistors.) Results achieved on the bench with typical 1% resistors showed 67dB of CMRR at low frequency and 4dB CMRR at 1MHz. Gains other than 2 can be achieved by setting R3 = α (R1 R2), R = α R4 and R7 = α R6 where gain = α. PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm 3mm) (Reference LTC DWG # ) R =.1.38 ±.1 TYP 8.67 ±. 3. ±. 2. ±. 1.6 ±. (2 SIDES).2 ±.. BSC 2.38 ±. (2 SIDES) PACKAGE OTLINE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK (NOTE 6) 3. ±.1 (4 SIDES) 1.6 ±.1 (2 SIDES) REF.7 ±..2 ±.. BSC 2.38 ±.1 (2 SIDES).. BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OTLINE M-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE (DD8) DFN fa 17

18 LT622/LT6221/LT6222 PACKAGE DESCRIPTIO.62 MAX.9 REF S Package -Lead Plastic TSOT-23 (Reference LTC DWG # ) 2.9 BSC (NOTE 4) 1.22 REF 3.8 MAX 2.62 REF 1.4 MIN 2.8 BSC (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOT PER IPC CALCLATOR.9 BSC.3.4 TYP PLCS (NOTE 3) BSC DATM A NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLSIVE OF PLATING MAX.3. REF BSC (NOTE 3) S TSOT DIMENSIONS ARE EXCLSIVE OF MOLD FLASH AND METAL BRR. MOLD FLASH SHALL NOT EXCEED.24mm 6. JEDEC PACKAGE REFERENCE IS MO fa

19 LT622/LT6221/LT6222 PACKAGE DESCRIPTIO S8 Package 8-Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # ). BSC.4 ± (4.81.4) NOTE MIN.16 ± ( )..7 ( ) NOTE 3.3 ±. TYP RECOMMENDED SOLDER PAD LAYOT (.24.8) (.23.24) 8 TYP.3.69 ( ).4.1 (.11.24).16. ( ) NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS) (.3.483) TYP 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.6" (.mm) SO8 33 GN Package 16-Lead Plastic SSOP (Narrow. Inch) (Reference LTC DWG # ). (1.27) BSC.4 ± * ( ) (.229) REF.24 MIN ( )..7** ( ).16 ±..2 BSC RECOMMENDED SOLDER PAD LAYOT ( ). ±.4 (.38 ±.1) 4 8 TYP ( ).4.98 ( ).16. ( ) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.2mm) PER SIDE **DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.1" (.24mm) PER SIDE.8.12 (.23.3) TYP.2 (.63) BSC Information furnished by Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. GN16 (SSOP) fa 19

20 LT622/LT6221/LT6222 TYPICAL APPLICATIO.6pF R 2k V ICM V DIFF /2 IN A 1/4 LT6222 R4 1k R1 2k V MID D 1/4 LT6222 R3 2k OT V OCM V ICM V DIFF /2 IN B 1/4 LT6222 R2 2k R6 1k C 1/4 LT6222 R7 2k OT.6pF F6 = ±1.3V TO ±6V BW 11MHz RELATED PARTS Figure 6. Buffered Gain of 2 Differential-In/Differential-Out Amplifier PART NMBER DESCRIPTION COMMENTS LT1498/LT1499 Dual/Quad 1MHz, 6V/µs Rail-to-Rail Input/ High DC Accuracy, 47µV V OS(MAX) Max Supply Current 2.2mA/Amp, Output C LOAD Op Amps Wide Supply Range, 2.2V to 3V LT18/LT181/LT182 Single/Dual/Quad 8MHz, 2V/µs, 3µV V OS(MAX), 2nA I BIAS(MAX), Max Supply Current 2mA/Amp Low Power Rail-to-Rail Input/Output Precision Op Amps LT183/LT184/LT18 Single/Dual/Quad 8MHz, 1V/µs 2mV V OS(MAX), Max Supply Current 3mA/Amp Rail-to-Rail Input/Output Op Amps LT186/LT187 Single/Dual 32MHz, 14V/µs Rail-to-Rail Input/ High DC Accuracy, µv V OS(MAX) Max Low Noise 3.nV/ Hz Output Op Amps Low Distortion 8dBc at MHz, Power Down (LT186) LT189/LT181 Single/Dual 18MHz, Rail-to-Rail Input/Output Op Amps 3V/µs Slew Rate, Low Distortion 9dBc at MHz, Power Down (LT189) 2 Linear Technology Corporation 62212fa LT/TP 24 1K PRINTED IN SA 163 McCarthy Blvd., Milpitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 23