DESCRIPTIO. LT685 High Speed Comparator FEATURES APPLICATIO S TYPICAL APPLICATIO

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1 High Speed Comparator FEATRES ltrafast (5.5ns typ) Complementary ECL Output 50Ω Line Driving Capability Low Offset Voltage Output Latch Capability External Hysteresis Control Pin Compatible with Am685 APPLICATIO S High Speed A-to-D Converters High Speed Sampling Circuits Oscillators DESCRIPTIO The LT 685 is an ultrafast comparator with differential inputs and complementary outputs fully compatible with ECL logic levels. The output current capability is adequate for driving transmission lines terminated in 50Ω. The low input offset and high resolution make this comparator ideally suited for analog-to-digital signal processing applications. A latch function is provided to allow the comparator to be used in a sample-hold mode. When the latch enable input is ECL high, the comparator functions normally. When the latch enable is driven low, the comparator outputs are locked in their existing logical states. If the latch function is not used, the latch enable must be connected to ground or ECL high. The device is pin-compatible with the Am685. Hysteresis has been added to improve switching time with slow input signals as well as to minimize oscillation. A single resistor between the hysteresis pin and V adds input hysteresis voltage as more current is drawn. If hysteresis is not required, the pin can be left unconnected., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO Comparator with Hysteresis 6V GND1 100 Hysteresis HYSTERESIS IS ZERO IF PIN LEFT OPEN V IN + V + V GND2 HYSTERESIS Q Q HYSTERESIS (mv) 10 LATCH ENABLE 5.2V R R L R L V T TA k 2k 5k 10k RESISTANCE (Ω) TA02 1

2 ABSOLTE AXI RATI GS W W W (Note 1) Positive Supply Voltage... 7V Negative Supply Voltage... 7V Input Voltage... ±4V Differential Input Voltage... ±6V Latch Pin Voltage... 2V to V Hysteresis Pin Voltage... 0V to V Output Current... 30mA Power Dissipation (Note 2) mW Operating Temperature C C T A 85 C M (OBSOLETE) C T A 125 C W PACKAGE/ORDER I FOR ATIO NONINVERTING INPT TOP VIEW GND #1 V + 10 GND # Q OTPT + INVERTING 3 7 Q OTPT INPT 4 6 LATCH 5 ENABLE V HYSTERESIS H PACKAGE TO-5 METAL CAN OBSOLETE PACKAGE Consider the N16 Package as an Alternate Source ORDER PART NMBER CH MH Consult LTC Marketing for parts specified with wider operating temperature ranges. GND #1 1 V + 2 NON-INVERTING INPT 3 INVERTING INPT 4 NC 5 LATCH ENABLE 6 NC 7 V 8 TOP VIEW N16 PACKAGE 16-LEAD CERDIP J16 PACKAGE (HERMETIC) 16-LEAD PDIP 16 GND #2 15 NC 14 NC 13 NC 12 Q OTPT 11 Q OTPT 10 NC 9 HYSTERESIS OBSOLETE PACKAGE Consider the N16 Package as an Alternate Source ORDER PART NMBER CN ORDER PART NMBER CJ MJ POI01 2

3 ELECTRICAL CHARACTERISTICS V + = 6.0V, V = 5.2V, V T = 2V, R L = 50Ω, R = over the operating temperature ranges, unless otherwise noted. C M SYMBOL PARAMETER CONDITIONS MIN TYP MIN TYP NITS V OS Input Offset Voltage T A = 25 C 1.0 ± ±2.0 mv ±2.5 ±3.0 mv dv OS /dt Input Offset Voltage Drift (Note 3) ±10 ±10 µv/ C l OS Input Offset Current T A = 25 C 0.3 ± ±1.0 µa ±1.3 ±1.6 µa I B Input Bias Current T A = 25 C µa µa R IN Input Resistance T A = 25 C (Note 3) kω C IN Input Capacitance T A = 25 C (Note 3) pf V CM lnput Voltage Range ±3.3 ±3.3 V CMRR Common Mode Rejection db SVRR Supply Voltage Rejection db V OH Output High Voltage T A = 25 C V T A = T MIN V T A = T V V OL Output Low Voltage T A = 25 C V T A = T MIN V T A = T V I + Positive Supply Current ma I Negative Supply Current ma P DISS Power Dissipation mw 3

4 SWITCHI G CHARACTERISTICS (V IN = 100mV step, 5mV overdrive) C M SYMBOL PARAMETER CONDITIONS MIN TYP MIN TYP NITS t PD Propagation Delay T A = 25 C ns (Note 4) T A = T ns T A = T MIN ns t PD(E) Latch Enable to T A = 25 C ns Output Delay T A = T ns (Note 3) T A = T MIN ns t S Minimum Set-p Time T MIN T A 25 C ns (Note 3) T A = T ns t H Minimum Hold Time T MIN T A T ns (Note 3) t PW(E) Minimum Latch Enable T MIN T A 25 C ns Pulse Width (Note 3) T A = T ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: For the metal can package, derate at 6.8mW/ C for operation at ambient temperatures above 100 C; for the hermetic dual-in-line package, derate at 9mW/ C for operation at ambient temperatures above 105 C. Note 3: Guaranteed by design, but not tested. Note 4: Sample tested at 25 C only. Definitions: t PD : The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of the output transition. t PD(E) : The propagation delay measured from the 50% point of the latch enable signal positive transition to the 50% point of the output transition. t S : The minimum time before the negative transition of the latch enable signal that an input signal change must be present in order to be acquired and held at the outputs. t H : The minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. t PW (E) : The minimum time that the latch enable signal must be HIGH in order to acquire and hold an input signal change. 4

5 5 SCHE ATIC DIAGRA W W R2 300Ω R1 300Ω R6 525Ω R5 525Ω R7 275Ω R17 150Ω V V + R16 2.1k R15 2.1k R13 3.0k R20 3.8k R21 846Ω R3 1.4k R4 2.4k R19 2.4k R14 3k R18 150Ω R10 880Ω R12 200Ω R11 430Ω R8 275Ω Q14 Q13 Q18 Q1 Q2 Q17 Q23 Q OTPT Q OTPT Q21 Q22 Q25 Q26 Q28 Q10 Q5 Q11 Q12 Q29 Q16 Q9 Q8 NONINVERTING INPT INVERTING INPT LATCH ENABLE HYSTERESIS Q6 Q7 D6 Q15 Q27 Q24 Q19 Q20 GND #2 D4 D1 D2 D3 D5 D7 D8 GND #1 R23 1.7k Q33 Q4 Q3 Q31 Q32 Q30 R22 2.9k S01

6 TYPICAL PERFOR A CE CHARACTERISTICS W PROPAGATION (ns) Propagation Delays as a Function of Temperature 2 50 V OD = 2.5mV V OD = 20mV V OD = 5mV V OD = 10mV TEMPERATRE ( C) LTC685 TPC01 HYSTERESIS (mv) Hysteresis as a Function of Temperature 0 50 R = 200Ω R = 500Ω R = 1000Ω TEMPERATRE ( C) LTC685 TPC02 PACKAGE DESCRIPTIO H Package 10-Lead TO-5 Metal Can (Reference LTC DWG # ) SEATING PLANE * ( ) ( ) DIA ( ) (1.016) (1.270) ( ) ** ( ) GAGE PLANE ( ) REFERENCE PLANE 36 BSC ( ) ( ) PIN ( 5.842) TYP ( ) INSLATING STANDOFF * LEAD DIAMETER IS NCONTROLLED BETWEEN THE REFERENCE PLANE AND 0.045" BELOW THE REFERENCE PLANE ** FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS ( ) H10(TO-5) 1197 OBSOLETE PACKAGE 6

7 PACKAGE DESCRIPTIO J Package 16-Lead CERDIP (Narrow.300 Inch, Hermetic) (Reference LTC DWG # ) CORNER LEADS OPTION (4 PLCS) (0.127) MIN (21.336) ( ) FLL LEAD OPTION BSC (0.762 BSC) ( ) HALF LEAD OPTION (0.635) RAD TYP ( ) (5.080) ( ) ( ) 0 15 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS (3.175) MIN ( ) ( ) (2.54) BSC J OBSOLETE PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7

8 PACKAGE DESCRIPTIO N Package 16-Lead PDIP (Narrow.300 Inch) (Reference LTC DWG # ) 0.770* (19.558) ± 0.015* (6.477 ± 0.381) ( ) ± (3.302 ± 0.127) ( ) ( ) ( ) (0.508) MIN (3.175) MIN *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED INCH (0.254mm) (2.54) BSC (1.651) TYP ± (0.457 ± 0.076) N Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA (408) FAX: (408) LW/TP K REV A PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 1988

TYPICAL APPLICATIO. LT MHz, 250V/µs, A V 4 Operational Amplifier DESCRIPTIO FEATURES APPLICATIO S

TYPICAL APPLICATIO. LT MHz, 250V/µs, A V 4 Operational Amplifier DESCRIPTIO FEATURES APPLICATIO S 5MHz, 5V/µs, A V Operational Amplifier FEATRES Gain-Bandwidth: 5MHz Gain of Stable Slew Rate: 5V/µs Input Noise Voltage: nv/ Hz C-Load TM Op Amp Drives Capacitive Loads Maximum Input Offset Voltage: µv