FEATURES APPLICATIO S TYPICAL APPLICATIO. LT1711/LT1712 Single/Dual 4.5ns, 3V/5V/±5V, Rail-to-Rail Comparators DESCRIPTIO

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1 FEATRES ltrafast:.ns at mv Overdrive.ns at mv Overdrive Rail-to-Rail Inputs Rail-to-Rail Complementary Outputs (TTL/CMOS Compatible) Specified at.v, V and ±V Supplies Output Latch Inputs Can Exceed Supplies Without Phase Reversal LT: -Lead MSOP Package LT: -Lead Narrow SSOP Package APPLICATIO S High Speed Automatic Test Equipment Current Sense for Switching Regulators Crystal Oscillator Circuits High Speed Sampling Circuits High Speed A/D Converters Pulse Width Modulators Window Comparators Extended Range V/F Converters Fast Pulse Height/Width Discriminators Line Receivers High Speed Triggers LT/LT Single/Dual.ns, V/V/±V, Rail-to-Rail Comparators DESCRIPTIO The LT /LT are ltrafast TM.ns comparators featuring rail-to-rail inputs, rail-to-rail complementary outputs and an output latch. Optimized for V and V power supplies, they operate over a single supply voltage range from.v to V or from ±.V to ±V dual supplies. The LT/LT are designed for ease of use in a variety of systems. In addition to wide supply voltage flexibility, rail-to-rail input common mode range extends mv beyond both supply rails, and the outputs are protected against phase reversal for inputs extending further beyond the rails. Also, the rail-to-rail inputs may be taken to opposite rails with no significant increase in input current. The rail-to-rail matched complementary outputs interface directly to TTL or CMOS logic and can sink ma to within.v of GND or source ma to within.v of V. The LT/LT have internal TTL/CMOS compatible latches for retaining data at the outputs. Each latch holds data as long as the latch pin is held high. Latch pin hysteresis provides protection against slow moving or noisy latch signals. The LT is available in the -pin MSOP package. The LT is available in the -pin narrow SSOP package., LTC and LT are registered trademarks of Linear Technology Corporation. ltrafast is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO 9Ω V M k pf LT pf MV-9 VARACTOR DIODE k M Y** pf pf A NTSC Subcarrier Voltage-Tunable Crystal Oscillator N M M* * % FILM RESISTOR ** NORTHERN ENGINEERING LABS C-N-.MHz V k* LT-..µF C SELECT (CHOOSE FOR CORRECT PLL LOOP RESPONSE).9k* k* FREENCY OTPT TA V TO V PROPAGATION DELAY (ns) LT/LT Propagation Delay vs Input Overdrive T A = C V = V V = V V STEP = mv INPT OVERDRIVE (mv) TA

2 ABSOLTE AXI RATI GS W W W Supply Voltage V to V....V V to GND....V V to GND...V to.v Differential Input Voltage... ±.V Latch Pin Voltage... V Input and Latch Current... ±ma W PACKAGE/ORDER I FOR ATIO (Note ) Output Current (Continuous)... ±ma Operating Temperature Range... C to C Specified Temperature Range (Note )... C to C Junction Temperature... C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C V IN IN V TOP VIEW MS PACKAGE -LEAD PLASTIC MSOP GND LATCH ENABLE T JMAX = C, θ JA = C/ W (NOTE ) ORDER PART NMBER LTCMS LTIMS MS PART MARKING LTTC LTTD IN A IN A V V V V IN B IN B TOP VIEW GN PACKAGE -LEAD PLASTIC SSOP LATCH ENABLE A GND A A B B GND LATCH 9 ENABLE B ORDER PART NMBER LTCGN LTIGN GN PART MARKING I T JMAX = C, θ JA = C/ W (NOTE ) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V =.V or V = V, V = V, V CM = V /, V LATCH =.V, C LOAD = pf, V OVERDRIVE = mv, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V Positive Supply Voltage Range. V V OS Input Offset Voltage (Note ) R S = Ω, V CM = V /.. mv R S = Ω, V CM = V /. mv R S = Ω, V CM = V. mv R S = Ω, V CM = V mv V OS / T Input Offset Voltage Drift µv/ C I OS Input Offset Current. µa µa I B Input Bias Current (Note ) µa µa V CM Input Voltage Range (Note 9). V. V CMRR Common Mode Rejection Ratio V = V, V V CM V db V = V, V V CM V db V =.V, V V CM.V db V =.V, V V CM.V db PSRR Positive Power Supply Rejection Ratio.V V V, V CM = V db db

3 ELECTRICAL CHARACTERISTICS LT/LT The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V =.V or V = V, V = V, V CM = V /, V LATCH =.V, C LOAD = pf, V OVERDRIVE = mv, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS PSRR Negative Power Supply Rejection Ratio V V V, V = V, V CM = V db db A V Small-Signal Voltage Gain (Note ) V/mV V OH Output Voltage Swing HIGH I OT = ma, V OVERDRIVE = mv V. V. V I OT = ma, V OVERDRIVE = mv V. V. V V OL Output Voltage Swing LOW I OT = ma, V OVERDRIVE = mv.. V I OT = ma, V OVERDRIVE = mv.. V I Positive Supply Current (Per Comparator) V = V, V OVERDRIVE = V 9 ma ma I Negative Supply Current (Per Comparator) V = V, V OVERDRIVE = V ma ma V IH Latch Pin High Input Voltage. V V IL Latch Pin Low Input Voltage. V I IL Latch Pin Current V LATCH = V µa Propagation Delay (Note ) = mv, V OVERDRIVE = mv.. ns = mv, V OVERDRIVE = mv. ns = mv, V OVERDRIVE = mv. ns Differential Propagation Delay (Note ) = mv, V OVERDRIVE = mv.. ns t r Output Rise Time % to 9% ns t f Output Fall Time 9% to % ns t LPD Latch Propagation Delay (Note ) ns t S Latch Setup Time (Note ) ns t H Latch Hold Time (Note ) ns t DPW Minimum Latch Disable Pulse Width (Note ) ns f MAX Maximum Toggle Frequency = mv P-P Sine Wave MHz t JITTER Output Timing Jitter = mv P-P (dbm) Sine Wave, f = MHz ps RMS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V = V, V = V, V CM = V, V LATCH =.V, C LOAD = pf, V OVERDRIVE = mv, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V Positive Supply Voltage Range. V V Negative Supply Voltage Range (Note ) V V OS Input Offset Voltage (Note ) R S = Ω, V CM = V.. mv R S = Ω, V CM = V. mv R S = Ω, V CM = V. mv R S = Ω, V CM = V mv V OS / T Input Offset Voltage Drift µv/ C I OS Input Offset Current. µa µa I B Input Bias Current (Note ) µa µa V CM Input Voltage Range.. V CMRR Common Mode Rejection Ratio V V CM V db db PSRR Positive Power Supply Rejection Ratio.V V V, V CM = V db db PSRR Negative Power Supply Rejection Ratio V V V, V CM = V db db

4 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V = V, V = V, V CM = V, V LATCH =.V, C LOAD = pf, V OVERDRIVE = mv, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS A V Small-Signal Voltage Gain V/mV V OH Output Voltage Swing HIGH (Note ) I OT = ma, V OVERDRIVE = mv.. V I OT = ma, V OVERDRIVE = mv.. V V OL Output Voltage Swing LOW (Note ) I OT = ma, V OVERDRIVE = mv.. V I OT = ma, V OVERDRIVE = mv.. V I Positive Supply Current (Per Comparator) V OVERDRIVE = V ma ma I Negative Supply Current (Per Comparator) V OVERDRIVE = V 9 ma ma V IH Latch Pin High Input Voltage. V V IL Latch Pin Low Input Voltage. V I IL Latch Pin Current V LATCH = V µa Propagation Delay (Notes, ) = mv, V OVERDRIVE = mv.. ns = mv, V OVERDRIVE = mv. ns = mv, V OVERDRIVE = mv. ns Differential Propagation Delay (Notes, ) = mv, V OVERDRIVE = mv.. ns t r Output Rise Time % to 9% ns t f Output Fall Time 9% to % ns t LPD Latch Propagation Delay (Note ) ns t S Latch Setup Time (Note ) ns t H Latch Hold Time (Note ) ns t DPW Minimum Latch Disable Pulse Width (Note ) ns f MAX Maximum Toggle Frequency = mv P-P Sine Wave MHz t JITTER Output Timing Jitter = mv P-P (dbm) Sine Wave, f = MHz ps RMS Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : The LTC/LTC are guaranteed to meet specified performance from C to C. They are designed, characterized and expected to meet specified performance from C to C but are not tested or A sampled at these temperatures. The LTI/LTI are guaranteed to meet specified performance from C to C. Note : The negative supply should not be greater than the ground pin voltage and the maximum voltage across the positive and negative supplies should not be greater than V. Note : Input offset voltage (V OS ) is measured with the LT/LT in a configuration that adds external hysteresis. It is defined as the average of the two hysteresis trip points. Note : Input bias current (I B ) is defined as the average of the two input currents. Note : Propagation delay ( ) is measured with the overdrive added to the actual V OS. Differential propagation delay is defined as: =. Load capacitance is pf. Due to test system requirements, the LT/LT propagation delay is specified with a kω load to ground for ±V supplies, or to mid-supply for.v or V single supplies. Note : Latch propagation delay (t LPD ) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (t S ) is the interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (t H ) is the interval after the latch is asserted in which the input signal must remain stable. Latch disable pulse width (t DPW ) is the width of the negative pulse on the latch enable pin that latches in new data on the data inputs. Note : Output voltage swings are characterized and tested at V = V and V = V. They are guaranteed by design and correlation to meet these specifications at V = V. Note 9: The input voltage range is tested under the more demanding conditions of V = V and V = V. The LT/LT are guaranteed by design and correlation to meet these specifications at V = V. Note : The LT/LT voltage gain is tested at V = V and V = V only. Voltage gain at single supply V = V and V =.V is guaranteed by design and correlation. Note : The LT/LT is tested at V = V and.v with V = V. Propagation delay at V = V, V = V is guaranteed by design and correlation. Note : Care must be taken to make sure that the LT/LT do not exceed T JMAX when operating with ±V supplies over the industrial temperature range. T JMAX is not exceeded for DC inputs, but supply current increases with switching frequency (see Typical Performance Characteristics).

5 TYPICAL PERFOR A CE CHARACTERISTICS W INPT OFFSET VOLTAGE (mv) Input Offset Voltage vs Temperature V = V V = V V CM = V V CM = V V CM =.V TEMPERATRE ( C) PROPAGATION DELAY (ns) 9 Propagation Delay vs Load Capacitance T A = C V = V V = V V CM =.V V OD = mv V STEP = mv LOAD CAPACITANCE (pf) PROPAGATION DELAY (ns) Propagation Delay vs Temperature V = V V = V V CM =.V V OD = mv V STEP = mv C LOAD = pf TEMPERATRE ( C) G G G PROPAGATION DELAY (ns) Propagation Delay vs Input Common Mode Voltage T A = C V = V V = V V OD = mv V STEP = mv C LOAD = pf INPT COMMON MODE (V) PROPAGATION DELAY (ns) Propagation Delay vs Positive Supply Voltage T A = C V = V V CM =.V V OD = mv V STEP = mv C LOAD = pf POSITIVE SPPLY VOLTAGE (V) POSITIVE SPPLY CRRENT (PER COMPARATOR) (ma) Positive Supply Current vs Positive Supply Voltage = mv I OT = ma V = V V = V I AT C I AT C I AT C POSITIVE SPPLY VOLTAGE (V) G G G POSITIVE SPPLY CRRENT (PER COMPARATOR) (ma) Positive Supply Current vs Switching Frequency T A = C V = V V = V C LOAD = pf SWITCHING FREENCY (MHz) NEGATIVE SPPLY CRRENT (PER COMPARATOR) (ma) Negative Supply Current vs Negative Supply Voltage V = V = mv I OT = ma I AT C I AT C I AT C NEGATIVE SPPLY VOLTAGE (V) INPT BIAS CRRENT (µa) Input Bias Current vs Input Common Mode Voltage V = V V = V = mv I B AT C I B AT C I B AT C INPT COMMON MODE VOLTAGE (V) G G G9

6 TYPICAL PERFOR A CE CHARACTERISTICS W INPT BIAS CRRENT (µa) Input Bias Current vs Temperature V = V V = V V CM =.V TEMPERATRE ( C) G OTPT VOLTAGE (V) Output High Voltage vs Source Current V OH AT C V OH AT C V OH AT C V = V V = V = mv. SORCE CRRENT (ma) G OTPT VOLTAGE (V) Output Low Voltage vs Sink Current. V = V V = V = mv V OL AT C V OL AT C V OL AT C. SINK CRRENT (ma) G OTPT TIMING JITTER (psrms) 9 Output Timing Jitter vs Switching Frequency Output Rising Edge, V Supply Output Falling Edge, V Supply FREENCY (MHz) T A = C V = V V = V V CM =.V = mv P-P (dbm) SINE WAVE G G G PI F CTIO S LT V (Pins ): Positive Supply Voltage, sually V. IN (Pin ): Noninverting Input. IN (Pin ): Inverting Input. V (Pins ): Negative Supply Voltage, sually V or V. LATCH ENABLE (Pin ): Latch Enable Input. With a logic high, the output is latched. GND (Pin ): Ground Supply Voltage, sually V. (Pin ): Noninverting Output. (Pin ): Inverting Output.

7 PI F CTIO S LT IN A (Pin ): Inverting Input of A Channel Comparator. IN A (Pin ): Noninverting Input of A Channel Comparator. V (Pins, ): Negative Supply Voltage, sually V. Pins and should be connected together externally. V (Pins, ): Positive Supply Voltage, sually V. Pins and should be connected together externally. IN B (Pin ): Noninverting Input of B Channel Comparator. IN B (Pin ): Inverting Input of B Channel Comparator. LATCH ENABLE B (Pin 9): Latch Enable Input of B Channel Comparator. With a logic high, the B output is latched. GND (Pin ): Ground Supply Voltage of B Channel Comparator, sually V. B (Pin ): Noninverting Output of B Channel Comparator. B (Pin ): Inverting Output of B Channel Comparator. A (Pin ): Inverting Output of A Channel Comparator. A (Pin ): Noninverting Output of A Channel Comparator. GND (Pin ): Ground Supply Voltage of A Channel Comparator, sually V LATCH ENABLE A (Pin ): Latch Enable Input of A Channel Comparator. With a logic high, the A output is latched. APPLICATIO S I FOR ATIO Common Mode Considerations W The LT/LT are specified for a common mode range of.v to.v on a ±V supply, or a common mode range of.v to.v on a single V supply. A more general consideration is that the common mode range is from mv below the negative supply to mv above the positive supply, independent of the actual supply voltage. The criteria for common mode limit is that the output still responds correctly to a small differential input signal. When either input signal falls outside the common mode limit, the internal PN diode formed with the substrate can turn on resulting in significant current flow through the die. Schottky clamp diodes between the inputs and the supply rails speed up recovery from excessive overdrive conditions by preventing these substrate diodes from turning on. Input Bias Current Input bias current is measured with the outputs held at.v with a V supply voltage. As with any rail-to-rail differential input stage, the LT/LT bias current flows into or out of the device depending upon the common mode level. The input circuit consists of an NPN pair and a PNP pair. For inputs near the negative rail, the NPN pair is inactive, and the input bias current flows out of the device; for inputs near the positive rail, the PNP pair is inactive, and these currents flow into the device. For inputs far enough away from the supply rails, the input bias current will be some combination of the NPN and PNP bias currents. As the differential input voltage increases, the input current of each pair will increase for one of the inputs and decrease for the other input. Large differential input voltages result in different input currents as the input stage enters various regions of operation. To reduce the influence of these changing input currents on system operation, use a low source resistance. Latch Pin Dynamics The internal latches of the LT/LT comparators retain the input data (output latched) when their respective latch pin goes high. The latch pin will float to a low state when disconnected, but it is better to ground the

8 APPLICATIO S I FOR ATIO latch when a flow-through condition is desired. The latch pin is designed to be driven with either a TTL or CMOS output. It has built-in hysteresis of approximately mv, so that slow moving or noisy input signals do not impact latch performance. For the LT, if only one of the comparators is being used at a given time, it is best to latch the second comparator to avoid any possibility of interactions between the two comparators in the same package. High Speed Design Techniques The extremely fast speed of the LT/LT necessitates careful attention to proper PC board layout and circuit design in order to prevent oscillations, as with most high speed comparators. The most common problem involves power supply bypassing which is necessary to maintain low supply impedance. Resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels, thereby allowing the supply voltages to move as the supply current changes. This movement of the supply voltages will often result in improper operation. In addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, thus keeping supply impedance low. Bypass capacitors should be as close as possible to the LT/LT supply pins. A good high frequency capacitor, such as a pf ceramic, is recommended in parallel with larger capacitors, such as a.µf ceramic and a.µf tantalum in parallel. These bypass capacitors should be soldered to the output ground plane such that the return currents do not pass through the ground plane under the input circuitry. The common tie point for these two ground planes should be at the board ground connection. Such stargrounding and ground plane separation is extremely important for the proper operation of ultra high speed circuits. Poor trace routes and high source impedances are also common sources of problems. Keep trace lengths as short as possible and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. If output traces are longer than a few inches, provide proper W termination impedances (typically Ω to Ω) to eliminate any reflections that may occur. Also keep source impedances as low as possible, preferably much less than kω. The input and output traces should also be isolated from one another. Power supply traces can be used to achieve this isolation as shown in Figure, a typical topside layout of the LT on a multilayer PC board. Shown is the topside metal etch including traces, pin escape vias and the land pads for a GN LT and its adjacent XR bypass capacitors. The V, V and GND traces all shield the inputs from the outputs. Although the two V pins are connected internally, they should be shorted together externally as well in order for both to function as shields. The same is true for the two V pins. The two GND pins are not connected internally, but in most applications they are both connected directly to the ground plane. F Figure. Typical LT Topside Metal for Multilayer PCB Layout Hysteresis Another important technique to avoid oscillations is to provide positive feedback, also known as hysteresis, from the output to the input. Increased levels of hysteresis, however, reduce the sensitivity of the device to input voltage levels, so the amount of positive feedback should be tailored to particular system requirements. The LT/LT are completely flexible regarding the application of hysteresis, due to rail-to-rail inputs and the complementary outputs. Specifically, feedback resistors can be connected from one of the outputs to its corresponding input without regard to common mode considerations. Figure shows several configurations.

9 APPLICATIO S I FOR ATIO W Ω k LT V = V V = V V HYST = mv (ALL CASES) Ω V REF k LT Ω Ω k k LT F Figure. Various Configurations for Introducing Hysteresis TYPICAL APPLICATIO S Simultaneous Full Duplex Mbaud Interface with Only Two Wires The circuit of Figure shows a simple, fully bidirectional, differential -wire interface that gives good results to Mbaud, using the LT. Eye diagrams under conditions of unidirectional and bidirectional communication are shown in Figures and. Although not as pristine as the unidirectional performance of Figure, the performance under simultaneous bidirectional operation is still excellent. Because the LT input voltage range extends mv beyond both supply rails, the circuit works with a full ±V (one whole V S up or down) of ground potential difference. The circuit works well with the resistor values shown, but other sets of values can be used. The starting point is the characteristic impedance, Z O, of the twisted-pair cable. The input impedance of the resistive network should match the characteristic impedance and is given by: R IN R ( R R) = RO R R ( R R) O [ ] k k RxD V / LE LT V / LT LE RxD k k V V k k TxD 9.9Ω 9.9Ω / LT LE 9 V RA.k RA Ω RB Ω RA 99Ω R OA Ω RB 99Ω -FEET TWISTED PAIR Z O Ω RC 99Ω R OB Ω RD 99Ω RC.k RC Ω RD Ω V / LT LE 9 9.9Ω 9.9Ω TxD k RB.k DIODES: BAV99 RD.k k F Figure. Mbaud Full Duplex Interface on Two Wires 9

10 TYPICAL APPLICATIO S F Figure. Performance of Figure s Circuit When Operated nidirectionally. Eye is Wide Open This comes out to Ω for the values shown. The Thevenin equivalent source voltage is given by: R R R VTH = VS ( ) ( R R R) RO RO [ R ( R R) ] This amounts to an attenuation factor of.9 with the values shown. (The actual voltage on the lines will be cut in half again due to the Ω Z O.) The reason this attenuation factor is important is that it is the key to deciding the ratio between the R-R resistor divider in the receiver path. This divider allows the receiver to reject the large signal of the local transmitter and instead sense the attenuated signal of the remote transmitter. Note that in the above equations, R and R are not yet fully determined because they only appear as a sum. This allows the designer to now place an additional constraint on their values. The R-R divide ratio should be set to equal half the attenuation factor mentioned above or: R/R = /.9. Having already designed R R to be.k (by allocating input impedance across R O, R and R R to get the requisite Ω), R and R then become 9Ω and.ω respectively. The nearest % value for R is.k and that for R is Ω. Voltage-Tunable Crystal Oscillator The front page application is a variant of a basic crystal oscillator that permits voltage tuning of the output frequency. Such voltage-controlled crystal oscillators (VCXO) F Figure. Performance When Operated Simultaneous Bidirectionally (Full Duplex). Crosstalk Appears as Noise. Eye is Slightly Shut But Performance is Still Excellent are often employed where slight variation of a stable carrier is required. This example is specifically intended to provide a NTSC sub-carrier tunable oscillator suitable for phase locking. The LT is set up as a crystal oscillator. The varactor diode is biased from the tuning input. The tuning network is arranged so a V to V drive provides a reasonably symmetric, broad tuning range around the.mhz center frequency. The indicated selected capacitor sets tuning bandwidth. It should be picked to complement loop response in phase locking applications. Figure is a plot of tuning input voltage versus frequency deviation. Tuning deviation from the NTSC.MHz center frequency exceeds ±ppm for a V to V input. sing the design value of R R =.k rather than the implementation value of.k Ω =.k. FREENCY DEVIATION (khz) 9.MHz.MHz.MHz INPT VOLTAGE (V) F Figure. Control Voltage vs Output Frequency for the Front Page Application Circuit. Tuning Deviation from Center Frequency Exceeds ±ppm

11 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. MS Package -Lead Plastic MSOP (LTC DWG # --). ±.* (. ±.).9 ±. (.9 ±.). ±.** (. ±.). (.). ±. (. ±.) TYP SEATING PLANE. (.) MAX.9. (..). (.) BSC * DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED." (.mm) PER SIDE. (.) REF. ±. (. ±.) MSOP (MS) GN Package -Lead Plastic SSOP (Narrow.) (LTC DWG # --).9.9* (..9) 9.9 (.9) REF.9. (..9)..** (..9)..9 (..9). ±. (. ±.) TYP.. (..)..9 (..9).. (..) * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.. (.) BSC GN (SSOP) 9

12 TYPICAL APPLICATIO MHz Series Resonant Crystal Oscillator with Square and Sinusoid Outputs Figure shows a classic MHz series resonant crystal oscillator. At series resonance, the crystal is a low impedance and the positive feedback connection is what brings about oscillation at the series resonant frequency. The RC feedback around the other path ensures that the circuit does not find a stable DC operating point and refuse to oscillate. The comparator output is a MHz square wave (top trace of Figure ) with jitter measured at better than ps RMS on a V supply and ps RMS on a V supply. At Pin of the comparator, on the other side of the crystal, is a clean sine wave except for the presence of the small high frequency glitch (middle trace of Figure ). This glitch is caused by the fast edge of the comparator output feeding back through crystal capacitance. Amplitude stability of the sine wave is maintained by the fact that the sine wave is basically a filtered version of the square wave. Hence, the usual amplitude control loops associated with sinusoidal oscillators are not necessary. The sine wave is filtered and buffered by the fast, low noise LT op amp. To remove the glitch, the LT is configured as a bandpass filter with a of and unity-gain center frequency of MHz, with its output shown as the bottom trace of Figure. Distortion was measured at dbc and dbc on the second and third harmonics, respectively. R k R.9k C pf R Ω C pf Amplitude will be a linear function of comparator output swing, which is supply dependent and therefore adjustable. The important difference here is that any added amplitude stabilization or control loop will not be faced with the classical task of avoiding regions of nonoscillation versus clipping. V S R k R k V S MHz AT-CT R Ω LT LE R k SARE R9 k V S C.µF C pf R k V S LTS R.k F SINE V/DIV V/DIV V/DIV C.µF Figure. LT Comparator is Configured as a Series Resonant Xtal Oscillator. LT Op Amp is Configured in a = Bandpass with f C = MHz ns/div F Figure. Oscillator Waveforms with V S = V. Top is Comparator Output. Middle is Xtal Feedback to Pin at LT (Note the Glitches). Bottom is Buffered, Inverted and Bandpass Filtered with a = by LT RELATED PARTS PART NMBER DESCRIPTION COMMENTS LT ltrafast Precision Comparator Industry Standard ns Comparator LT ns Single Supply Ground Sensing Comparator Single Supply Version of the LT LT9 ns, ltrafast Single Supply Comparator ma Single Supply Comparator LT ns, Low Power, Single Supply Comparator µa Single Supply Comparator LT/LT Single/Dual ns, Low Power, V/V/±V, R-R Comparator ns/ma versions of the LT/LT LT9.ns, Single Supply V/V/±V Comparator ma Comparator with Rail-to-Rail Outputs and Level Shifting LT/LT Dual/uad,.ns, Single Supply Comparator Dual/uad Version of the LT9 Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - f LT/TP K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION