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2 LTC Micropower Quad -Bit DAC FEATRES Tiny: DACs in the Board Space of an SO- Micropower: µa per DAC Plus µa Sleep Mode for Extended Battery Life Wide.V to.v Supply Range Rail-to-Rail Voltage Outputs Drive pf Reference Range Includes Supply for Ratiometric V-to-V CC Output Reference Input Impedance is Code-Independent Eliminates External Reference Buffer Individually Addressable DACs Differential Nonlinearity: ±.LSB Max Pin-Compatible Octal Version Available (LTC) APPLICATIO S Mobile Communications Remote Industrial Devices Automatic Calibration for Manufacturing Portable Battery-Powered Instruments Trim/Adjust Applications DESCRIPTIO The LTC integrates four accurate, serially addressable -bit digital-to-analog converters (DACs) in a tiny -pin Narrow SSOP package. Each buffered DAC draws just µa total supply current, yet is capable of supplying DC output currents in excess of ma and reliably driving capacitive loads of up to pf. Sleep mode further reduces total supply current to µa. Linear Technology s proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. ltralow supply current, power-saving Sleep mode and extremely compact size make the LTC ideal for battery-powered applications, while its ease of use, high performance and wide supply range make it an excellent choice as a general-purpose converter., LTC and LT are registered trademarks of Linear Technology Corporation. BLOCK DIAGRA W GND V CC V OT A -BIT -BIT DAC A DAC D V OT D... Differential Nonlinearity (DNL) V CC = V V REF =.V V OT B -BIT -BIT DAC B DAC C V OT C.. LSB. REF CONTROL LOGIC ADDRESS DECODER CLR... CS/LD SCK SHIFT REGISTER D OT D IN. CODE G BD

3 LTC ABSOLTE AXI RATI GS W W W (Note ) V CC to GND....V to.v Logic Inputs to GND....V to.v V OT A, V OT B V OT D, REF to GND....V to (V CC.V) Maximum Junction Temperature... C Operating Temperature Range LTCC... C to C LTCI... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR GND V OT A V OT B V OT C V OT D REF CS/LD SCK TOP VIEW GN PACKAGE -LEAD PLASTIC SSOP V CC NC NC NC NC CLR D OT D IN N PACKAGE -LEAD PDIP T JMAX = C, θ JA = C/W (GN) T JMAX = C, θ JA = C/W (N) W ATIO ORDER PART NMBER LTCCGN LTCCN LTCIGN LTCIN GN PART MARKING I Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V CC =.V to.v, V REF V CC, V OT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITONS MIN TYP MAX NITS Accuracy Resolution Bits Monotonicity (Notes, ) Bits DNL Differential Nonlinearity (Notes, ) ±. ±. LSB INL Integral Nonlinearity (Notes, ) ±. ±. LSB V OS Offset Error (Note ) ± ± mv V OS Temperature Coefficient ± µv/ C FSE Full-Scale Error V CC = V, V REF =.V (Note ) ± ± LSB Full-Scale Error Temperature Coefficient ± µv/ C PSR Power Supply Rejection V REF =.V. LSB/V Reference Input Input Voltage Range V CC V Resistance Not in Sleep Mode kω Capacitance pf I REF Reference Current Sleep Mode. µa Power Supply V CC Positive Supply Voltage.. V I CC Supply Current V CC = V (Note ) µa V CC = V (Note ) µa Sleep Mode (Note ) µa

4 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V CC =.V to.v, V REF V CC, V OT unloaded, unless otherwise noted. TI I G CHARACTERISTICS W LTC SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS DC Performance Short-Circuit Current Low V OT = V, V CC =.V, V REF =.V, ma Code = (Note ) Short-Circuit Current High V OT = V CC =.V, V REF =.V, Code = (Note ) ma AC Performance Voltage Output Slew Rate Rising (Notes, ). V/µs Falling (Notes, ). V/µs Digital I/O The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (See Figure ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V CC =.V to.v t D IN Valid to SCK Setup ns t D IN Valid to SCK Hold ns t SCK High Time (Note ) ns t SCK Low Time (Note ) ns t CS/LD Pulse Width (Note ) ns t LSB SCK High to CS/LD High (Note ) ns t CS/LD Low to SCK High (Note ) ns t D OT Propagation Delay C LOAD = pf (Note ) ns t SCK Low to CS/LD Low (Note ) ns t CLR Pulse Width (Note ) ns t CS/LD High to SCK Positive Edge (Note ) ns V CC =.V to.v Voltage Output Settling Time Rising.V FS to.v FS ±.LSB (Notes, ) µs Falling.V FS to.v FS ±.LSB (Notes, ) µs Capacitive Load Driving pf V IH Digital Input High Voltage V CC =.V to.v. V V CC =.V to.v. V V IL Digital Input Low Voltage V CC =.V to.v. V V CC =.V to.v. V V OH Digital Output High Voltage I OT = ma, D OT Only V CC V V OL Digital Output Low Voltage I OT = ma, D OT Only. V I LK Digital Input Leakage V IN = GND to V CC. ± µa C IN Digital Input Capacitance pf SCK Frequency (Notes and ). MHz t D IN Valid to SCK Setup (Note ) ns t D IN Valid to SCK Hold (Note ) ns t SCK High Time (Note ) ns t SCK Low Time (Note ) ns

5 LTC TI I G CHARACTERISTICS W The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (See Figure ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS t CS/LD Pulse Width (Note ) ns t LSB SCK High to CS/LD High (Note ) ns t CS/LD Low to SCK High (Note ) ns t D OT Propagation Delay C LOAD = pf (Note ) ns t SCK Low to CS/LD Low (Note ) ns t CLR Pulse Width (Note ) ns t CS/LD High to SCK Positive Edge (Note ) ns SCK Frequency (Notes and ) MHz Note : Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note : Nonlinearity and monotonicity are defined and tested at V CC = V, V REF =.V, from code to code. See Rail-to-Rail output considerations. Note : Digital inputs at V or V CC. Note : Load is kω in parallel with pf. Note : V CC = V REF = V. Note : Guaranteed by design and not subject to test. Note : Measured at code. Note : If a continuous clock is used, CS/LD timing (t and t ) will limit the maximum clock frequency to MHz at.v to.v(.mhz at.v to.v). Note : Any output shorted. TYPICAL PERFOR A CE CHARACTERISTICS W LSB Integral Nonlinearity (INL) V CC = V V REF =.V CODE G LSB Differential Nonlinearity (DNL) V CC = V V REF =.V. CODE G SPPLY CRENT (µa) Supply Current vs Temperature V REF = V CC CODE = V CC =.V V CC =.V V CC =.V V CC =.V TEMPERATRE ( C) G

6 LTC TYPICAL PERFOR A CE CHARACTERISTICS W Load Regulation vs Output Current Load Regulation vs Output Current Large-Signal Step Response. V CC = V REF = V CODE =. V CC = V REF = V CODE = V CC = V REF = V % TO % STEP V OT (LSB).. VOT (LSB).. VOT (V).. SORCE SINK I OT (ma) SORCE SINK I OT (µa) TIME (µs) G G G Midscale Output Voltage vs Load Current Midscale Output Voltage vs Load Current Supply Current vs Logic Input Voltage VOT (V) V REF = V CC CODE = SORCE V CC =.V V CC = V V CC =.V SINK I OT (ma) VOT (V) V REF = V CC. CODE =.. V CC =.V.. V CC = V.. V CC =.V.. SORCE SINK I OT (ma) SPPLY CRRENT (ma) ALL DIGITAL INPTS SHORTED TOGETHER LOGIC INPT VOLTAGE (V) G G G Minimum V OT vs Load Current (Output Sinking) Minimum Supply Headroom vs Load Current (Output Sourcing) V CC = V CODE = C V REF =.V V OT < LSB CODE = VOT (mv) C C VCC VOT (mv) C C C I OT (ma) (Sinking) G I OT (ma) (Sourcing) G

7 LTC PIN FNCTIONS GND (Pin ): System Ground. V OT A to V OT D (Pins ): DAC Analog Voltage Outputs. The output range is to V REF REF (Pin ): Reference Voltage Input. V V REF V CC. CS/LD (Pin ): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on D IN into the register. When CS/LD is pulled high, SCK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible. SCK (Pin ): Serial Interface Clock Input. CMOS and TTL compatible. D IN (Pin ): Serial Interface Data Input. Data on the D IN pin is shifted into the -bit register on the rising edge of SCK. CMOS and TTL compatible. D OT (Pin ): Serial Interface Data Output. Data appears on D OT positive SCK edges after being applied to D IN. May be tied to D IN of another serial device for daisy-chain operaton. CMOS and TTL compatible. CLR (Pin ): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible. NC (Pins ): Make no electrical connection to these pins. V CC (Pin ): Supply Voltage Input..V V CC.V.

8 LTC BLOCK DIAGRA W GND V CC V OT A -BIT -BIT DAC A DAC D V OT D V OT B -BIT -BIT DAC B DAC C V OT C REF CONTROL LOGIC ADDRESS DECODER CLR CS/LD SHIFT REGISTER D OT SCK D IN BD W W TI I G DIAGRA t t t t t SCK t t D IN A A A X X t t CS/LD t D OT A A A X X A F Figure

9 LTC OPERATIO Transfer Function The transfer function is V k ( ) = V OT IDEAL REF where k is the decimal equivalent of the binary DAC input code and V REF is the voltage at REF (Pin ). Power-On Reset The LTC clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Power Supply Sequencing The voltage at REF (Pin ) should be kept within the range.v V REF V CC.V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at V CC (Pin ) is in transition. If it is not possible to sequence the supplies, connect a Schottky diode from REF (anode) to V CC (cathode). Serial Interface Referring to Figure : With CS/LD held low, data on the D IN input is shifted into the -bit shift register on the positive edge of SCK. The -bit DAC address, A-A, is loaded first (see Table ), then the -bit input code, D-D, ordered MSB-to-LSB in each case. Two don t-care bits, X-X, are loaded last. When the full -bit input word has been shifted in, CS/LD is pulled high, loading the DAC register with the word and causing the addressed DAC output(s) to update. The clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low. The buffered serial output of the shift register is available on the D OT pin, which swings from GND to V CC. Data appears on D OT positive SCK edges after being applied to D IN. Multiple LTC s can be controlled from a single -wire serial port (i.e., SCK, D IN and CS/LD) by using the included daisy-chain facility. A series of m chips is configured by connecting each D OT (except the last) to D IN of the next chip, forming a single m-bit shift register. The SCK and CS/LD signals are common to all chips in the chain. In use, CS/LD is held low while m -bit words are clocked to D IN of the first chip; CS/LD is then pulled high, updating all of them simultaneously. Sleep Mode DAC address b is reserved for the special Sleep instruction (see Table ). In this mode, the digital interface stays active while the analog circuits are disabled; static power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. Sleep mode is initiated by performing a load sequence to address b (the DAC input word D-D is ignored). Once in Sleep mode, a load sequence to any other address (including No Change address b ) causes the LTC to Wake. It is possible to keep one or more chips of a daisy chain in continuous Sleep mode by giving the Sleep instruction to these chips each time the active chips in the chain are updated. Table. LTC Input Word A A A A D D D D D D D D D D X X Address/Control Input Code Don t Care

10 LTC OPERATIO SCK D IN A A A A D D D D D D D D D D X X ADDRESS/CONTROL INPT CODE DON T CARE INPT WORD W CS/LD (ENABLE SCK) (PDATE OTPT) D OT A A A A D D D D D D D D D D X X A INPT WORD W INPT WORD W F Figure. LTC Register Loading Sequence Table. DAC Address/Control Functions ADDRESS/CONTROL A A A A DAC STATS SLEEP STATS No Change Wake Load DAC A Wake Load DAC B Wake Load DAC C Wake Load DAC D Wake Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved No Change Sleep Load ALL DACs Wake with Same -Bit Code

11 OPERATIO LTC Voltage Outputs Each of the four rail-to-rail output amplifiers contained in the LTC can source or sink up to ma. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of Ω when driving a load to the rails. The output amplifiers are stable driving capacitive loads of up to pf. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. A µf load can be successfully driven by inserting a Ω resistor; a.µf load needs only a Ω resistor. In either case, larger values of resistance, capacitance or both may be safely substituted for the values given. Rail-to-Rail Output Considerations In any rail-to-rail voltage output DAC, the output is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at V as shown in Figure b. Similarly, limiting can occur near full scale when the REF pin is tied to V CC. If V REF = V CC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at V CC as shown in Figure c. No full-scale limiting can occur if V REF is less than V CC FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.

12 LTC OPERATIO V REF = V CC POSITIVE FSE OTPT VOLTAGE INPT CODE (c) V REF = V CC OTPT VOLTAGE INPT CODE (a) OTPT VOLTAGE NEGATIVE OFFSET V INPT CODE (b) / F Figure. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V REF = V CC

13 LTC TYPICAL APPLICATIONS A Low Power Dual Trim Circuit with Coarse/Fine Adjustment V OT R Ω.µF.V.V R k.v.µf A LT.µF.µF GND V CC LTC R Ω COARSE V OT A V OT D DAC A DAC D R k FINE V OT B DAC B DAC C V OT C R Ω COARSE R k FINE R k.µf B LT R Ω V OT LTC-. REF CLR CS/LD CONTROL LOGIC ADDRESS DECODER D OT TO OTHER LTCs -WIRE SERIAL INTERFACE SCK SHIFT REGISTER D IN V CODE A OT = V REF R CODE B R =.V CODE A CODE B ) V CODE D R CODE C OT = V REF R ) =.V CODE D CODE C ) ) ) ) ) ) TA

14 LTC TYPICAL APPLICATIONS A -Channel Bipolar Output Voltage Circuit Configuration V V OT A ±V.µF R V S A LT.µF R GND V OT A LTC DAC A DAC D.µF V CC V OT D R D LT R V OT D ±V V S R R R R V OT B ±V B LT V OT B DAC B DAC C V OT C C LT V OT C ±V REF CLR -WIRE SERIAL INTERFACE CS/LD CLK CONTROL LOGIC SHIFT REGISTER ADDRESS DECODER D OT D IN CODE V OT X V V.V TA

15 LTC PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. GN Package -Lead Plastic SSOP (Narrow.) (LTC DWG # --)..* (..). (.) REF.. (..)..** (..).. (..). ±. (. ±.) TYP.. (..).. (..).. (..) * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..). (.) BSC GN (SSOP)

16 LTC PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package -Lead PDIP (Narrow.) (LTC DWG # --).* (.) MAX. ±.* (. ±.).. (..). ±. (. ±.).. (..).. (..) ( ). (.) MIN. (.) MIN *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) BSC. (.) TYP. ±. (. ±.) N Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

17 LTC TYPICAL APPLICATION An -Bit Pin Driver V H and V L Adjustment Circuit for ATE Applications V.µF CLR V CC REF LTC DAC A DAC B DAC C DAC D V H (FROM MAIN DAC) V.µF R F R G k V A k V H = V H V H A LT.µF V B V C V D R G k V L (FROM MAIN DAC) R G k R G k R F k V B LT.µF R F k R F k V L = V L V L.µF LOGIC DRIVE V L V H V L PIN DRIVER V H V OT TA CS/LD D IN SCK GND CODE A CODE B VH, VL mv mv mv mv mv mv V A = V C =.V V H = V H R F (V A V B ) R G V L = V L R F (V C V D ) R G For Resistor Values Shown: Adjustment Range = ±mv Adjustment Step Size = µv RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC/LTC Octal /-Bit V OT DAC in -Pin Narrow SSOP V CC =.V to.v, µa per DAC, Rail-to-Rail Output LTC Dual -Bit V OT DAC in -Pin MSOP Package V CC =.V to.v, µa per DAC, Rail-to-Rail Output LTC ltra Low Power Dual -Bit V OT DAC in -Pin MSOP Package V CC =.V to.v,.µa per DAC, Rail-to-Rail Output LTC Single -Bit V OT DAC with -Wire Interface in SOT- Package V CC =.V to.v, Internal Reference, µa LTC/LTCL Dual -Bit V OT DACs in SO- Package with Internal Reference LTC: V CC =.V to.v, V OT = V to.v LTCL: V CC =.V to.v, V OT = V to.v LTC Dual -Bit V OT DAC in SO- Package V CC =.V to.v, External Reference Can Be Tied to V CC LTC/LTCL Dual -Bit V OT DACs in SO- Package with Added Functionality LTC: V CC =.V to.v, V OT = V to.v LTCL: V CC =.V to.v, V OT = V to.v LTC/LTCL Quad -Bit Rail-to-Rail Output DACs with Added Functionality LTC: V CC =.V to.v, V OT = V to.v LTCL: V CC =.V to.v, V OT = V to.v LT Micropower Precision Series Reference,.V, V, V Versions.% Max, ppm/ C Max, Only µa Supply Current LTC Dual -Bit I OT DAC in SO- Package V CC =.V to.v, -Quadrant Multiplication LTC Dual -Bit DAC in SO- Footprint LBS DNL, Selectable Speed/Power LTC Single Rail-to-Rail -Bit V OT DAC in -Lead MSOP Package Low Power Multiplying V OT DAC. Output Swings from V CC :.V to.v GND to REF. REF Input Can Be Tied to V CC Linear Technology Corporation McCarthy Blvd., Milpitas, CA - ()- FAX: () - f LT/TP K PRINTED IN THE SA LINEAR TECHNOLOGY CORPORATION

LTC1664 Micropower Quad 10-Bit DAC. Applications. Block Diagram

LTC1664 Micropower Quad 10-Bit DAC. Applications. Block Diagram LTC Micropower Quad -Bit DAC Features n Tiny: DACs in the Board Space of an SO- n Micropower: µa per DAC Plus µa Sleep Mode for Extended Battery Life n Wide.V to.v Supply Range n Rail-to-Rail Voltage Outputs