FEATURES APPLICATIO S. LTC1588/LTC1589/LTC /14-/16-Bit SoftSpan DACs with Programmable Output Range DESCRIPTIO TYPICAL APPLICATIO

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1 LTC88/LTC89/LTC9 -/-/-Bit SoftSpan DACs with Programmable Output Range FEATURES Six Programmable Output Ranges Unipolar Mode: V to, V to V Bipolar Mode: ±, ±V, ±.,. to. LSB Max DNL and INL Over the Industrial Temperature Range Glitch Impulse < nv-s -Lead SSOP Package Power-On Reset to V Asynchronous Clear to V for All Ranges APPLICATIO S U Process Control and Industrial Automation Precision Instrumentation Direct Digital Waveform Generation Software-Controlled Gain Adjustment Automatic Test Equipment DESCRIPTIO U The LTC 88/LTC89/LTC9 are serial input -/- /-bit multiplying current output DACs that operates from a single supply. These SoftSpan TM DACs can be software-programmed for either unipolar or bipolar mode through a -wire SPI interface. In either mode, the voltage output range can also be software-programmed. Two output ranges in unipolar mode and four output ranges in bipolar mode are available. INL and DNL are accurate to LSB over the industrial temperature range in both unipolar and bipolar modes. True -bit -quadrant multiplication is achieved with on-chip four quadrant multiplication resistors. The LTC88/LTC89/LTC9 are available in a -lead SSOP package. These devices include an internal deglitcher circuit that reduces the glitch impulse to less than nv-s (typ. The asynchronous clear pin resets the LTC88/LTC89/ LTC9 to V in unipolar or bipolar mode., LTC and LT are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO U Programmable Output Range -Bit SoftSpan DAC V REF 9.µF R R V CC CLR SDO / LT 9 R COM C pf R -BIT DAC WITH SPAN ADJUST LTC9 R REF R OFS R FB I OUT I OUT AGND GND 8 C pf / LT9.µF 8.µF V OUT INTEGRAL NONLINEARITY (LSB LTC9 Integral Nonlinearity V REF = ALL OUTPUT RANGES DIGITAL INPUT CODE 8899 TA 8899 TA 8899fa

2 LTC88/LTC89/LTC9 ABSOLUTE AXI U RATI GS W W W (Note V CC to AGND, GND....V to V AGND to GND....V to (V CC.V GND to AGND....V to (V CC.V R COM to AGND, GND....V to V REF to AGND, GND... ± R OFS, R FB, R, R to AGND, GND... ± Digital Inputs to AGND, GND....V to (V CC.V I OUT, I OUT to AGND, GND....V to (V CC.V Maximum Junction Temperature... C Operating Temperature Range LTC88C/LTC89C/LTC9C... C to C LTC88I/LTC89I/LTC9I... C to 8 C Storage Temperature Range... C to C Lead Temperature (Soldering, sec... C U U U W PACKAGE/ORDER I FOR ATIO R COM R R OFS R FB I OUT I OUT AGND GND 8 TOP VIEW G PACKAGE -LEAD PLASTIC SSOP T JMAX = C, θ JA = C/ W R REF CLR SDO 9 V CC ORDER PART NUMBER LTC88CG LTC88IG LTC89CG LTC89IG LTC9ACG LTC9AIG LTC9BCG LTC9BIG Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are T A = T MIN to T MAX, V CC =, V REF =, I OUT = AGND = GND = V. LTC88 LTC89 LTC9B LTC9A SYMBOL PARAMETER CONDITIONS TEMPERATURE MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Accuracy Resolution Bits INL Integral (Notes, T A = C ± ± ± ±. ± LSB Nonlinearity T MIN to T MAX ± ± ± ±. ± LSB DNL Differential Guaranteed T MIN to T MAX ± ± ± ±. ± LSB Nonlinearity Monotonic (Note GE Gain Error All Output Ranges T A = C. ±. ± ± ± LSB (Note T MIN to T MAX. ±. ± ± ± LSB BZE Bipolar Zero Error All Bipolar Ranges T A = C ± ±. ± ± LSB (Note T MIN to T MAX ± ±. ± ±8 LSB Gain Temperature Gain/ Temperature ppm/ C Coefficient (Note I LKG I OUT Leakage (Note T A = C ± ± ± ± na Current T MIN to T MAX ± ± ± ± na PSRR Power Supply V CC = ±% ±.±. ±. ±. ± ±. ± LSB/V Rejection 8899fa

3 LTC88/LTC89/LTC9 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are T A = T MIN to T MAX, V CC =, V REF =, I OUT = AGND = GND = V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input R REF DAC Input Resistance (Unipolar (Note kω R, R R, R Resistance (Notes, kω R OFS Offset Resistance (Bipolar ±, ±V, ±. Ranges kω. to. Range 8 kω R FB Feedback Resistance (Unipolar Range kω V Range kω Feedback Resistance (Bipolar ± and. to. Ranges kω ±V Range 8 kω ±. Range kω Analog Outputs (Note C OUT Output Capacitance (I OUT DAC Load All s pf DAC Load All s pf AC Performance (Note Settling Time Range, V to Step with LT8 (Note µs Midscale Glitch Impulse (Note nv-s Multiplying Feedthrough Error V REF = ±V, khz Sine Wave mv P-P THD Total Harmonic Distortion (Note 8 Multiplying 8 db Digital Inputs Output Noise Voltage Density (Note 9 At I OUT nv/ Hz V IH Digital Input High Voltage. V V IL Digital Input Low Voltage.8 V I IN Digital Input Current ± µa C IN Digital Input Capacitance V IN = V (Note 8 pf Digital Outputs V OH Digital Output High Voltage I OH = µa V V OL Digital Output Low Voltage I OL =.ma. V Timing Characteristics t Serial Input Valid to Setup Time ns t Serial Input Valid to Hold Time ns t Pulse Width High ns t Pulse Width Low ns t Pulse High Width ns t LSB High to High ns t Low to High ns t 8 to SDO Propagation Delay C LOAD = pf 8 ns t 9 Low to Low ns t Clear Pulse Low Width ns t High to Positive Edge ns Frequency Non-Daisy Chain (Note. MHz Daisy Chain (Note. MHz 8899fa

4 LTC88/LTC89/LTC9 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are T A = T MIN to T MAX, V CC =, V REF =, I OUT = AGND = GND = V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply V CC Supply Voltage.. V I CC Supply Current, V CC Digital Inputs = V or V CC µa Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : ±LSB = ±.% of full scale = ±.ppm of full scale (LTC9. ±LSB = ±.% of full scale = ±.ppm of full scale (LTC89. ±LSB =.% of full scale = ±.8ppm of full scale (LTC88. Note : Using internal feedback resistor. Note : Guaranteed by design, not subject to test. Note : I OUT with DAC register loaded to all s. Note : Typical temperature coefficient is ppm/ C. Note : To.% for a full-scale change, measured from the falling edge of LD for the LTC9 only. Note 8: REF = V RMS at khz. DAC register loaded with all s. Output amplifier = LT8. Note 9: Calculation from e n = ktrb where: k = Boltzmann constant (.8E- J/ K; R = resistance (Ω; T = temperature ( K; B = bandwidth (Hz. Note : Midscale transition code: to 8 for the LTC9, 89 to 89 for the LTC89, to 8 for the LTC88. Note : R and R are measured between R and R COM, R and R COM. Note : If a continuous clock is used with data changing on the rising edge of, setup and hold time (t, t will limit the maximum clock frequency. If data changes on the falling edge of then the setup time will limit the maximum clock frequency to 8MHz (continuous % duty cycle clock. Note : SDO propagation delay and setup time (t 8, t limit the maximum clock frequency for daisy chaining. TYPICAL PERFOR A CE CHARACTERISTICS UW (LTC88/LTC89/LTC9 OUTPUT VOLTAGE (mv Midscale Glitch Impulse USING AN LT8 C FEEDBACK = pf V REF = V nv-s TYPICAL SUPPLY CURRENT (ma Supply Current vs Input Voltage V CC = ALL DIGITAL INPUTS TIED TOGETHER LOGIC THRESHOLD (V Logic Threshold vs Supply Voltage TIME (µs INPUT VOLTAGE (V SUPPLY VOLTAGE (V 8899 G 8899 G G 8899fa

5 TYPICAL PERFOR A CE CHARACTERISTICS (LTC88 INTEGRAL NONLINEARITY (LSB UW Integral Nonlinearity Differential Nonlinearity DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY (LSB LTC88/LTC89/LTC DIGITAL INPUT CODE (LTC89 INTEGRAL NONLINEARITY (LSB Integral Nonlinearity 8899 G DIGITAL INPUT CODE 8899 G DIFFERENTIAL NONLINEARITY (LSB Differential Nonlinearity 8899 G DIGITAL INPUT CODE 8899 G (LTC9 Integral Nonlinearity (INL INTEGRAL NONLINEARITY (LSB DIGITAL INPUT CODE 8899 G DIFFERENTIAL NONLINEARITY (LSB Differential Nonlinearity (DNL DIGITAL INPUT CODE 8899 G INTEGRAL NONLINEARITY (LSB Integral Nonlinearity vs Reference Voltage in Unipolar Mode. 8 8 REFERENCE VOLTAGE (V 8899 G 8899fa

6 LTC88/LTC89/LTC9 TYPICAL PERFOR A CE CHARACTERISTICS UW (LTC9 INTEGRAL NONLINEARITY (LSB Integral Nonlinearity vs Reference Voltage in Bipolar Mode. 8 8 REFERENCE VOLTAGE (V 8899 G DIFFERENTIAL NONLINEARITY (LSB Differential Nonlinearity vs Reference Voltage in Unipolar Mode. 8 8 REFERENCE VOLTAGE (V 8899 G DIFFERENTIAL NONLINEARITY (LSB Differential Nonlinearity vs Reference Voltage in Bipolar Mode. 8 8 REFERENCE VOLTAGE (V LD PULSE /DIV GATED SETTLING WAVEFORM µv/div Full-Scale Settling Waveform ns/div USING LT8 OP AMP C FEEDBACK = pf V TO V STEP 9 G 8899 G8 PI FU CTIO S U U U R COM (Pin : Center Tap Point of the Two Bipolar Resistors R and R. Normally tied to the inverting input of an external amplifier. When these resistors are not used, connect this pin to ground. The absolute maximum voltage range on this pin is.v to V. R (Pin : Bipolar Resistor R. The main reference input V REF, typically. Accepts up to ±. Normally tied to R OFS (Pin and the reference input voltage V REF (. When not used connect this pin to ground. R OFS (Pin : Bipolar Offset Network. This pin provides the offset of the output voltage range for bipolar modes. Accepts up to ±. Normally tied to R and the reference input voltage V REF (. Alternatively, this pin may be driven from a different voltage than V REF. R FB (Pin : Feedback Network. Normally tied to the output of the current to voltage converter op amp. Range limited to ±. 8899fa

7 LTC88/LTC89/LTC9 PI FU CTIO S U U U I OUT (Pin : True DAC Current Output. Tied to the inverting input of the current-to-voltage op amp. I OUT (Pin : Complement of DAC Current Output. Normally tied to AGND pin. AGND (Pin : Analog Ground. Tie to the system s analog ground plane. GND (Pin 8: Ground. Tie to the system s analog ground plane. V CC (Pin 9: Positive Supply Input.. V CC.. Requires a.µf bypass capacitor to ground. SDO (Pin : Serial Data Output. Data at this pin is shifted out on the rising edge of. (Pin : Serial Data Input. (Pin : Serial Interface Clock. Data on the pin is shifted into the input shift register on rising edge of. (Pin : Chip Select Input. When is low, is enabled for shifting data into the input shift register. When is pulled high, is disabled and the control logic executes the control word (the first bits of the input data stream as shown in Table. CLR (Pin : When CLR is taken to a logic low, it sets the DAC output to V and all internal registers to zero code. REF (Pin : DAC Reference Input. Typically, accepts up to ±. R (Pin : Bipolar Resistor R. Normally tied to the DAC reference input REF (Pin and the output of the inverting amplifier tied to R COM (Pin. FU CTIO TABLE Table C U U COMMAND C C C OPERATION EACH COMMAND IS EXECUTED ON THE RISING EDGE OF Copy Data Word in SReg to Buf Copy the Data in Buf to Buf Copy Data Word in SReg to Buf and Buf Reserved (Do Not Use Reserved (Do Not Use Reserved (Do Not Use Reserved (Do Not Use Reserved (Do Not Use Set Range to. Copy in SReg to Buf and Buf Set Range to V. Copy in SReg to Buf and Buf Set Range to ±. Copy in SReg to Buf and Buf Set Range to ±V. Copy in SReg to Buf and Buf Set Range to ±.. Copy in SReg to Buf and Buf Set Range to. to V. Copy in SReg to Buf and Buf Reserved (Do Not Use No Operation SREG DATA WORD IN INPUT SHIFT REGISTER X X Internal Register Status BUF INPUT BUFFER No Change Data Word (n = to is the last bits shifted into the input shift register SReg that corresponds to the DAC code. BUF DAC BUFFER (DAC OUTPUT No Change No Change DAC OUTPUT RANGE No Change No Change No Change V ± ±V ±.. to. No Change 8899fa

8 LTC88/LTC89/LTC9 BLOCK DIAGRA W BUF BUF SREG -BIT SHIFT REGISTER -/-/-BIT DATA WORD BUFFER // BITS BUFFER // BITS -/-/-BIT DAC SPAN ADJUST BIT COMMAND WORD DECODER 8899 BD 8-BIT SHIFT REGISTER SDO U W W TI I G DIAGRA t t t t t t 9 t t t t 8 SDO 8899 TD fa

9 LTC88/LTC89/LTC9 OPERATIO U INPUT WORD (LTC88 C INPUT WORD (LTC89 C INPUT WORD (LTC9 COMMAND DON T CARE DATA ( BITS DON T-CARE BITS C C C X X X X D D D9 D8 D D D D D D D D X X X X MSB COMMAND DON T CARE DATA ( BITS DON T-CARE BITS C C C X X X X D D D D D9 D8 D D D D D D D D X X MSB COMMAND DON T CARE DATA ( BITS LSB LSB 8899 TD 8899 TD C C C C X X X X D D D D D D D9 D8 D D D D D D D D MSB LSB 8899 TD Serial Interface When the is brought to a logic low, the data on the input is loaded into the shift register on the rising edge of the clock. A -bit command word (C C C C, followed by four don t care bits and data bits (MSB-first is the minimum loading sequence required for the LTC88/LTC89/LTC9. When the is brought to a logic high, the clock is disabled internally and the command word is executed. If no daisy-chaining is required, the input stream can be -bit wide as shown in Figure a. The first four bits are the command word, followed by four don t care bits, then a -bit data word. The last four bits (LSBs of this -bit data word are don t cares for the LTC88. For the LTC89, the last bits of the -bit data word are don t cares. If daisy-chaining is required or the input needs to be written in two -bit wide segments, then the input stream must be -bit wide and the first 8 bits loaded are don t care bits. The remaining bits work the same as a -bit stream which is described in the previous paragraph. The output of the internal -bit shift register is available on the SDO pin clock cycles later. Multiple LTC88/LTC89/LTC9s may be daisychained together by connecting the SDO pin to the pin of the next IC. The clock and signals should remain common to all ICs in the daisy-chain. The serial data is clocked to all ICs, then the signal is pulled high to update all of them simultaneously. Power-On Reset and Clear When the power supply is first turned on, the LTC88/ LTC89/LTC9 will power up in unipolar mode (C C C C =. All the internal registers are set to zeros and the DAC is set to zero code. The LTC88/LTC89/LTC9 must first be programmed in either unipolar or bipolar mode. There are six operating modes available and can be software-programmed by the command word. When a CLR signal is brought to low, it clears all internal registers to zero. The DAC output voltage goes to zero volts. If an update DAC command (C C C C = is issued immediately after the CLR signal, the DAC output remains at zero volts. If a CLR signal is given within a ns interval immediately after goes high, the user should reload the output range. Output Range Programming There are two output ranges available in unipolar mode and four output ranges available in bipolar mode. See Function Table for details. All output ranges are with respect to a reference input. When changing the LTC88/ LTC89/LTC9 to a new mode, the command word and data are given at the same time ( or bit. When 8899fa 9

10 OPERATIO U LTC88/LTC89/LTC9 SDO -BIT DATA STREAM (CANNOT BE DAISY-CHAINED C C C C X X X X D D D D D D D9 D8 D D D D D D D D 8899 Fa CONTROL WORD DON T CARE (RESERVED DATA WORD Figure a. LTC9 -Bit Load Sequence (Minimum Input Word LTC89 Data Word = -Bit Input Code Don t Care Bits at LSB Positions LTC88 Data Word = -Bit Input Code Don t Care Bits at LSB Positions -BIT DATA STREAM (CAN BE DAISY-CHAINED X X X X X X X C C C C X X X X D D D D D D D9 D8 D D D D D D D D X DON T CARE CONTROL WORD DON T CARE DATA WORD X X X X X X X C C C C X X X X D D D D D D D9 D8 D D D D D D D D X PREVIOUS -BIT INPUT WORD t D t t t D 8 SDO PREVIOUS D PREVIOUS D t8 Figure b. LTC9 -Bit Load Sequence (Required for Daisy-Chain Operation LTC89 /SDO Data Word = -Bit Input Code Don t Care Bits at LSB Positions LTC88 /SDO Data Word = -Bit Input Code Don t Care Bits at LSB Positions CURRENT -BIT INPUT WORD 8899 Fb 8899fa

11 OPERATIO U LTC88/LTC89/LTC9 goes high, the mode changes and the DAC output goes to a value corresponding to the data code. Examples using the LTC9:. Using a -bit loading sequence, load the unipolar range of V to V with the DAC output at zero volt: a b Clock = XXXX c ; then V OUT = V. Using a -bit loading sequence, load the bipolar range of ± and the DAC output at zero volt: a b Clock = XXXX c ; then V OUT = V on the ± range. Using a -bit load sequence, load the bipolar range of ±V with the DAC output voltage at initially. Then change the DAC output to : a b Clock = XXXX XXXX XXXX c ; then V OUT = on the ±V range Next, the bipolar range of ±V is retained and the DAC output voltage is changed to V OUT = : a b Clock = XXXX XXXX XXXX c ; then V OUT = on the ±V range APPLICATIO S I FOR ATIO Op Amp Selection U W U U Because of the extremely high accuracy of the -bit LTC9, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables and contain equations for evaluating the effects of op amp parameters on the LTC9 s accuracy when programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Tables and can also be used to determine the effects of op amp parameters on the LTC89 and the LTC88. However, the results obtained from Tables and are in -bit LSBs. Divide these results by (LTC89 and (LTC88 to obtain the correct LSB sizing. Table contains a partial list of LTC precision op amps recommended for use with the LTC9. The easy-to-use design equations simplify the selection of op amps to meet the system s specified error budget. Select the amplifier from Table and insert the specified op amp parameters in Table. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the LTC9. Arithmetic summation gives an (unlikely worstcase effect. A root-sum-square (RMS summation produces a more realistic estimate. Op amp offset will contribute mostly to output offset and gain error and has minimal effect on INL and DNL. For the LTC9, a µv op amp offset will cause about.lsb INL degradation and.lsb DNL degradation with a V full-scale range (V range in bipolar. For the LTC9 programmed in a unipolar mode, the same µv op amp offset will cause a.lsb zero-scale error and a.lsb gain error with a V full-scale range. 8899fa

12 LTC88/LTC89/LTC9 APPLICATIO S I FOR ATIO U W U U While not directly addressed by the simple equations in Tables and, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp s data sheet to find the worst-case V OS and I B over temperature. Then, plug these numbers in the V OS and I B equations from Table and calculate the temperature induced effects. For applications where fast settling time is important, Application Note, entitled Component and Measurement Table. Variables for Each Output Range That Adjust the Equations in Table OUTPUT RANGE A A A A A. V.. ±.. ±V.. ±... to..9.. Advances Ensure -Bit DAC Settling Time, offers a thorough discussion of -bit DAC settling time and op amp selection. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC9 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC9 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for -bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference Table. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges OP AMP V OS (mv I B (na A VOL (V/V V OS (mv I B (mv A VOL (V/V INL (LSB V OS. I B..k ( A A VOL DNL (LSB V OS. I B.8.k ( A A VOL UNIPOLAR OFFSET (LSB V OS. I B. ( ( ( V REF ( A k ( Table. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC88/LTC89/LTC9, with Relevant Specifications AMPLIFIER SPECIFICATIONS VOLTAGE CURRENT SLEW GAIN BANDWIDTH t SETTLING POWER V OS I B A OL NOISE NOISE RATE PRODUCT with LTC9 DISSIPATION AMPLIFIER µv na V/mV nv/ Hz pa/ Hz V/µs MHz µs mw LT LT V REF BIPOLAR ZERO ERROR (LSB A V OS 9.8 I B. ( LT (Dual..8.../Op Amp LT (Dual /Op Amp LT8. 9. LT9 (Dual. 9. /Op Amp A V OS. A I B. A VOL V REF UNIPOLAR GAIN ERROR (LSB V OS. I B.8 A ( V V OS. REF ( V I B.8 REF k k ( A VOL A ( k ( V OS. I B. A VOL BIPOLAR GAIN ERROR (LSB A VOL V OS. V REF I B. k ( A VOL ( 8899fa

13 LTC88/LTC89/LTC9 APPLICATIO S I FOR ATIO U W U U with low output voltage initial tolerance, like the LT (±.%, minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit s INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to -bit and higher performance, reference output voltage noise may contribute a dominant share of the system s noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT, produce low output noise in the.hz to Hz region, well below the -bit LSB level in or V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Table. Partial List of LTC Precision References Recommended for Use with the LTC88/LTC89/LTC9 with Relevant Specifications INITIAL TEMPERATURE.Hz to Hz REFERENCE TOLERANCE DRIFT NOISE LT9A-, ±.% ppm/ C µv P-P LT9A- LTA-, ±.% ppm/ C µv P-P LTA- LTA-, ±.% ppm/ C µv P-P LTA- LT9A-. ±.% ppm/ C µv P-P Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding techniques should be used. I OUT must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to I OUT, a low resistance trace should be used to route this pin to star ground. This minimizes the voltage drop from this pin to ground caused by the code dependent current flowing to ground. When the resistance of this circuit board trace becomes greater than Ω, a force/sense amplified configuration should be used to drive this pin (see Figure. This preserves the excellent accuracy (LSB INL and DNL of the LTC88/LTC89/LTC9. An Isolated -Bit Subsystem Using the LTC9 The circuit in Figure is a complete example of an optically isolated analog output subsystem that supports most of the legacy ranges that are still common in industrial environments. This circuit uses only two optoisolators, the load pulse ( being derived from a series of transitions on the data line ( after the clock ( is halted high. If a single chip microcontroller with an automated SPI interface is to be used, the SPI port can transfer the bits as three bytes. Subsequently, the data output port pin can be reassigned to general purpose port operation and exercised to produce a number of transitions to generate the load pulse. Alternatively, the entire sequence can be programmed bit by bit with a general purpose port. Figure shows the timing. The DC/DC converter, Figure based on the LT 9 ultralow noise transformer driver provides a compact means of powering this circuit, and allows the output to deliver output current that is only limited by the LT8 capabilities. The output capability of the DC/DC converter itself is 8mA at ±V and is available as demo board DCA. This circuit as shown requires approximately ma of the supply (no load. The total surface area required is less than square inches. 8899fa

14 LTC88/LTC89/LTC9 APPLICATIO S I FOR ATIO U W U U ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE I OUT ZETEX BATS LT8 Ω Ω pf I OUT LT V REF / LT9 C** pf ZETEX* BATS *SCHOTTKY BARRIER DIODE 9.µF R R V CC R COM R R REF R OFS R FB I OUT C pf.µf 8 CLR SDO -/-/-BIT DAC WITH SPAN ADJUST LTC88/LTC89/LTC9 I OUT AGND GND 8 / LT9.µF V OUT 8899 F **FOR MULTIPLYING APPLICATIONS C = pf Figure. Basic Connections for SoftSpan V OUT DAC with Two Optional Circuits for Driving I OUT from AGND with a Force/Sense Amplifier E V IN ±% E SHDN E SYNC E GND V IN C.µF.V R9 k C 8pF R M R.9k SHDN SYNC V IN LT9 COLA CT COLB RT RSL GND PGND PGND T CTX- R k D MMBD9 D MMBD9 D MMBD9 D MMBD9 R k LT- C µf CER C µf CER.µF BYP LT IN OUT GND ADJ GND ADJ LT9 IN OUT BYP R k R 9.9k R 9.9k R k C.µF C8.µF C µf TANT C µf TANT 8899 F V AGND V C.nF kv Figure. Isolated Power Supplies for the Circuit of Figure 8899fa

15 PACKAGE DESCRIPTIO U G Package -Lead Plastic SSOP (.mm (Reference LTC DWG # -8- LTC88/LTC89/LTC9. ±..9.* ( (.9.. ±.. BSC RECOMMENDED SOLDER PAD LAYOUT..** ( ( (....9 (.. NOTE:. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS. DIMENSIONS ARE IN (INCHES. DRAWING NOT TO SCALE * DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.mm (." PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.mm (." PER SIDE. (. BSC..8 (.9.. (. G SSOP 8 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 8899fa

16 LTC88/LTC89/LTC9 APPLICATIO S I FOR ATIO U W U U TO µcontroller V CC V CC R.k R.k HCPL HCPL 8 8 OPTIONAL CIRCUIT FOR -WIRE INTERFACE. FOR A -WIRE INTERFACE (SPI, ADD A RD OPTOISOLATOR TO DRIVE WITH THE WAVEFORMS OF FIGURE GND 9 HC A B C D CLK ENP ENT LD QA QB QC QD CLR RCO ISOLATED ISOLATED ISOLATED.µF 9 R R V CC CLR SDO R COM V LT8 V.µF pf R µf.µf µf R -/-/-BIT DAC WITH SPAN ADJUST LTC88/LTC89/LTC9 REF REF R OFS R FB µf I OUT I OUT AGND GND V 8 LT- 8 pf V LT8 V µf.µf AGND V OUT µf 8899 F.µF AGND Figure. Optically Isolated -Bit SoftSpan System C C C C X D D D 8899 F Figure. Timing Diagram for the Circuit of Figure RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC9/LTC9 Parallel -/-Bit Current Output DACs On-Chip -Quadrant Resistors LTC9/LTC9 Serial -Bit Current Output DACs Low Glitch, ±LSB Maximum INL, DNL LTC99 -Byte, -Bit Current Output DAC On-Chip -Quadrant Resistors LTC8 Parallel -Bit Voltage Outupt DAC Precision -Bit Settling in µs for V Step LTC/LTC Octal -/-/-Bit DACs Single Supply, µpower in Narrow SSOP LTC Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- (8-9 FAX: ( fa LT/TP K REV A PRINTED IN USA LINEAR TECHNOLOGY CORPORATION