TYPICAL APPLICATION LTC1591/LTC1591-1

Transcription

1 FEATURES True -Bit Performance Over Industrial Temperature Range DNL and INL: LSB Max On-Chip 4-Quadrant Resistors Allow Precise V to V, V to V or ±V Outputs Pin Compatible 4- and -Bit Parts Asynchronous Clear Pin LTC59/LTC59: Reset to Zero Scale LTC59-/LTC59-: Reset to Midscale Glitch Impulse < 2nV-s 28-Lead SSOP Package Low Power Consumption: µw Typ Power-On Reset APPLICATIONS U Process Control and Industrial Automation Direct Digital Waveform Generation Software-Controlled Gain Adjustment Automatic Test Equipment LTC59/LTC59 4-Bit and -Bit Parallel Low Glitch Multiplying DACs with 4-Quadrant Resistors DESCRIPTION U The LTC 59/LTC59 are pin compatible, parallel input 4-bit and -bit multiplying current output DACs that operate from a single 5V supply. INL and DNL are accurate to LSB over the industrial temperature range in both 2- and 4- quadrant multiplying modes. True -bit 4-quadrant multiplication is achieved with on-chip 4-quadrant multiplication resistors. These DACs include an internal deglitcher circuit that reduces the glitch impulse to less than 2nV-s (typ). The asynchronous pin resets the LTC59/LTC59 to zero scale and LTC59-/LTC59- to midscale. The LTC59/LTC59 are available in 28-pin SSOP and PDIP packages and are specified over the industrial temperature range. For serial interface -bit current output DACs refer to the LTC595/LTC59 data sheet., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION DATA INPUTS TO 2, 24 TO 2 U -Bit, 4-Quadrant Multiplying DAC with a Minimum of External Components R R COM REF V CC R LT 48 R2 LTC59-5pF 5V.µF -BIT DAC I OUT AGND 5pF LT48 V OUT = TO 59/9 TA LTC59/LTC59- Integral Nonlinearity LTC59/LTC59- Integral Nonlinearity = V V OUT = ±V BIPOLAR DIGITAL INPUT CODE = V V OUT = ±V BIPOLAR 59/9 TA DIGITAL INPUT CODE 59/9 TA3

2 LTC59/LTC59 ABSOLUTE MAXIMUM RATINGS W W W V CC to AGND....5V to V V CC to....5v to V AGND to... V CC.5V to AGND... V CC.5V REF,,, R, R COM to AGND,... ±25V Digital Inputs to....5v to (V CC.5V) I OUT to AGND....5V to( V CC.5V) Maximum Junction Temperature C U (Note ) Operating Temperature Range LTC59C/LTC59-C LTC59C/LTC59-C... C to C LTC59I/LTC59-I LTC59I/LTC59-I... 4 C to 85 C Storage Temperature Range... 5 C to 5 C Lead Temperature (Soldering, sec)... 3 C PACKAGE/ORDER INFORMATION REF R COM 2 R I OUT AGND 8 9 D3 D2 D 2 D 3 D9 4 G PACKAGE 28-LEAD PLASTIC SSOP TOP VIEW 28 2 NC 2 NC 25 D 24 D V CC 2 D2 2 D3 9 D4 8 D5 D D 5 D8 N PACKAGE 28-LEAD NARROW PDIP T JMAX = 25 C, θ JA = 95 C/ W (G) T JMAX = 25 C, θ JA = C/ W (N) Consult factory for Military grade parts. U W U ORDER PART NUMBER LTC59CG LTC59CN LTC59IG LTC59IN LTC59-CG LTC59-CN LTC59-IG LTC59-IN REF R COM 2 R I OUT AGND 8 9 D5 D4 D3 2 D2 3 D 4 G PACKAGE 28-LEAD PLASTIC SSOP TOP VIEW 28 2 D 2 D 25 D2 24 D3 V CC 2 D4 2 D5 9 D 8 D D8 D9 5 D N PACKAGE 28-LEAD NARROW PDIP T JMAX = 25 C, θ JA = 95 C/ W (G) T JMAX = 25 C, θ JA = C/ W (N) ORDER PART NUMBER LTC59ACG LTC59ACN LTC59BCG LTC59BCN LTC59-ACG LTC59-ACN LTC59-BCG LTC59-BCN LTC59AIG LTC59AIN LTC59BIG LTC59BIN LTC59-AIG LTC59-AIN LTC59-BIG LTC59-BIN 2

3 ELECTRICAL CHARACTERISTICS V CC = 5V ±%, = V, I OUT = AGND = = V, T A = T MIN to T MAX, unless otherwise noted. LTC59/LTC59 LTC59/- LTC59B/-B LTC59A/-A SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Accuracy Resolution 4 Bits Monotonicity 4 Bits INL Integral Nonlinearity (Note 2) T A = 25 C ± ± 2 ±.25 ± LSB T MIN to T MAX ± ±2 ±.35 ± LSB DNL Differential Nonlinearity T A = 25 C ± ± ±.2 ± LSB T MIN to T MAX ± ± ±.2 ± LSB GE Gain Error Unipolar Mode (Note 3) T A = 25 C ±4 ± 2 ± LSB T MIN to T MAX ± ±24 3 ± LSB Bipolar Mode (Note 3) T A = 25 C ±4 ± 2 ± LSB T MIN to T MAX ± ± 24 3 ± LSB Gain Temperature Coefficient (Note 4) Gain/ Temperature ppm/ C Bipolar Zero-Scale Error T A = 25 C ± 3 ± ± 5 LSB T MIN to T MAX ± 5 ± ± 8 LSB I LKG OUT Leakage Current (Note 5) T A = 25 C ±5 ±5 ±5 na T MIN to T MAX ±5 ±5 ±5 na PSRR Power Supply Rejection Ratio V CC = 5V ± ±. ± ±.4 ±2 ±.4 ±2 LSB/V V CC = 5V ±%, = V, I OUT = AGND = = V, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input R REF DAC Input Resistance (Unipolar) (Note ) 4.5 kω R/R2 R/R2 Resistance (Bipolar) (Notes, 3) kω, Feedback and Offset Resistances (Note ) kω AC Performance (Note 4) Output Current Settling Time (Notes, 8) µs Midscale Glitch Impulse (Note 2) 2 nv-s Digital-to-Analog Glitch Impulse (Note 9) nv-s Multiplying Feedthrough Error = ±V, khz Sine Wave mv P-P THD Total Harmonic Distortion (Note ) 8 db Output Noise Voltage Density (Note ) nv/ Hz Harmonic Distortion Unipolar Mode (Note 4) (Digital Waveform Generation) 2nd Harmonic 94 db 3rd Harmonic db SFDR 94 db Bipolar Mode (Note 4) 2nd Harmonic 94 db 3rd Harmonic db SFDR 94 db 3

4 LTC59/LTC59 ELECTRICAL CHARACTERISTICS V CC = 5V ±%, = V, I OUT = AGND = = V, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Outputs (Note 4) C OUT Output Capacitance (Note 4) DAC Register Loaded to All s: C OUT 5 3 pf DAC Register Loaded to All s: C OUT 8 pf Digital Inputs V IH Digital Input High Voltage 2.4 V V IL Digital Input Low Voltage.8 V I IN Digital Input Current. ± µa C IN Digital Input Capacitance (Note 4) V IN = V 8 pf Timing Characteristics t DS Data to Setup Time 2 ns t DH Data to Hold Time 2 ns t Pulse Width 25 ns t Pulse Width 55 ns t Clear Pulse Width 4 ns t LWD to Delay Time ns Power Supply V DD Supply Voltage V I DD Supply Current Digital Inputs = V or V CC µa The denotes specifications that apply over the full operating temperature range. Note : Absolute Maximum Values are those beyond which the life of a device may be impaired. Note 2: ±LSB = ±.% of full scale = ±ppm of full scale for the LTC59/LTC59-. ±LSB = ±.5% of full scale = ±5.3ppm of full scale for the LTC59/LTC59-. Note 3: Using internal feedback resistor. Note 4: Guaranteed by design, not subject to test. Note 5: I (OUT) with DAC register loaded to all s. Note : Typical temperature coefficient is ppm/ C. Note : I OUT load = Ω in parallel with 3pF. Note 8: To.% for a full-scale change, measured from the rising edge of for the LTC59/LTC59-. To.5% for a full-scale change, measured from the rising edge of for the LTC59/LTC59-. Note 9: = V. DAC register contents changed from all s to all s or all s to all s. Note : = V RMS at khz. DAC register loaded with all s. Note : Calculation from e n = 4kTRB where: k = Boltzmann constant (J/ K), R = resistance (Ω), T = temperature ( K), B = bandwidth (Hz). Note 2: Midscale transition code: to for the LTC59/LTC59- and to for the LTC59/LTC59-. Note 3: R and R2 are measured between R and R COM, REF and R COM. Note 4: Measured using the LT48 op amp in unipolar mode for I/V converter and LT48 I/V and LT reference inverter in bipolar mode. Sample Rate = 5kHz, Signal Frequency = khz, = 5V, T A = 25 C. 4

5 LTC59/LTC59 TYPICAL PERFOR A CE CHARACTERISTICS UW (LTC59/LTC59) OUTPUT VOLTAGE (mv) Midscale Glitch Impulse 4 USING AN LT48 3 C FEEDBACK = 3pF = V nv-s TYPICAL TIME (µs) 59/9 G PULSE 5V/DIV GATED SETTLING WAVEFORM 5µV/DIV Full-Scale Settling Waveform USING LT48 OP AMP C FEEDBACK = 2pF V to V STEP 5ns/DIV 59/9 G2 SIGNAL/(NOISE DISTORTION) (db) Unipolar Multiplying Mode Signal-to-(Noise Distortion) vs Frequency V CC = 5V USING AN LT48 C FEEDBACK = 3pF REFERENCE = V RMS 8kHz FILTER 5kHz FILTER 3kHz FILTER k k k FREQUENCY (Hz) 59/9 G3 SIGNAL/(NOISE DISTORTION) (db) Bipolar Multiplying Mode Signal-to-(Noise Distortion) vs Frequency, Code = All Zeros V CC = 5V USING TWO LT48s C FEEDBACK = 5pF REFERENCE = V RMS 5kHz FILTER 8kHz FILTER 3kHz FILTER k k k FREQUENCY (Hz) 59/9 G4 SIGNAL/(NOISE DISTORTION) (db) Bipolar Multiplying Mode Signal-to-(Noise Distortion) vs Frequency, Code = All Ones V CC = 5V USING TWO LT48s C FEEDBACK = 5pF REFERENCE = V RMS 5kHz FILTER 8kHz FILTER 3kHz FILTER k k k FREQUENCY (Hz) 59/9 G5 SUPPLY CURRENT (ma) Supply Current vs Input Voltage V CC = 5V ALL DIGITAL INPUTS TIED TOGETHER LOGIC THRESHO (V) Logic Threshold vs Supply Voltage INTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) 59/9 G 59/9 G 5

6 LTC59/LTC59 TYPICAL PERFOR A CE CHARACTERISTICS UW (LTC59) Integral Nonlinearity (INL) DIGITAL INPUT CODE Integral Nonlinearity vs Reference Voltage in Bipolar Mode 59 G REFERENCE VOLTAGE (V) G4 Integral Nonlinearity vs Supply Voltage in Unipolar Mode = V = V SUPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity (DNL) DIGITAL INPUT CODE Differential Nonlinearity vs Reference Voltage in Unipolar Mode 59 G REFERENCE VOLTAGE (V) Integral Nonlinearity vs Supply Voltage in Bipolar Mode = V = V 59 G SUPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) Integral Nonlinearity vs Reference Voltage in Unipolar Mode REFERENCE VOLTAGE (V) Differential Nonlinearity vs Reference Voltage in Bipolar Mode 59 G REFERENCE VOLTAGE (V) G Differential Nonlinearity vs Supply Voltage in Unipolar Mode = V = V SUPPLY VOLTAGE (V) 59 G 59 G8 59 G9

7 LTC59/LTC59 TYPICAL PERFOR A CE CHARACTERISTICS UW (LTC59) DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity vs Supply Voltage in Bipolar Mode = V = V SUPPLY VOLTAGE (V) 59 G ATTENUATION (db) Unipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS ON D3 ON D2 ON 2 D ON D ON D9 ON 4 D8 ON D ON D ON D5 ON D4 ON D3 ON D2 ON 8 D ON D ON ALL BITS OFF 2 k k k M M FREQUENCY (Hz) 59G LTC59 3pF LT48 V OUT ATTENUATION (db) Bipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS ON D3 AND D2 ON D3 AND D ON 2 D3 AND D ON D3 AND D9 ON D3 AND D8 ON 4 D3 AND D ON D3 AND D ON D3 AND D5 ON D3 AND D4 ON D3 AND D3 ON D3 AND D2 ON D3 AND D ON 8 D3 AND D ON D3 ON* CODES FROM MIDSCALE TO FULL SCALE k k k M M FREQUENCY (Hz) 59 G2 *DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO 84dB TYPICAL (db MAX) ATTENUATION (db) Bipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS OFF D2 ON D2 AND D ON 2 D2 TO D ON D2 TO D9 ON D2 TO D8 ON 4 D2 TO D ON D2 TO D ON D2 TO D5 ON D2 TO D4 ON D2 TO D3 ON D2 TO D2 ON D2 TO D ON 8 D2 TO D ON D3 ON* CODES FROM MIDSCALE TO ZERO SCALE k k k M M FREQUENCY (Hz) 59G3 *DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO 84dB TYPICAL (db MAX) LT48 2pF 2pF LTC59 5 5pF LT48 V OUT LT48 2pF 2pF LTC59 5 5pF LT48 V OUT

8 LTC59/LTC59 TYPICAL PERFOR A CE CHARACTERISTICS UW (LTC59) Integral Nonlinearity (INL) DIGITAL INPUT CODE Integral Nonlinearity vs Reference Voltage in Bipolar Mode REFERENCE VOLTAGE (V) 59 G G4 Integral Nonlinearity vs Supply Voltage in Unipolar Mode = V = V SUPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity (DNL) DIGITAL INPUT CODE Differential Nonlinearity vs Reference Voltage in Unipolar Mode REFERENCE VOLTAGE (V) 59 G Integral Nonlinearity vs Supply Voltage in Bipolar Mode = V = V 59 G SUPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) Integral Nonlinearity vs Reference Voltage in Unipolar Mode REFERENCE VOLTAGE (V) Differential Nonlinearity vs Reference Voltage in Bipolar Mode REFERENCE VOLTAGE (V) 59 G G Differential Nonlinearity vs Supply Voltage in Unipolar Mode = V.2.2 = V SUPPLY VOLTAGE (V) 8 59 G 59 G8 59 G9

9 LTC59/LTC59 TYPICAL PERFOR A CE CHARACTERISTICS UW (LTC59) DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity vs Supply Voltage in Bipolar Mode = V = V SUPPLY VOLTAGE (V) 59 G ATTENUATION (db) Unipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS ON D5 ON D4 ON D3 ON D2 ON D ON D ON D9 ON D8 ON D ON D ON D5 ON D4 ON D3 ON D2 ON D ON D ON ALL BITS OFF 2 k k k M M FREQUENCY (Hz) 59G LTC59 3pF LT48 V OUT ATTENUATION (db) ALL BITS ON D5 AND D4 ON D5 AND D3 ON D5 AND D2 ON D5 AND D ON D5 AND D ON D5 AND D9 ON D5 AND D8 ON D5 AND D ON D5 AND D ON D5 AND D5 ON D5 AND D4 ON D5 AND D3 ON D5 AND D2 ON D5 AND D ON D5 AND D ON D5 ON* k k k M M FREQUENCY (Hz) 59 G2 *DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO 9dB TYPICAL (8dB MAX, A GRADE) Bipolar Multiplying Mode Frequency Response vs Digital Code CODES FROM MIDSCALE TO FULL SCALE ATTENUATION (db) Bipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS OFF D4 ON D4 AND D3 ON D4 TO D2 ON D4 TO D ON D4 TO D ON D4 TO D9 ON D4 TO D8 ON D4 TO D ON D4 TO D ON D4 TO D5 ON D4 TO D4 ON D4 TO D3 ON D4 TO D2 ON D4 TO D ON 59 G3 *DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO 9dB TYPICAL (8dB MAX, A GRADE) CODES FROM MIDSCALE TO ZERO SCALE D4 TO D ON D5 ON* k k k M M FREQUENCY (Hz) 2pF LT48 2pF V OUT 2pF LT48 2pF V OUT LTC59 5 5pF LT LTC59 5 5pF LT48 9

10 LTC59/LTC59 PIN FUNCTIONS U U U LTC59 REF (Pin ): Reference Input and 4-Quadrant Resistor R2. Typically ±V, accepts up to ±25V. In 2-Quadrant mode this is the reference input. In 4-quadrant mode, this pin is driven by external inverting reference amplifier. R COM (Pin 2): Center Tap Point of the Two 4-Quadrant Resistors R and R2. Normally tied to the inverting input of an external amplifier in 4-quadrant operation, otherwise shorted to the REF pin. See Figures a and 2a. R (Pin 3): 4-Quadrant Resistor R. In 2-quadrant operation short to the REF pin. In 4-quadrant mode tie to (Pin 4). (Pin 4): Bipolar Offset Resistor. Typically swings ±V, accepts up to ±25V. In 2-quadrant operation tie to. In 4-quadrant operation tie to R. (Pin 5): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. Swings to ±. is typically ±V. LTC59 REF (Pin ): Reference Input and 4-Quadrant Resistor R2. Typically ±V, accepts up to ±25V. In 2-Quadrant mode this is the reference input. In 4-quadrant mode, this pin is driven by external inverting reference amplifier. R COM (Pin 2): Center Tap Point of the Two 4-Quadrant Resistors R and R2. Normally tied to the inverting input of an external amplifier in 4-quadrant operation, otherwise shorted to the REF pin. See Figures b and 2b. R (Pin 3): 4-Quadrant Resistor R. In 2-quadrant operation short to the REF pin. In 4-quadrant mode tie to (Pin 4). (Pin 4): Bipolar Offset Resistor. Typically swings ±V, accepts up to ±25V. In 2-quadrant operation tie to. In 4-quadrant operation tie to R. (Pin 5): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. Swings to ±. is typically ±V. I OUT (Pin ): DAC Current Output. Tie to the inverting input of the current to voltage converter op amp. AGND (Pin ): Analog Ground. Tie to ground. (Pin 8): DAC Digital Input Load Control Input. When is taken to a logic high, data is loaded from the input register into the DAC register, updating the DAC output. (Pin 9):DAC Digital Write Control Input. When is taken to a logic low, data is loaded from the digital input pins into the 4-bit wide input register. DB3 to D2 (Pins to 2): Digital Input Data Bits. (Pin ): Digital Ground. Tie to ground. V CC (Pin ): The Positive Supply Input. 4.5V V CC 5.5V. Requires a bypass capacitor to ground. DB, DB (Pins 24, 25): Digital Input Data Bits. NC (Pins 2, 2): No Connect. (Pin 28):Digital Clear Control Function for the DAC. When is taken to a logic low, it sets the DAC output and all internal registers to zero code for the LTC59 and midscale code for the LTC59-. I OUT (Pin ): DAC Current Output. Tie to the inverting input of the current to voltage converter op amp. AGND (Pin ): Analog Ground. Tie to ground. (Pin 8): DAC Digital Input Load Control Input. When is taken to a logic high, data is loaded from the input register into the DAC register, updating the DAC output. (Pin 9):DAC Digital Write Control Input. When is taken to a logic low, data is loaded from the digital input pins into the -bit wide input register. DB5 to D4 (Pins to 2): Digital Input Data Bits. (Pin ): Digital Ground. Tie to ground. V CC (Pin ): The Positive Supply Input. 4.5V V CC 5.5V. Requires a bypass capacitor to ground. DB3 to DB (Pins 24 to 2): Digital Input Data Bits. (Pin 28):Digital Clear Control Function for the DAC. When is taken to a logic low, it sets the DAC output and all internal registers to zero code for the LTC59 and midscale code for the LTC59-.

11 TRUTH TABLE Table LTC59/LTC59 CONTROL INPUTS REGISTER OPERATION X X Reset Input and DAC Register to All s for LTC59/LTC59 and Midscale for LTC59-/LTC59- (Asynchronous Operation) Load Input Register with All 4/ Data Bits Load DAC Register with the Contents of the Input Register Input and DAC Register Are Transparent CLK = and Tied Together. The 4/ Data Bits Are Loaded into the Input Register on the Falling Edge of the CLK and Then Loaded into the DAC Register on the Rising Edge of the CLK No Register Operation BLOCK DIAGRA SM W LTC59 REF 48k 48k 5 R COM 2 2k 48k 48k 48k 48k 48k 48k 48k 9k 9k 9k 9k 2k 2k 4 2k R 3 I OUT V CC AGND DECODER 8 LOAD D3 (MSB) D2 D D D9 D (LSB) DAC REGISTER RST 28 9 INPUT REGISTER RST 59 BD D3 D2 2 D2 24 D 25 D 2 NC 2 NC

12 LTC59/LTC59 BLOCK DIAGRA SM W LTC59 REF 48k 48k 5 R COM 2 2k 48k 48k 48k 48k 48k 48k 48k 9k 9k 9k 9k 2k 2k 4 2k R 3 I OUT V CC AGND DECODER 8 LOAD D5 (MSB) D4 D3 D2 D D (LSB) RST DAC REGISTER 28 9 INPUT REGISTER RST 59 BD D5 D4 2 D4 24 D3 25 D2 2 D 2 D U W W TI I G DIAGRA t DATA t DS t DH tlwd t t 59/9TD 2

13 LTC59/LTC59 APPLICATIONS INFORMATION U W U U Description The LTC59/LTC59 are 4-/-bit multiplying, current output DACs with a full parallel 4-/-bit digital interface. The devices operate from a single 5V supply and provide both unipolar V to V or V to V and bipolar ±V output ranges from a V or V reference input. They have three additional precision resistors on chip for bipolar operation. Refer to the block diagrams regarding the following description. The 4-/-bit DACs consist of a precision R-2R ladder for the /3LSBs. The 3MSBs are decoded into seven segments of resistor value R. Each of these segments and the R-2R ladder carries an equally weighted current of one eighth of full scale. The feedback resistor and 4-quadrant resistor have a value of R/4. 4-quadrant resistors R and R2 have a magnitude of R/4. R and R2 together with an external op amp (see Figure 2) inverts the reference input voltage and applies it to the 4-/-bit DAC input REF, in 4-quadrant operation. The REF pin presents a constant input impedance of R/8 in unipolar mode and R/2 in bipolar mode. The output impedance of the current output pin I OUT varies with DAC input code. The I OUT capacitance due to the NMOS current steering switches also varies with input code from pf to 5pF. An added feature of these devices, especially for waveform generation, is a proprietary deglitcher that reduces glitch energy to below 2nV-s over the DAC output voltage range. 5V Digital Section The LTC59/LTC59 are 4-/-bit wide full parallel data bus inputs. The devices are double-buffered with two 4-/-bit registers. The double-buffered feature permits the update of several DACs simultaneously. The input register is loaded directly from a -bit microprocessor bus when the pin is brought to a logic low level. The second register (DAC register) is updated with the data from the input register when the pin is brought to a logic high level. Updating the DAC register updates the DAC output with the new data. To make both registers transparent for flowthrough mode, tie low and high. However, this defeats the deglitcher operation and output glitch impulse may increase. The deglitcher is activated on the rising edge of the pin. The versatility of the interface also allows the use of the input and DAC registers in a master slave or edge-triggered configuration. This mode of operation occurs when and are tied together. The asynchronous clear pin resets the LTC59/LTC59 to zero scale and the LTC59-/ LTC59- to midscale. resets both the input and DAC registers. These devices also have a power-on reset. Table shows the truth table for the LTC59/LT59. Unipolar Mode (2-Quadrant Multiplying, V OUT = V to ) The LTC59/LTC59 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in Figure. With a fixed V reference, the circuits shown give a precision unipolar V to V output swing. 4 DATA INPUTS TO 2, 24, R R COM REF R R2 LTC59.µF V CC NC NC BIT DAC I OUT AGND 33pF LT V OUT = V TO Unipolar Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT VOUT (,383/,384) (8,92/,384) = /2 (/,384) V 59/9 Fa Figure a. Unipolar Operation (2-Quadrant Multiplication) V OUT = V to 3

14 LTC59/LTC59 APPLICATIONS INFORMATION U W U U 5V DATA INPUTS TO 2, 24 TO R R COM REF R R2 LTC59.µF V CC 4 5 -BIT DAC I OUT AGND 33pF LT V OUT = V TO Unipolar Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT VOUT (5,535/5,53) (32,8/5,53) = /2 (/5,53) V 59/9 Fb Figure b. Unipolar Operation (2-Quadrant Multiplication) V OUT = V to Bipolar Mode (4-Quadrant Multiplying, V OUT = to ) The LTC59/LTC59 contain on chip all the 4-quadrant resistors necessary for bipolar operation. 4-quadrant multiplying operation can be achieved with a minimum of external components, a capacitor and a dual op amp, as shown in Figure 2. With a fixed V reference, the circuit shown gives a precision bipolar V to V output swing. Op Amp Selection Because of the extremely high accuracy of the 4-/-bit LTC59/LTC59, thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Op amp offset will contribute mostly to output offset and gain and will have minimal effect on INL and DNL. For the LTC59, a 5µV op amp offset will cause about.55lsb INL degradation and.5lsb DNL degradation with a V full-scale range. The main effects of op amp offset will be a degradation of zero-scale error equal to the op amp offset, and a degradation of full-scale error equal to twice the op amp offset. For the LTC59, the same 5µV op amp offset (2mV offset for LTC59) will cause a 3.3LSB zero-scale error and a.5lsb full-scale error with a V full-scale range. Op amp input bias current (I BIAS ) contributes only a zeroscale error equal to I BIAS (/ ) = I BIAS (k). For a thorough discussion of -bit DAC settling time and op amp selection, refer to Application Note 4, Component and Measurement Advances Ensure -Bit DAC Settling Time. Reference Input and Grounding For optimum performance the reference input of the LTC59 should be driven by a source impedance of less than kω. However, these DACs have been designed to minimize source impedance effects. An 8kΩ source impedance degrades both INL and DNL by.2lsb. As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. AGND must be tied to the star ground with as low a resistance as possible. 4

15 LTC59/LTC59 APPLICATIONS INFORMATION U W U U 5V /2 LT2.µF 3 2 R R COM REF V CC pF Bipolar Offset Binary Code Table 4 DATA INPUTS TO 2, 24, 25 R R2 LTC59- NC NC BIT DAC I OUT AGND /2 LT2 V OUT = TO DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT V OUT (8,9/8,92) (/8,92) V (/8,92) 59/9 F2a Figure 2a. Bipolar Operation (4-Quadrant Multiplication) V OUT = to 5V /2 LT2.µF 3 2 R R COM REF V CC pF Bipolar Offset Binary Code Table DATA INPUTS TO 2, 24 TO 2 R R2 LTC59- -BIT DAC I OUT AGND /2 LT2 V OUT = TO DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT V OUT (32,/32,8) (/32,8) V (/32,8) 59/9 F2b Figure 2b. Bipolar Operation (4-Quadrant Multiplication) V OUT = to 5

16 LTC59/LTC59 TYPICAL APPLICATIONS U Noninverting Unipolar Operation (2-Quadrant Multiplication) V OUT = V to /2 LT2 5V.µF DATA INPUTS 3 R R 2 R COM REF R2 LTC59 V CC 4 5 -BIT DAC I OUT AGND 33pF /2 LT2 V OUT = V TO TO 2, 24 TO /9 F

17 LTC59/LTC59 TYPICAL APPLICATIONS U -Bit V OUT DAC Programmable Unipolar/Bipolar Configuration 5 4 LTCAC UNIPOLAR/ BIPOLAR 2 3 5V 2 LT48 LTA- 4 5V LT.µF 3 2 R R COM REF V CC 4 5 5pF DATA INPUTS R R2 LTC59 -BIT DAC I OUT AGND LT48 V OUT TO 2, 24 TO /9 F4

18 LTC59/LTC59 TYPICAL APPLICATIONS U Digital Waveform Generator 5V 2 LTA- 4 LT 5V.µF FREQUENCY CONTROL SERIAL OR BYTE LOAD REGISTER n PARALLEL DELTA PHASE REGISTER M n = 24 TO 32 BITS n PHASE ACCUMULATOR n Σ n PHASE REGISTER CLOCK n SIN ROM LOOKUP TABLE PHASE TRUNCATION BITS DATA INPUTS TO 2, 24 TO R R COM REF R R2 LTC59 V CC 4 5 -BIT DAC I OUT AGND 59/9 F5 5pF LT48 LOWPASS FILTER (M)(f C ) f O = 2 n f O 8

19 LTC59/LTC59 PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (.29) (LTC DWG # 5-8-4) * (..33) (.5.9) ** ( ).8.8 (.3.99) (.3.)..3 (.55.95) *DIMENSIONS DO NOT INCLUDE MO FLASH. MO FLASH SHALL NOT EXCEED." (.52mm) PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.254mm) PER SIDE.25 (.5) BSC..5 (.25.38) N Package 28-Lead PDIP (Narrow.3) (LTC DWG # 5-8-5).2.8 (.5.2) G28 SSOP 94.3* (34.89) MAX ±.5* (.4 ±.38) ( ).3 ±.5 (3.32 ±.2).45.5 (.43.5).9.5 (.9.38) ( ).2 (.58) MIN.25 (3.5) MIN *THESE DIMENSIONS DO NOT INCLUDE MO FLASH OR PROTRUSIONS. MO FLASH OR PROTRUSIONS SHALL NOT EXCEED. INCH (.254mm).5 (.2) MIN. ±. (2.54 ±.254).8 ±.3 (.45 ±.) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. N (.5) TYP 9

20 LTC59/LTC59 TYPICAL APPLICATION U -Bit Sign Magnitude DAC with Bipolar Zero Error of 4µV (.92LSB at Bits) at 25 C 5 4 5V 2 LTCAC LTA V LT48.µF 5pF SIGN BIT DATA INPUTS 3 2 R R COM REF R R2 LTC59 V CC 4 5 -BIT DAC I OUT AGND 2pF LT48 V OUT TO 2, 24 TO /9 F3 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Op Amps LT Precision Operational Amplifier Low Offset, Low Drift LT2 Dual Low Power, Precision Picoamp Input Op Amp Low Offset, Low Drift LT48 9MHz, V/µs, -Bit Accurate Op Amp Precise, µs Settling to.5% DACs LTC595/LTC59 Serial -Bit Current Output DACs Low Glitch, ±LSB Maximum INL, DNL LTC5 Serial -Bit Voltage Output DAC Low Noise and Glitch Rail-to-Rail VOUT LTC58 Serial 4-Bit Voltage Output DAC Low Power, 8-Lead MSOP Rail-to-Rail VOUT ADCs LTC48 4-Bit, 2ksps 5V Sampling ADC mw Dissipation, Serial and Parallel Outputs LTC4 -Bit, 333ksps Sampling ADC ±2.5V Input, SINAD = 9dB, THD = db LTC5 Single 5V, -Bit ksps ADC Low Power, ±V Inputs References LT Precision Reference Ultralow Drift, 5ppm/ C, High Accuracy.5% 2 Linear Technology Corporation 3 McCarthy Blvd., Milpitas, CA (48)432-9 FAX: (48) f LT/TP 298 4K PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 998