+3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC AD7304/AD7305*

Transcription

1 a FEATURES Four -Bit DACs in One Package +3 V, +5 V and 5 V Operation Rail-to-Rail REF-Input to Voltage Output Swing 2.6 MHz Reference Multiplying Bandwidth Compact. mm Height TSSOP 6-/2-Lead Package Internal Power ON Reset SPI Serial Interface Compatible AD734 Fast Parallel Interface AD735 4 A Power Shutdown APPLICATIONS Automotive Output Span Voltage Instrumentation, Digitally Controlled Calibration Pin-Compatible AD7226 Replacement when V DD < 5.5 V CS SDI/SHDN CLK +3 V/+5 V, Rail-to-Rail Quad, -Bit DAC AD734/AD735* FUNCTIONAL BLOCK DIAGRAMS V DD PWR ON RESET SERIAL V SS GND A B C D DAC B DAC C DAC D V REF B V REF A DAC B DAC C DAC D CLR LDAC V REF CV REF D AD734 V OUT A V OUT B V OUT C V OUT D V DD V REF GENERAL DESCRIPTION The AD734/AD735 are quad, -bit DACs that operate from a single +3 V to +5 V supply or ±5 V supplies. The AD734 has a serial interface, while the AD735 has a parallel interface. Internal precision buffers swing rail-to-rail. The reference input range includes both supply rails allowing for positive or negative fullscale output voltages. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V, consuming less than 9 mw from a +3 V supply. The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail V REF input to DAC V OUT allows for a full-scale voltage set equal the positive supply V DD, the negative supply V SS or any value in between. The AD734 s doubled-buffered serial-data interface offers high speed, three-wire, SPI and microcontroller compatible inputs using data in (SDI), clock (CLK) and chip select (CS) pins. Additionally, an internal power-on reset sets the output to zero scale. The parallel input AD735 uses a standard address decode along with the WR control line to load data into the input registers. The double buffered architecture allows all four input registers to be preloaded with new values, followed by a LDAC control strobe which copies all the new data into the DAC registers thereby updating the analog output values. When operating from less than +5.5 V, the AD735 is pin-compatible with the popular industry standard AD7226. DB DB DB2 DB3 DB4 DB5 DB6 WR A/SHDN A PWR ON RESET DECODE A B C D DAC B DAC C DAC D LDAC DAC B DAC C DAC D V SS AD735 GND V OUT A V OUT B V OUT C V OUT D An internal power ON reset places both parts in the zero-scale state at turn ON. A 4 µa power shutdown (SHDN) feature is activated on both parts by tristating the SDI/SHDN pin on the AD734, and tristating the A/SHDN address pin on the AD735. The AD734/AD735 are specified over the extended industrial ( 4 C to +5 C), and the automotive ( 4 C to +25 C) temperature ranges. AD734s are available in 6-lead plastic DIP (N-6), and wide-body SOL-6 (R-6) packages. The parallel input AD735 is available in the 2-lead plastic DIP (N-2), and the SOL-2 (R-2) surface mount package. For ultracompact applications the thin. mm TSSOP-6 (RU-6) package will be available for the AD734, while the TSSOP-2 (RU-2) will house the AD735. *Protected under Patent Number REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: 7/ World Wide Web Site: Fax: 7/ Analog Devices, Inc., 99

2 AD734/AD735 SPECIFICATIONS V DD = +3 V or +5 V, V SS = V; or V DD = +5 V and V SS = 5 V, V SS V REF V DD, 4 C < T A < +5 C/+25 C, unless otherwise noted.) Parameter Symbol Condition 3 V % 5 V % 5 V % Units STATIC PERFORMANCE Resolution N Bits Integral Nonlinearity 2 INL ± ± ± LSB max Differential Nonlinearity DNL Monotonic, All Codes to FF H ± ± ± LSB max Zero-Scale Error V ZSE Data = H 5 5 ±5 mv max Full-Scale Voltage Error V FSE Data = FF H ± 4 ± 4 ± 4 LSB max Full-Scale Tempco 3 TCV FS ppm/ C typ 4 REFERENCE V REFIN Range V REFIN V SS /V DD V SS /V DD V SS /V DD V min/max Input Resistance (AD734) R REFIN Code = 55 H kω typ Input Resistance (AD735) R REFIN All DACs at Code = 55 H kω typ Input Capacitance 3 C REFIN pf typ ANALOG OUTPUTS Output Voltage Range V OUT V SS /V DD V SS /V DD V SS /V DD V min/max Output Current Drive I OUT Code = H, V OUT < LSB ± 3 ± 3 ± 3 ma typ Shutdown Resistance R OUT DAC Outputs Placed in Shutdown State kω typ Capacitive Load 3 C L No Oscillation pf typ LOGIC S Logic Input Low Voltage V IL.6.. V min Logic Input High Voltage V IH V max Input Leakage Current 5 I IL ± ± ± µa max Input Capacitance 3 C IL pf max AC CHARACTERISTICS 3 Output Slew Rate SR Code = H to FF H to H /2.7 /3.6 /3.6 V/µs min/typ Reference Multiplying BW Small Signal, V SS = 5 V 2.6 MHz typ Total Harmonic Distortion THD V REF = 4 V p-p, V SS = 5 V, f = khz.25 % Settling Time 6 t S To ±.% of Full Scale./2./2./2 µs typ/max Shutdown Recovery Time t SDR To ±.% of Full Scale µs max Time to Shutdown t SDN µs typ DAC Glitch Q nvs typ Digital Feedthrough Q nvs typ Feedthrough V OUT /V REF Code = H, V REF = V p-p, f = khz 65 db SUPPLY CHARACTERISTICS Positive Supply Current I DD V LOGIC = V or V DD, No Load ma max Negative Supply Current I SS V SS = 5 V 6 ma max Power Dissipation P DISS V LOGIC = V or V DD, No Load mw max Power Down I DD_SD SDI/SHDN = Floating µa typ Power Supply Sensitivity PSS V DD = ±% %/% NOTES One LSB = V REF / The first three codes ( H, H, H ) are excluded from the integral nonlinearity error measurement in single supply operation +3 V or +5 V. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25 C. 5 SDI/SHDN and A/SHDN pins have 3 µa maximum I IL input leakage current. 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation. Specifications subject to change without notice. V REF = V p-p f = 2kHz 5V 5V V V 5V V OUT = V p-p 5V (OUT) (IN) Figure. AD734/AD735 Rail-to-Rail Reference Input to Output at 2 khz 2 REV. A

3 AD734/AD735 TIMING SPECIFICATIONS V DD = +3 V or +5 V, V SS = V; or V DD = +5 V and V SS = 5 V, V SS V REF V DD, 4 C < T A < +5 C/25 C, unless otherwise noted.) Parameter Symbol 3 V % 5 V % 5 V % Units INTERFACE TIMING SPECIFICATIONS, 2 AD734 Only Clock Width High t CH ns min Clock Width Low t CL ns min Data Setup t DS ns min Data Hold t DH ns min Load Pulsewidth t LDW ns min Load Setup t LD ns min Load Hold t LD ns min Clear Pulsewidth t CLWR ns min Select t CSS ns min Deselect t CSH ns min AD735 Only Data Setup t DS ns min Data Hold t DH ns min Address Setup t AS ns min Address Hold t AH ns min Write Width t WR ns min Load Pulsewidth t LDW ns min Load Setup t LS ns min Load Hold t LH ns min NOTES These parameters are guaranteed by design and not subject to production testing. 2 All input control signals are specified with t R = t F = 2 ns (% to 9% of V DD ) and timed from a voltage level of.6 V. ABSOLUTE MAXIMUM RATINGS* V DD to GND V, + V V SS to GND V, V V REFX to GND V SS, V DD Logic Inputs to GND V, V DD +.3 V V OUTX to GND V, V DD +.3 V I OUT Short Circuit to GND ma Package Power Dissipation (T J MAX T A )/θ JA Thermal Resistance θ JA 6-Lead Plastic DIP Package (N-6) C/W 6-Lead SOIC Package (R-6) C/W TSSOP-6 Package (RU-6) C/W 2-Lead Plastic DIP Package (N-2) C/W 2-Lead SOIC Package (R-2) C/W TSSOP-2 Package (RU-2) C/W Maximum Junction Temperature (T J MAX ) C Operating Temperature Range C to +5 C Storage Temperature Range C to +5 C Lead Temperature N-6 and N-2 (Soldering, secs) C R-6, R-2, RU-6, RU-2 (Vapor Phase, 6 secs) C R-6, R-2, RU-6, RU-2 (Infrared, 5 secs) C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD734/AD735 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Package Package Model Range Description Options AD734BN 4 C/+5 C 6-Lead P-DIP N-6 AD734BR 4 C/+5 C 6-Lead SOIC R-6 AD734YR 4 C/+25 C 6-Lead SOIC R-6 AD734BRU 4 C/+5 C TSSOP-6 RU-6 AD735BN 4 C/+5 C 2-Lead P-DIP N-2 AD735BR 4 C/+5 C 2-Lead SOIC R-2 AD735YR 4 C/+25 C 2-Lead SOIC R-2 AD735BRU 4 C/+5 C TSSOP-2 RU-2 The AD734/AD735 contains 2759 transistors. Die size: 3 mil 2 mil,,56 sq mil. WARNING! ESD SENSITIVE DEVICE REV. A 3

4 AD734/AD735 SDI SA SI A A D7 D6 D5 D4 D3 D2 D D CLK t CSS t CSH CS t LD2 LDAC t LD SDI t DS t DH CLK t CL t CH LDAC t LDW CLR FS V OUT ZS Figure 2. AD734 Timing Diagram t S LSB ERROR BAND t CLRW t S t SDN SDI/SHDN t SDR I DD Figure 3. AD734 Timing Diagram Table I. AD734 Control Logic Truth Table CS CLK LDAC CLR Serial Shift Register Function Input Function DAC Register Function H X H H No Effect No Effect No Effect L + H H Data Advanced Bit No Effect No Effect + L H H No Effect Updated with SR Contents 2 No Effect H X L H No Effect Latched with SR Contents 2 All Input Register Contents Transferred 3 H X H No Effect Loaded with H Loaded with H H X H + No Effect Latched with H Latched with H NOTES + positive logic transition; negative logic transition; X Don t Care. 2 One Input Register receives the data bits D7 D decoded from the SR address bits (A, A); where A = (, ); B = (, ); C = (, ); D = (, ). 3 LDAC is a level-sensitive input. Table II. AD734 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format MSB LSB B B B9 B B7 B6 B5 B4 B3 B2 B B AD734 SAC SDC A A D7 D6 D5 D4 D3 D2 D D If B (SAC), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B (SDC), Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A and A is placed in the shutdown mode. 4 REV. A

5 AD734/AD735 Table III. AD735 Control Logic Truth Table WR A A LDAC Input Register Function DAC Register Function L L L H A Loaded with DB DB7 Latched with Previous Contents, No Change + L L H A Latched with DB DB7 Latched with Previous Contents, No Change L L H H B Loaded with DB DB7 Latched with Previous Contents, No Change + L H H B Latched with DB DB7 Latched with Previous Contents, No Change L H L H C Loaded with DB DB7 Latched with Previous Contents, No Change + H L H C Latched with DB DB7 Latched with Previous Contents, No Change L H H H D Loaded with DB DB7 Latched with Previous Contents, No Change + H H H D Latched with DB DB7 Latched with Previous Contents, No Change H X X L No Effect All Input Register Contents Loaded, Register Transparent L X X L Input x Transparent to DB DB7 Register Transparent H X X + No Effect All Input Register Contents Latched H X X H No Effect, Device Not Selected No Effect, Device Not Selected NOTES + positive logic transition; negative logic transition; X Don t Care. 2 LDAC is a level sensitive input. PIN CONFIGURATIONS t WR V OUT B 2 V OUT C WR A, A D D7 t AS t DS t AH t DH V OUT B V OUT A V SS V REF A V REF B GND LDAC AD734 6 V OUT C 5 V OUT D 4 V DD 3 V REF C TOP VIEW 2 (Not to Scale) V REF D SDI/SHDN CLK V OUT A V SS V REF GND LDAC DB7 DB6 2 9 V OUT D 3 V DD 4 7 A/SHDN 5 AD735 6 A 6 TOP VIEW 5 WR (Not to Scale) 7 4 DB 3 DB t LS t LH t LDW CLR 9 CS DB5 9 2 DB2 LDAC DB4 DB3 t S V OUT LSB ERROR BAND Figure 4. AD735 Timing Diagram t SDN A/SHDN t SDR I DD Figure 5. AD735 Timing Diagram REV. A 5

6 AD734/AD735 AD734 PIN FUNCTION DESCRIPTIONS Pin # Name Function V OUT B Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REF B pin. Output is open circuit when SHDN is enabled. 2 V OUT A Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REF A pin. Output is open circuit when SHDN is enabled. 3 V SS Negative Power Supply Input. Specified range of operation V to 5.5 V. 4 V REF A Channel A Reference Input. Establishes V OUT A full-scale voltage. Specified range of operation V SS < V REF A < V DD. 5 V REF B Channel B Reference Input. Establishes V OUT B full-scale voltage. Specified range of operation V SS < V REF B < V DD. 6 GND Common Analog and Digital Ground. 7 LDAC Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous active low input. DAC Register is transparent when LDAC =. See Control Logic Truth Table for operation. CLR Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected. 9 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the decoded Input Register when CS returns HIGH. Does not effect LDAC operation. CLK Clock input, positive edge clocks data into shift register. Disabled by chip select CS. SDI/SHDN Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is present on V DD. 2 V REF D Channel D Reference Input. Establishes V OUT D full-scale voltage. Specified range of operation V SS < V REF D < V DD. 3 V REF C Channel C Reference Input. Establishes V OUT C full-scale voltage. Specified range of operation V SS < V REF C < V DD. 4 V DD Positive power supply input. Specified range of operation +2.7 V to +5.5 V. 5 V OUT D Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REF D pin. Output is open circuit when SHDN is enabled. 6 V OUT C Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REF C pin. Output is open circuit when SHDN is enabled. Pin # Name Function AD735 PIN FUNCTION DESCRIPTIONS V OUT B Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REF B pin. Output is open circuit when SHDN is enabled. 2 V OUT A Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REF A pin. Output is open circuit when SHDN is enabled. 3 V SS Negative Power Supply Input. Specified range of operation V to 5.5 V. 4 V REF Channel B Reference Input. Establishes V OUT full-scale voltage. Specified range of operation V SS < V REF < V DD. 5 GND Common Analog and Digital Ground. 6 LDAC Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous active low input. DAC Register is transparent when LDAC =. See Control Logic Truth Table for operation. 7 DB7 MSB Digital Input Data Bit. DB6 Data Bit 6. 9 DB5 Data Bit 5. DB4 Data Bit 4. DB3 Data Bit 3. 2 DB2 Data Bit 2. 3 DB Data Bit. 4 DB LSB Digital Input Data Bit. 5 WR Write data into Input Register control line, active low. See Control Logic Truth Table for operation. 6 A Address Bit. 7 A/SHDN Address Bit /Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is present on V DD. V DD Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V. 9 V OUT D Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REF D pin. Output is open circuit when SHDN is enabled. 2 V OUT C Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REF C pin. Output is open circuit when SHDN is enabled. 6 REV. A

7 Typical Performance Characteristics AD734/AD V REF = V DD.6 I OUT SINK CURRENT ma DATA = H INL LSB.2.2 DAC D DAC B DAC C 24.6 DATA = H T A = +25 C V OUT mv Figure 6. I OUT SINK vs. V OUT Rail-to-Rail Performance REFERENCE VOLTAGE Volts Figure 9. INL vs. Reference Input Voltage I OUT SOURCE CURRENT ma V REF = V DD DATA = FF H DNL LSB V REF = 2.5V V OUT OUTPUT VOLTAGE Volts Figure 7. I OUT SOURCE vs. V OUT Rail-to-Rail Performance CODE Decimal Figure. DNL vs. Code INL LSB DAC B DAC C V REF = +2.5V T A = +25 C DAC D CODE Decimal Figure. INL vs. Code, All DAC Channels ZERO SCALE VOLTAGE mv V DD = +5.5V V SS = V V REF = +5.45V TEMPERATURE C Figure. Zero Scale Voltage vs. Temperature REV. A 7

8 AD734/AD735 V OUT V REF = +4V DATA = H FF H NO LOAD R L = 7k C L = 5pF CS R L = k CS V 5V V V OUT 2 s/div Figure 2. Large-Signal Settling Time 5 s/div Figure 5. Time to Shutdown 5V CS V REFIN ( 5kHz) DATA = FF H V 5V I DD ma/v V OUTA 5V 5V V V OUT 2 s/div Figure 3. Multiplying Mode Step Response and Output Slew Rate Figure 6. Shutdown Recovery Time (Wakeup) 6 4 DATA = FF H V REF = mv rms A GAIN db 4 f 3dB = 2.6MHz THD %. 6. k k M FREQUENCY Hz M Figure 4. Multiplying Mode Gain vs. Frequency. m V REF AMPLITUDE V p-p Figure 7. THD vs. Reference Input Amplitude REV. A

9 AD734/AD735 THD %. A V OUT V REF = 2.5V F = MHz DATA = H 7F H. CS. 2 k k k FREQUENCY Hz Figure. THD vs. Frequency Figure 2. Midscale Transition Glitch 3. 4 NOISE DENSITY V/ Hz V REF = 4V DATA = FF H CROSS TALK db V REF = 5mV rms DATA = FF H DAC B, C, D DATA = H CT = 2 LOG V OUTB V REF 4 k k k FREQUENCY Hz Figure 9. Output Noise Voltage Density vs. Frequency 6 k k k M M FREQUENCY Hz Figure 22. Crosstalk vs. Frequency 6 5 PSRR, % +PSRR, % 4 V OUTB CLK V REF = 2.5V = FF H DAC B = OO H F = 2MHz PSRR db 3 2 +PSRR, V DD = +3V % PSRR, V SS = 3V % DATA = H T A = +25 C 5ns/DIV k FREQUENCY Hz k k Figure 2. Digital Feedthrough Figure 23. Power Supply Rejection vs. Frequency REV. A 9

10 AD734/AD735 2 SUPPLY CURRENT ma I DD I SS V REF = 2.5V A = 5V ALL OTHER DIGITAL PINS VARYING SHUTDOWN SUPPLY A V DD = +5.5V V SS = 5.5V V REF = 2.5V PIN A FLOATING DIGITAL VOLTAGE Volts Figure 24. Supply Current vs. Digital Input Voltage TEMPERATURE C Figure 27. Shutdown Supply Current vs. Temperature.. SUPPLY CURRENT ma.... I DD I SS V REF = 2.5V ALL DIGITAL PINS VARY, EXCEPT A = 5V NORMALIZED TOTAL UNADJUSTED ERROR DRIFT LSB.4.4 READING MADE AT T A = +25 C SAMPLE SIZE = 924 UNITS V DD = 2.7V V DD = 5.5V DIGITAL VOLTAGE Volts Figure 25. Shutdown Supply Current vs. Digital Input Voltage (A Only) DEGREES CELCIUS Figure 2. Normalized TUE Drift Accelerated by Burn-In Hours of 5 C V REF = 2.5V SUPPLY CURRENT ma I DD AND I SS TEMPERATURE C Figure 26. Supply Current vs. Temperature REV. A

11 AD734/AD735 CIRCUIT OPERATION The AD734/AD735 are a set of four-channel, -bit, voltageoutput, digital-to-analog converters differing primarily in digital logic interface and number of reference inputs. Both parts share the same internal DAC design and true rail-to-rail output buffers. The AD734 contains four independent multiplying reference inputs, while the AD735 has one common reference input. The AD734 uses a 3-wire SPI compatible serial data interface, while the AD735 offers a -bit parallel data interface. D/A Converter Section Each part contains four voltage-switched R-2R ladder DACs. Figure A shows a typical equivalent DAC. These DACs are designed to operate both single-supply or dual supply, depending on whether the user supplies a negative voltage on the V SS pin. In a single-supply application the V SS is tied to ground. In either mode the DAC output voltage is determined by the V REF input voltage and the digital data (D) loaded into the corresponding DAC register according to Equation. V OUT = V REF D/256 () Note that the output full-scale polarity is the same as the V REF polarity for dc reference voltages. V REF DB7 2R DB6 2R DB 2R R 2R V DD V SS V OUT Figure 29. Typical Equivalent DAC Channel These DACs are also designed to accommodate ac reference input signals. As long as the ac signals are maintained between V SS < V REF <V DD, the user can expect 5 khz of full-power multiplying bandwidth performance. In order to use negative input reference voltages, the V SS pin must be biased with a negative voltage of equal or greater magnitude than the reference voltage. The reference inputs are code-dependent, exhibiting worst case minimum resistance values specified in the parametric specification table. The DAC outputs V OUT A, B, C, D are each capable of driving 2 kω loads in parallel with up to 5 pf loads. Output source and sink current is shown in Figures 6 and 7. The output slew rate is nominally 3.6 V/µs while operating from ±5 V supplies. The low output impedance of the buffers minimizes crosstalk between analog input channels. At khz, 65 db of channel-to-channel isolation exists (Figure 22). Output voltage noise is plotted in Figure 9. In order to maintain good analog performance, power supply bypassing of. µf in parallel with µf is recommended. The true rail-to-rail capability of the AD734/AD735 allows the user to connect the reference inputs directly to the same supply as the V DD or V SS pin (Figure 3). Under these conditions clean power supply voltages (low ripple, avoid switching supplies) appropriate for the application should be used. Q Q2 V DD V SS 2k V OUT X Figure 3. Equivalent mplifier Output Circuit AD734 SERIAL DATA INTERFACE The AD734 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. New serial data is clocked into the serial input register in a 2-bit data-word format. MSB bits are loaded first. Table II defines the 2 data-word bits. Data is placed on the SDI/SHDN pin and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the TIMING SPECIFICATIONS. Data can only be clocked in while the CS chip select pin is active low. Only the last 2-bits clocked into the serial register will be interrogated when the CS pin returns to the logic high state, extra data bits are ignored. Since most microcontrollers output serial data in -bit bytes, two right justified data bytes can be written to the AD734. Keeping the CS line low between the first and second byte transfer will result in a successful serial register update. Once the data is properly aligned in the shift register the positive edge of the CS initiates either the transfer of new data to the target DAC register, determined by the decoding of address bits A and A, or the shutdown features will be activated based on the SAC or SDC bits. When either SAC or SDC pins are set (Logic = ) the loading of new data determined by Bits B9 to B are still loaded, but the results do not appear on the buffer outputs until the device is brought out of the shutdown state. The selected DAC output voltages become high impedance with a nominal resistance of 2 kω to ground, Figure 3. If both SAC and SDC pins are set, all channels are still placed in the shutdown mode. When the AD734 has been programmed into the power shutdown state, the present DAC register data is maintained as long as V DD remains greater than 2.7 volts. The remaining characteristics of the software serial interface are defined by Tables I, II and Figure 3 timing diagram. Two additional pins CLR and LDAC on the AD734 provide hardware control over the clear function and the DAC Register loading. If these functions are not needed the CLR pin can be tied to logic high, and the LDAC pin can be tied to logic low. The asynchronous input CLR pin forces all input and DAC registers to the zero-code state. The asynchronous LDAC pin can be strobed to active low when all DAC Registers need to be updated simultaneously from their respective Input Registers. The LDAC pin places the DAC Register in a transparent mode while in the logic low state. REV. A

12 AD734/AD735 V REF A V REF B V REF C V REF D V DD V REF V DD CS CLK EN AD734 DATA DB DB7 AD735 SDI D D D2 D3 D4 D5 D6 D7 A A SDC SAC 64k DACA B 2:4 C DECODE D V DD 6k g D Q g D Q g D Q DAC B DAC C DAC D OE DAC B OE DAC C OE DAC D OE V OUT A V OUT B V OUT C V OUT D WR A A/SHDN B 2:4 C DECODE D VDD 64k 6k DAC B DAC C DAC D OE DAC B OE DAC C OE DAC D OE V OUT A V OUT B V OUT C V OUT D k g D Q k 2k 32k POWER- ON RESET 2k 32k POWER- ON RESET GND LDAC Figure 3. AD734 Equivalent Logic Interface AD734 Hardware Shutdown SHDN If a three-state driver is used on the SDI/SHDN pin, the AD734 can be placed into a power shutdown mode when the SDI/ SHDN pin is placed in a high impedance state. For proper operation no other termination voltages should be present on this pin. An internal window comparator will detect when the logic voltage on the SHDN pin is between 2% and 36% of V DD. A high impedance internal bias generator provides this voltage on the SHDN pin. The four DAC output voltages become high impedance with a nominal resistance of 2 kω to ground. See Figure 3 for an equivalent circuit. AD734/AD735 POWER ON RESET When the V DD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the zero-code state. The V DD power supply should have a monotonically increasing ramp in order to have consistent results, especially in the region of V DD =.5 V to 2.3 V. The V SS supply has no effect on the power ON reset performance. The DAC register data will stay at zero until a valid serial register software load takes place. In the case of the double buffered AD735 the output DAC register can only be changed once the LDAC strobe is initiated. AD735 PARALLEL DATA INTERFACE The AD735 has an -bit parallel interface DB7 = MSB, DB = LSB. Two address Bits A and A are decoded when an active low write strobe is placed on the WR pin, see Table III. The WR is a level-sensitive input pin, therefore the data setup and data hold times defined in the TIMING SPECIFICATIONS need to be adhered to. The LDAC pin provides the capability of simultaneously updating all DAC registers with new data from the Input Registers at CLR V SS the same time. This will result in the analog outputs all changing to their new values at the same time. The LDAC pin is a level-sensitive input. If the simultaneous update feature is not required the LDAC pin can be tied to logic low. When the LDAC is tied to logic low, the DAC Registers become transparent and the Input Register data determines the DAC output voltage. See Figure 32 for an equivalent interface logic diagram. AD7226 Pin Compatibility By tying the LDAC pin to ground, the AD735 has the same pin out and functionality as the AD7226, with the exception of a lower power supply operating voltage. AD735 Hardware Shutdown SHDN If a three state driver is used on the A/SHDN pin, the AD735 can be placed into a power shutdown mode when the A/SHDN pin is placed in a high impedance state. For proper operation no other termination voltages should be present on this pin. An internal window comparator will detect when the logic voltage on the SHDN pin is between 2% and 36% of V DD. A high impedance internal bias generator provides this voltage on the SHDN pin. The four DAC output voltages become high impedance with a nominal resistance of 2 kω to ground. ESD Protection Circuits All logic input pins contain back-biased ESD protection Zeners connected to ground (GND). The V REF pins also contain a back-biased ESD protection Zener connected to V DD (see Figure 33). DIGITAL S GND GND LDAC Figure 32. AD735 Equivalent Logic Interface V DD V REF X Figure 33. Equivalent ESD Protection Circuits V SS 2 REV. A

13 AD734/AD735 APPLICATIONS The AD734/AD735 is inherently a 2-quadrant multiplying D/A converter. That is, it can easily be set up for unipolar output operation. The full-scale output polarity is the same as the reference input voltage polarity. In some applications it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished using an external true rail-to-rail op amp, such as the OP295. Connecting the external amplifier with two equal value resistors as shown in Figure 34 results in a full 4-quadrant multiplying circuit. In this circuit the amplifier provides a gain of two, which increases the output span magnitude to volts. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (V OUT = 5 V) to midscale (V OUT = V) to full scale (V OUT = +5 V). V OUT = (D/2 ) V REF (2) +5V k k 5V < V OUT < +5V AD734 REF Figure 34. Four-Quadrant Multiplying Application Circuit REV. A 3

14 AD734/AD735 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 6-Lead Wide SOIC (R-6) 2-Lead SOIC (R-2).433 (.5).3977 (.).5 (3.).496 (2.6) (7.6).294 (7.4).493 (.65).3937 (.).2992 (7.6).294 (7.4).493 (.65).3937 (.). (.3).4 (.) PIN.43 (2.65).926 (2.35).29 (.74).9 (.25) x 45 PIN.43 (2.65).926 (2.35).29 (.74).9 (.25) x 45.5 (.27) BSC.92 (.49) SEATING.3 (.35) PLANE.25 (.32).9 (.23).5 (.27).57 (.4). (.3).4 (.).5 (.27) BSC.92 (.49).3 (.35) SEATING PLANE.25 (.32).9 (.23).5 (.27).57 (.4) 6-Lead Plastic DIP (N-6) 2-Lead Plastic DIP (N-2).4 (2.33).745 (.93).6 (26.9).925 (23.5) 6.6 (4.6).5 (2.93).22 (.55).4 (.356) 9.2 (7.).24 (6.) PIN.6 (.52).2 (5.33).5 (.3) MAX.3. (2.54) BSC (3.3) MIN.7 (.77) SEATING.45 (.5) PLANE.325 (.25).3 (7.62).95 (4.95).5 (2.93).5 (.3). (.24) 2 PIN.2 (5.33) MAX.6 (4.6).5 (2.93).22 (.55).4 (.356). (2.54) BSC.2 (7.).24 (6.).6 (.52).5 (.3).3 (3.3) MIN.7 (.77) SEATING.45 (.5) PLANE.325 (.25).3 (7.62).95 (4.95).5 (2.93).5 (.3). (.24) 6-Lead TSSOP (RU-6) 2-Lead Thin Surface Mount (TSSOP) (RU-2).2 (5.).93 (4.9).26 (6.6).252 (6.4) (4.5).69 (4.3).256 (6.5).246 (6.25).77 (4.5).69 (4.3).256 (6.5).246 (6.25).6 (.5).2 (.5) SEATING PLANE PIN.256 (.65) BSC. (.3).75 (.9).433 (.) MAX.79 (.2).35 (.9).2 (.7).2 (.5).6 (.5).2 (.5) SEATING PLANE PIN.256 (.65) BSC. (.3).75 (.9).433 (.) MAX.79 (.2).35 (.9).2 (.7).2 (.5) 4 REV. A

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16 PRINTED IN U.S.A. C3252 2/9 6