FEATURES DESCRIPTIO TYPICAL APPLICATIO LTC Bit, Ultra Precise, Fast Settling V OUT DAC APPLICATIO S

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1 FEATURES µs Settling to.15% for 1V Step 1LSB Max DNL and INL Over Industrial Temperature Range On-Chip 4-Quadrant Resistors Allow Precise V to 1V, V to 1V or ±1V Outputs Low Glitch Impulse: nv s Low Noise: 1nV/ Hz -Lead SSOP Package Power-On Reset Asynchronous Clear Pin LTC181: Reset to Zero Scale LTC181-1: Reset to Midscale APPLICATIO S U DESCRIPTIO U LTC181 1-Bit, Ultra Precise, Fast Settling DAC The LTC 181 is a parallel input 1-bit multiplying voltage output DAC that operates from analog supply voltages of ±5V up to ±15V. INL and DNL are accurate to 1LSB over the industrial temperature range in both unipolar V to 1V and bipolar ±1V modes. Precise 1-bit bipolar ±1V outputs are achieved with on-chip 4-quadrant multiplication resistors. The LTC181 is available in a -lead SSOP package and is specified over the industrial temperature range. The device includes an internal deglitcher circuit that reduces the glitch impulse to less than nv s (typ). The LTC181 settles to 1LBS in µs with a full-scale 1V step. The combination of fast, precise settling and ultra low glitch make the LTC181 ideal for precision industrial control applications. The asynchronous CLR pin resets the LTC181 to zero scale and resets the LTC181-1 to midscale. Process Control and Industrial Automation Precision Instrumentation Direct Digital Waveform Generation Software-Controlled Gain Adjustment, LTC and LT are registered trademarks of Linear Technology Corporation. Automatic Test Equipment TYPICAL APPLICATIO U 1-Bit, 4-Quadrant Multiplying DAC with a Minimum of External Components V REF V REF 1 DATA INPUTS TO, 5 TO WR LD CLR R1 R COM REF V CC R1 WR LD CLR 4 7 LT 8 R LTC pF 11 1 R OFS R FB I OUT R OFS DNC* DNC* DNC* NC *DO NOT CONNECT 5V.1µF R FB 1-BIT DAC DGND 1 AGNDF 17 1 AGNDS 15pF V V V.1µF V REF = V REF 15V.1µF 181 TA1 INTEGRAL NONLINEARITY (LSB) LTC181/LTC181-1 Integral Nonlinearity V REF = 1V = ±1V BIPOLAR DIGITAL INPUT CODE 181 TA 1

2 ABSOLUTE MAXIMUM RATINGS W W W (Note 1) V CC to AGNDF, AGNDS....V to 7V V CC to DGND....V to 7V Total Supply Voltage (V to V )... V AGNDF, AGNDS to DGND... V CC.V DGND to AGNDF, AGNDS... V CC.V REF, R COM to AGNDF, AGNDS, DGND... ±15V R OFS, R FB, R1, to AGNDF, AGNDS, DGND... ±15V Digital Inputs to DGND....V to (V CC.V) I OUT to AGNDF, AGNDS....V to (V CC.V) Maximum Junction Temperature C Operating Temperature Range LTC181C/LTC181-1C... C to 7 C LTC181I/LTC181-1I... 4 C to 85 C Storage Temperature Range... 5 C to 15 C Lead Temperature (Soldering, 1 sec)... C U PACKAGE/ORDER INFORMATION DGND 1 V CC D D 4 D1 5 D CLR 7 REF 8 R COM 9 R1 1 R OFS 11 R FB 1 VOUT 1 I OUT V 15 AGNDS 1 AGNDF 17 DNC* 18 TOP VIEW D4 5 D5 4 D D7 D8 1 D9 D1 9 D11 8 D1 7 D1 D 5 D15 4 WR LD NC 1 DNC* V 19 DNC* GW PACKAGE -LEAD PLASTIC SSOP WIDE T JMAX = 15 C, θ JA = 8 C/ W *DO NOT CONNECT U W U ORDER PART NUMBER LTC181ACGW LTC181BCGW LTC181-1ACGW LTC181-1BCGW LTC181AIGW LTC181BIGW LTC181-1AIGW LTC181-1BIGW Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are T A = T MIN to T MAX, V = 15V, V = 15V, V CC = 5V, V REF = 1V, AGNDF = AGNDS = DGND = V. LTC181B/-1B LTC181A/-1A SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Accuracy Resolution 1 1 Bits Monotonicity 1 1 Bits INL Integral Nonlinearity T A = 5 C (Note ) ± ±.5 ±1 LSB T MIN to T MAX ± ±.5 ±1 LSB DNL Differential Nonlinearity T A = 5 C ±1 ±. ±1 LSB T MIN to T MAX ±1 ±. ±1 LSB GE Gain Error Unipolar Mode T A = 5 C (Note ) ±1 ±5 ±1 LSB T MIN to T MAX ±4 ±8 ±1 LSB Bipolar Mode T A = 5 C (Note ) ±1 ± ±1 LSB T MIN to T MAX ± 4 ±5 ±1 LSB Gain Temperature Coefficient Gain/ Temperature (Note 4) 1 1 ppm/ C Unipolar Zero-Scale Error T A = 5 C ± ±.5 ± LSB T MIN to T MAX ± ±.5 ±4 LSB Bipolar Zero Error T A = 5 C ±1 ± ±8 LSB T MIN to T MAX ±1 ± ±1 LSB PSRR Power Supply Rejection Ratio V CC = 5V ±1%.7 LSB/V V, V = ±4.5V to ±1.5V ± ±.1 ± LSB/V

3 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are T A = T MIN to T MAX, V = 15V, V = 15V, V CC = 5V, V REF = 1V, AGNDF = AGNDS = DGND = V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input R REF DAC Input Resistance (Unipolar) (Note ) kω R1/R R1/R Resistance (Bipolar) (Notes, 11) 9 1 kω R OFS, R FB Feedback and Offset Resistances (Note ) 9 1 kω AC Performance (Note 4) Analog Outputs (Note 4) Output Voltage Settling Time = 1V (Notes 7, 8) µs Midscale Glitch Impulse (Note 1) nv s Digital-Feedthrough (Note 9) nv s Multiplying Feedthrough Error V REF = ±1V, 1kHz Sine Wave (Note 7) 1 mv P-P Multiplying Bandwidth Code = Full Scale (Note 7) khz Output Noise Voltage Density 1kHz to 1kHz (Note 7) Code = Zero Scale 1 nv/ Hz Code = Full Scale nv/ Hz Output Noise Voltage.1Hz to 1Hz (Note 7) Code = Zero Scale.45 µv RMS Code = Full Scale 1 µv RMS 1/f Noise Corner (Note 7) Hz DAC Output Swing R L = k, V = 15V, V = 15V ±1. V R L = k, V = 5V, V = 5V ±. V DAC Output Load Regulation V = 15V, V = 15V, ±5mA Load.. LSB/mA I SC Short-Circuit Current = V, V = 15V, V = 15V 1 4 ma SR Slew Rate R L = k, V = 15V, V = 15V V/µs R L = k, V = 5V, V = 5V V/µs Digital Inputs V IH Digital Input High Voltage.4 V V IL Digital Input Low Voltage.8 V I IN Digital Input Current.1 ±1 µa C IN Digital Input Capacitance (Note 4 ) V IN = V 8 pf Timing Characteristics t DS Data to WR Setup Time ns t DH Data to WR Hold Time 1 ns t WR WR Pulse Width 5 ns t LD LD Pulse Width ns t CLR Clear Pulse Width 4 ns t LWD WR to LD Delay Time ns Power Supply I CC Supply Current, V CC Digital Inputs = V or V CC µa I S Supply Current, V, V ±15V ma ±5V 4..8 ma V CC Supply Voltage V V Supply Voltage V V Supply Voltage V

4 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : ±1LSB = ±.15% of full scale = ±15.ppm of full scale. Note : Using internal feedback resistor. Note 4: Guaranteed by design, not subject to test. Note 5: I OUT with DAC register loaded to all s. Note : Typical temperature coefficient is 1ppm/ C. Note 7: Measured in unipolar mode. Note 8: To.15% for a full-scale change, measured from the rising edge of LD. Note 9: REF = V. DAC register contents changed from all s to all 1s or all 1s to all s. LD low and WR high. Note 1: Midscale transition code: to 1. Unipolar mode, C FEEDBACK = pf. Note 11: R1 and R are measured between R1 and R COM, REF and R COM. TYPICAL PERFOR A CE CHARACTERISTICS UW Midscale Glitch Impulse Full-Scale Setting Waveform Unipolar Multiplying Mode Signal-to-(Noise Distortion) vs Frequency OUTPUT VOLTAGE (mv) 4 CFEEDBACK = pf V REF = 1V 1 1nV-s TYPICAL TIME (µs) LD PULSE 5V/DIV GATED SETTLING WAVEFORM 5µV/DIV V REF = 1V C FEEDBACK = pf V TO 1V STEP 5ns/DIV 181 G SIGNAL/(NOISE DISTORTION) (db) V CC = 5V C FEEDBACK = pf REFERENCE = V RMS 8kHz FILTER 5kHz FILTER khz FILTER k 1k 1k FREQUENCY (Hz) 181 G1 181 G SIGNAL/(NOISE DISTORTION) (db) Bipolar Multiplying Mode Signal-to-(Noise Distortion) vs Frequency, Code = All Zeros V CC = 5V USING AN LT8 C FEEDBACK = 15pF REFERENCE = V RMS 5kHz FILTER 1 8kHz FILTER khz 11 FILTER 1 1 1k 1k 1k FREQUENCY (Hz) SIGNAL/(NOISE DISTORTION) (db) Bipolar Multiplying Mode Signal-to-(Noise Distortion) vs Frequency, Code = All Ones V CC = 5V USING AN LT8 C FEEDBACK = 15pF REFERENCE = V RMS 5kHz FILTER 1 8kHz FILTER khz FILTER k 1k 1k FREQUENCY (Hz) SUPPLY CURRENT (ma) V CC Supply Current vs Digital Input Voltage V CC = 5V ALL DIGITAL INPUTS TIED TOGETHER INTPUT VOLTAGE (V) 181 G4 181 G5 181 G 4

5 TYPICAL PERFOR A CE CHARACTERISTICS UW LOGIC THRESHOLD (V) Logic Threshold vs V CC Supply Voltage Integral Nonlinearity (INL) Differential Nonlinearity (DNL) SUPPLY VOLTAGE (V) INTEGRAL NONLINEARITY (LSB) DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY (LSB) DIGITAL INPUT CODE 181 G7 181 G8 181 G9 INTEGRAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY (LSB) Integral Nonlinearity vs Reference Voltage in Unipolar Mode REFERENCE VOLTAGE (V) 181 G1 Differential Nonlinearity vs Reference Voltage in Bipolar Mode REFERENCE VOLTAGE (V) 181 G1 INTEGRAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity vs Reference Voltage in Bipolar Mode REFERENCE VOLTAGE (V) 181 G11 Integral Nonlinearity vs V CC Supply Voltage in Unipolar Mode V REF =.5V V REF =.5V V REF = 1V V REF = 1V SUPPLY VOLTAGE (V) 181 G DIFFERENTIAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) Differential Nonlinearity vs Reference Voltage in Unipolar Mode V REF = 1V REFERENCE VOLTAGE (V) V REF =.5V V REF = 1V V REF =.5V 181 G1 Integral Nonlinearity vs V CC Supply Voltage in Bipolar Mode SUPPLY VOLTAGE (V) 181 G15 5

6 TYPICAL PERFOR A CE CHARACTERISTICS UW DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity vs V CC Supply Voltage in Unipolar Mode V REF = 1V V REF =.5V V REF = 1V V REF =.5V SUPPLY VOLTAGE (V) 181 G1 DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity vs V CC Supply Voltage in Bipolar Mode V REF =.5V V REF =.5V V REF = 1V V REF = 1V SUPPLY VOLTAGE (V) 181 G17 ATTENUATION (db) Unipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS ON D15 ON D ON D1 ON D1 ON D11 ON D1 ON D9 ON D8 ON D7 ON D ON D5 ON D4 ON D ON D ON D1 ON D ON ALL BITS OFF 1 1 1k 1k 1k 1M 1M FREQUENCY (Hz) V REF LTC pf 181 G18 ATTENUATION (db) Bipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS ON D15 AND D ON D15 AND D1 ON D15 AND D1 ON D15 AND D11 ON D15 AND D1 ON D15 AND D9 ON D15 AND D8 ON D15 AND D7 ON D15 AND D ON D15 AND D5 ON D15 AND D4 ON D15 AND D ON D15 AND D ON CODES FROM MIDSCALE TO FULL SCALE D15 AND D1 ON D15 AND D ON D15 ON* 1 1k 1k 1k 1M 1M FREQUENCY (Hz) 181 G19 *DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO 9dB TYPICAL (78dB MAX, A GRADE) V REF LT8 1pF 1pF ATTENUATION (db) 4 8 Bipolar Multiplying Mode Frequency Response vs Digital Code ALL BITS OFF D ON D AND D1 ON D TO D1 ON D TO D11 ON D TO D1 ON D TO D9 ON D TO D8 ON D TO D7 ON D TO D ON D TO D5 ON D TO D4 ON D TO D ON D TO D ON D TO D1 ON CODES FROM MIDSCALE TO ZERO SCALE D TO D ON D15 1 ON* 1 1 1k 1k 1k 1M 1M FREQUENCY (Hz) 181 G *DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO 9dB TYPICAL (78dB MAX, A GRADE) V REF LT8 1pF 1pF LTC pF LTC pF

7 PIN FUNCTIONS U U U DGND (Pin 1): Digital Ground. Connect to analog ground. V CC (Pin ): Positive Supply Input. 4.5V V CC 5.5V. Requires a bypass capacitor to ground. D (Pin ): Digital Input Data Bit. D (Pin 4): Digital Input Data Bit. D1 (Pin 5): Digital Input Data Bit 1. D (Pin ): LSB or Digital Input Data Bit. CLR (Pin 7): Digital Clear Control Function for the DAC. When CLR is taken to a logic low, it sets the DAC output and all internal registers to: zero code for the LTC181 and midscale code for the LTC REF (Pin 8): Reference Input and 4-Quadrant Resistor R. Typically ±1V, accepts up to ±15V. In -quadrant mode, tie this pin to the external reference signal. In 4-quadrant mode, this pin is driven by external inverting reference amplifier. R COM (Pin 9): Center Tap Point of the Two 4-Quadrant Resistors R1 and R. Normally tied to the inverting input of an external amplifier in 4-quadrant operation. Otherwise this pin is shorted to the REF pin. See Figures 1 and. R1 (Pin 1): 4-Quadrant Resistor R1. In -quadrant operation, short this pin to the REF pin. In 4-quadrant mode, tie this pin to the external reference signal. R OFS (Pin 11): Bipolar Offset Resistor. Typically swings ±1V, accepts up to ±15V. For -quadrant operation, tie this pin to R FB and for 4-quadrant operation, tie this pin to R1. R FB (Pin1): Feedback Resistor. Normally connected to. Typically swings ±1V. The voltage at this pin swings to V REF in unipolar mode and ±V REF in bipolar mode. (Pin 1): DAC Voltage Output. Normally connected to R FB and to I OUT through a pf feedback capacitor in unipolar mode (15pF in bipolar mode). Typically swings ±1V. I OUT (Pin ): DAC Current Output. Normally tied through a pf feedback capacitor in unipolar mode (15pF in bipolar mode) to. V (Pin 15): Amplifier Positive Supply. Range is 4.5V to 1.5V. AGNDS (Pin 1): Analog Ground Sense. Connect to analog ground. AGNDF (Pin 17): Analog Ground Force. Connect to analog ground. DNC (Pin 18, 19, 1): Connected internally. Do not connect external circuitry to these pins. V (Pin ): Amplifier Negative Supply. Range is 4.5V to 1.5V. NC (Pin ): No Connection. LD (Pin ): DAC Digital Input Load Control Input. When LD is taken to a logic high, data is loaded from the input register into the DAC register, updating the DAC output. WR (Pin 4): DAC Digital Write Control Input. When WR is taken to a logic low, data is written from the digital input pins into the 1-bit wide input reigster. D15 (Pins 5): MSB or Digital Input Data Bit 15. D (Pin ): Digital Input Data Bit. D1 (Pin 7): Digital Input Data Bit 1. D1 (Pin 8): Digital Input Data Bit 1. D11 (Pin 9): Digital Input Data Bit 11. D1 (Pin ): Digital Input Data Bit 1. D9 (Pin 1): Digital Input Data Bit 9. D8 (Pin ): Digital Input Data Bit 8. D7 (Pin ): Digital Input Data Bit 7. D (Pin 4): Digital Input Data Bit. D5 (Pin 5): Digital Input Data Bit 5. D4 (Pin ): Digital Input Data Bit 4. 7

8 TRUTH TABLE Table 1 CONTROL INPUTS CLR WR LD REGISTER OPERATION X X Reset Input and DAC Register to All s for LTC181 and Midscale for LTC181-1 (Asynchronous Operation) 1 Write Input Register with All 1 Data Bits Load DAC Register with the Contents of the Input Register 1 1 Input and DAC Register Are Transparent 1 CLK = LD and WR Tied Together. The 1 Data Bits Are Written Into the Input Register on the Falling Edge of the CLK and Then Loaded Into the DAC Register on the Rising Edge of the CLK 1 1 No Register Operation BLOCK DIAGRA W REF 8 48k 48k 1 R FB R COM 9 1k 48k 48k 48k 48k 48k 48k 48k 9k 9k 9k 9k 1k 1k 11 R OFS R1 1 1k 15 I OUT V V CC 1 DECODER 1 V AGNDS LD LOAD D15 (MSB) D D1 D1 D11 D (LSB) RST DAC REGISTER AGNDF CLR DNC* 19 DNC* WR 4 WR INPUT REGISTER RST 1 DNC* NC 5 D15 D D4 D 4 D 5 D1 D *CONNECTED INTERNALLY. DO NOT CONNECT EXTERNAL CIRCUITRY TO THESE PINS 1 DGND 181 BD 8

9 U W W TI I G DIAGRA t WR WR DATA t DS t DH tlwd LD t LD t CLR CLR 181 TD APPLICATIONS INFORMATION U W U U Description The LTC181 is a 1-bit voltage output DAC with a full parallel 1-bit digital interface. The device can operate from 5V and ±15 supplies and provides both unipolar V to 1V or V to 1V and bipolar ±1V output ranges from a 1V or 1V reference input. Additionally, the power supplies for the LTC181 can go as low as 4.5V and ±4.5V. In this case for a.5v or.5v reference, the output range is V to.5v, V to.5v and ±.5V. The LTC181 has three additional precision resistors on chip for bipolar operation. Refer to the block diagram regarding the following description. The 1-bit DAC consists of a precision R-R ladder for the 1 LSBs. The three MSBs are decoded into seven segments of resistor value R. Each of these segments and the R-R ladder carries an equally weighted current of one eighth of full scale. The feedback resistor R FB and 4-quadrant resistor R OFS have a value of R/4. 4-quadrant resistors R1 and R have a magnitude of R/4. R1 and R together with an external op amp (see Figure ) inverts the reference input voltage and applies it to the 1-bit DAC input REF, in 4-quadrant operation. The REF pin presents a constant input impedance of R/8 in unipolar mode and R/1 in bipolar mode. The LTC181 contains an onboard precision high speed amplifier. This amplifier together with the feedback resistor (R FB ) form a precision current-to-voltage converter for the DAC s current output. The amplifier has very low noise, offset, input bias current and settles in less than µs to.15% for a 1V step. It can sink and source ma (±15V) typically and can drive a pf capacitive load. An added feature of these devices, especially for waveform generation, is a proprietary deglitcher that reduces glitch impulse to below nv-s over the DAC output voltage range. Digital Section The LTC181 has a 1-bit wide full parallel data bus input. The device is double-buffered with two 1-bit registers. The double-buffered feature permits the update of several DACs simultaneously. The input register is loaded directly from a 1-bit microprocessor bus when the WR pin is brought to a logic low level. The second register (DAC register) is updated with the data from the input register when the LD signal is brought to a logic high. Updating the DAC register updates the DAC output with the new data. To make both registers transparent in flowthrough mode, tie WR low and LD high. However, this defeats the deglitcher operation and output glitch impulse may increase. The deglitcher is activated on the rising edge of the LD pin. The 9

10 APPLICATIONS INFORMATION U W U U versatility of the interface also allows the use of the input and DAC registers in a master slave or edge-triggered configuration. This mode of operation occurs when WR and LD are tied together. The asynchronous clear pin resets the LTC181 to zero scale and the LTC181-1 to midscale. CLR resets both the input and DAC registers. These devices also have a power-on reset. Table 1 shows the truth table for the LTC181. Unipolar Mode (-Quadrant Multiplying, = V to V REF ) The LTC181 can be used to provide -quadrant multiplying operation as shown in Figure 1. With a fixed 1V reference, the circuit shown gives a precision unipolar V to 1V output swing. 5V.1µF pf V REF R1 R COM REF R1 R V CC 11 1 R OFS R FB R OFS R FB I OUT 15 15V.1µF LTC181 1-BIT DAC V 1 DATA INPUTS 1 = V TO V REF 5 TO, TO WR LD CLR WR LD CLR DNC* DNC* DNC* NC V DGND AGNDF AGNDS *DO NOT CONNECT 15V.1µF Unipolar Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT VOUT V REF (5,55/5,5) V REF (,78/5,5) = V REF / V REF (1/5,5) V 181 F1 Figure 1. Unipolar Operation (-Quadrant Multiplication) = V to V REF 1

11 APPLICATIONS INFORMATION U W U U Bipolar Mode (4-Quadrant Multiplying, = V REF to V REF ) The LTC181 contains on chip all the 4-quadrant resistors necessary for bipolar operation. 4-quadrant multiplying operation can be achieved with a minimum of external components a capacitor and a single op amp, as shown in Figure. With a fixed 1V reference, the circuit shown gives a precision bipolar 1V to 1V output swing. V REF LT11 5V.1µF pf R1 R COM REF R1 R V CC 11 1 R OFS R FB R OFS R FB I OUT 15 15V.1µF LTC181 1-BIT DAC V 1 DATA INPUTS 1 = V REF TO V REF 5 TO, TO WR LD CLR WR LD CLR DNC* DNC* DNC* NC V DGND AGNDF AGNDS *DO NOT CONNECT 15V.1µF Bipolar Offset Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB ANALOG OUTPUT V REF (,77/,78) V REF (1/,78) V V REF (1/,78) V REF 181 F Figure. Bipolar Operation (4-Quadrant Multiplication) = V REF to V REF 11

12 APPLICATIONS INFORMATION U W U U Precision Voltage Reference Considerations Because of the extremely high accuracy of the 1-bit LTC181, careful thought should be given to the selection of a precision voltage reference. As shown in the section describing the basic operation of the LTC181, the output voltage of the DAC circuit is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 1-bit applications: output voltage initial tolerance, output voltage temperature coefficient (TC), and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1 (±.5%), minimizes the gain error due to the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit s INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 1-bit and higher performance, reference output voltage noise may contribute a dominant share of the system s noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1, produce low output noise in the.1hz to 1Hz region, well below the 1-bit LSB level in 5V or 1V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. AGNDF and AGNDS must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to AGNDF and AGNDS, separate traces should be used to route these pins to the star ground. This minimizes the voltage drop from these pins to ground due to the code dependent current flowing into the ground plane. If the resistance of these separate circuit board traces exceeds 1Ω, the circuit of Figure eliminates this code dependent voltage drop error for high resistance traces. To calculate PC track resistance in squares, divide the length of the PC track by the width and multiply this result by the sheet resistance of copper foil. For 1 oz copper ( 1.4 mils thick), the sheet resistance is.45ω per square. Table. Partial List of LTC Precision References Recommended for Use with the LTC181, with Relevant Specifications INITIAL TEMPERATURE.1Hz to 1Hz REFERENCE TOLERANCE DRIFT NOISE LT119A-5, ±.5% 5ppm/ C 1µV P-P LT119A-1 LT1A-5, ±.5% 5ppm/ C µv P-P LT1A-1 LTA-5, ±.75% 1ppm/ C µv P-P LTA-1 LT179A-.5 ±.5% 1ppm/ C 1µV P-P 1

13 APPLICATIONS INFORMATION U W U U 5V 15V 1V 4 LT1A-1.1µF R1 R COM REF V CC R OFS R FB I OUT pf 1 DATA INPUTS 5 TO, TO WR LD CLR R1 R LTC181 WR LD CLR DNC* DNC* DNC* NC *DO NOT CONNECT R OFS R FB 1-BIT DAC DGND 19 AGNDF ERA V 15 V AGNDS 1 LT11 1.1µF.1µF 15V = V TO 1V 15V ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE ERA8.4 AGNDF 17 AGNDS 1 LT8 Ω Ω 1pF 181 F Figure. Driving AGNDF and AGNDS with a Force/Sense Amplifier 1

14 TYPICAL APPLICATION U 17-Bit Sign Magnitude Output Voltage DAC with Bipolar Zero Error of µv (.9LSB at 17 Bits) 1 15 LTCAC 15V 4 LT1A-1 1 V LT8.1µF.1µF 5V.1µF V 15pF pf SIGN BIT R1 R COM REF V CC R1 R 11 1 R OFS R FB I OUT R OFS R FB V 15.1µF 15V 1 DATA INPUTS LTC181 1-BIT DAC 1 5 TO, TO WR LD CLR WR LD CLR DNC* DNC* DNC* NC DGND AGNDF AGNDS *DO NOT CONNECT V 181 TA.1µF 15V

15 PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. GW Package -Lead Plastic SSOP (Wide.) (LTC DWG # 5-8-) * (..1) (.4.41) ** (.9.99) (.1.1).4.41 (.97.) (.9.94) 8 TYP (.91.15) (.4.4) NOTE: DIMENSIONS ARE IN MILLIMETERS * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.15mm (.") PER SIDE.8 (.15) BSC.4.41 (.1.17) ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.54mm (.1") PER SIDE.17.5 (.5.115) GW SSOP 198 Information furnished by Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15

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