Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in µmax

Transcription

1 ; Rev 2; 1/4 Low-Cost, Voltage-Output, 16-Bit DACs with General Description The serial input, voltage-output, 16-bit digital-to-analog converters (DACs) provide monotonic 16-bit output over temperature without any adjustments. The MAX52/MAX521 operate from a +5V single power supply featuring an internal reference of +2.5V and an internal gain of 2, while the MAX522/ MAX523 operate from a +3V or +3.3V single power supply featuring an internal reference of +1.5V and an internal gain of 2. The DAC output range is typically from to V DD. The feature a hardware reset input (CLR) that, when pulled low, clears the output to zero code hex (MAX521/MAX523) or resets the output to midscale code 8 hex (MAX52/MAX522). The 3-wire serial interface is compatible with SPI /QSPI /MICROWIRE. All devices have a lowpower shutdown mode that reduces the supply current consumption to 1µA. The are available in a space-saving 1-pin µmax package and are guaranteed over the extended temperature range (-4 C to +15 C). Refer to the MAX524 MAX527 data sheet for external reference versions. Features Guaranteed 16-Bit Monotonic Internal Reference 1-Pin 5mm 3mm µmax Package Rail-to-Rail Output Amplifier Single-Supply Operation +5V (MAX52/MAX521) +3V, +3.3V (MAX522/MAX523) Low Power Consumption:.8mA Shutdown Mode Reduces Supply Current to 1µA SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface Power-On-Reset Sets Output to Midscale (MAX52/MAX522) Zero Scale (MAX521/MAX523) Applications Low-Cost VCO/VCXO Frequency Control Industrial Process Control High-Resolution Offset Adjustment TOP VIEW CLR REF AGND V DD Pin Configuration MAX52 MAX523 µmax 1 DGND 9 8 DIN 7 LDAC 6 CS Ordering Information PART TEMP RANGE PIN-PACKAGE MAX52AEUB -4 C to +15 C 1 µmax MAX52BEUB -4 C to +15 C 1 µmax MAX52ACUB C to +7 C 1 µmax MAX521AEUB -4 C to +15 C 1 µmax MAX521BEUB -4 C to +15 C 1 µmax MAX521ACUB C to +7 C 1 µmax MAX522AEUB -4 C to +15 C 1 µmax MAX522BEUB -4 C to +15 C 1 µmax MAX522ACUB C to +7 C 1 µmax MAX523AEUB -4 C to +15 C 1 µmax MAX523BEUB -4 C to +15 C 1 µmax MAX523ACUB C to +7 C 1 µmax SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. µmax is a registered trademark of Maxim Integrated Products, Inc. Selector Guide appears at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS V DD to AGND, DGND...-.3V to +6V AGND to DGND V to +.3V REF, to AGND V to (V DD +.3V) CLR, LDAC,, DIN, CS to DGND...-.3V to (V DD +.3V) Maximum Current into Any Pin...5mA Continuous Power Dissipation (T A = +7 C) 1-Pin µmax (derate 5.6mW/ C above +7 C) mW Operating Temperature Ranges MAX52_CUB... C to +7 C MAX52_EUB C to +15 C Junction Temperature C Storage Temperature Range...-6 C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS MAX52/MAX521 (V DD = +4.75V to +5.25V, f = 1MHz (5% duty cycle), output load = 1kΩ in parallel with 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution N 16 Bits Integral Nonlinearity (Note 2) Differential Nonlinearity (Note 2) Offset Error INL DNL MAX52_AEUB ±1 ±2 MAX52_ACUB ±1 ±2 MAX52_BEUB ±2 ±4 MAX52_A_UB (Note 3) ±1 MAX52_BEUB ( C to +15 C) (Note 3) ±1 MAX52_BEUB (-4 C to C) ±2 Inferred from measurement at 1C hex and FFFF hex LSB LSB ±3 ±25 mv Gain Error GE Within DAC output range (Note 4) ±.1 ±1 %FSR Power-Supply Rejection PSR V DD = 5V ±5%, midscale input ±.6 ±.5 mv/v DYNAMIC PERFORMANCE DAC Output Range (Note 2) Output-Voltage Slew Rate SR.6 V/µs Output Settling Time to V DD To ±1LSB of FS, V STEP =.25 V REF to.75 V REF 25 µs Output Noise DAC code = 84 hex, 1kHz 175 nv/ Hz DAC Glitch Impulse Major carry transition (code 7FFF hex to code 8 hex) V 1 nv s Digital Feedthrough Code = hex; CS = V DD ; LDAC = ;, DIN = or V DD 1 nv s Wake-Up Time Power-Up Time From software shutdown to 9% of output code = FFFF hex, C REF =.1µF From power applied to 9% of output code = FFFF hex 5 µs 1 ms 2

3 ELECTRICAL CHARACTERISTICS MAX52/MAX521 (continued) (V DD = +4.75V to +5.25V, f = 1MHz (5% duty cycle), output load = 1kΩ in parallel with 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL REFERENCE V REF Output Voltage T A = +25 C V V REF Tempco DIGITAL INPUTS (DIN,, CS, CLR, LDAC) T A = C to +7 C ±15 T A = -4 C to +15 C ±2 Input High Voltage V IH 2.4 V Input Low Voltage V IL.8 V Input Hysteresis V HYST 2 mv Input Leakage I IN Digital inputs = or V DD ±1 µa Input Capacitance C IN 15 pf POWER REQUIREMENTS Positive Power Supply V DD V Positive Supply Current I DD All digital inputs at or V DD (Note 5) ma Shutdown Supply Current I SHDN All digital inputs at or V DD 1 1 µa TIMING CHARACTERISTICS Frequency f 1 MHz Clock Period t CP 1 ns Pulse Width High t CH 4 ns Pulse Width Low t CL 4 ns DIN Setup Time t DS 4 ns DIN Hold Time t DH ns CS Fall to Rise Setup Time t CSS 4 ns Rise to CS Rise Hold Time t CSH ns Rise to CS Fall Ignore t CS 1 ns CS Rise to Rise Ignore t CS1 4 ns LDAC Pulse Width t LDAC 4 ns CS Rise to LDAC Low Setup t LDACS 4 ns Fall to CS Fall Ignore t CSOL 1 ns CS Pulse Width Low for Shutdown t CSWL 4 ns CS Pulse Width High t CSWH 1 ns ppm/ C 3

4 ELECTRICAL CHARACTERISTICS MAX522/MAX523 (V DD = +2.7V to +3.6V, f = 1MHz (5% duty cycle), output load = 1kΩ in parallel with 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution N 16 Bits Integral Nonlinearity (Note 2) Differential Nonlinearity (Note 2) Offset Error INL DNL MAX52_AEUB ±1 ±2 MAX52_ACUB ±1 ±2 MAX52_BEUB ±2 ±4 MAX52_A_UB (Note 3) ±1 MAX52_BEUB ( C to +15 C) (Note 3) ±1 MAX52_BEUB (-4 C to C) ±2 Inferred from measurement at 38 hex and FFFF hex LSB LSB ±3 ±25 mv Gain Error GE Within DAC output range (Note 4) ±.1 ±1. %FSR Power-Supply Rejection PSR V DD = 3V ±1%, midscale input ±.6 ±.5 mv/v DYNAMIC PERFORMANCE DAC Output Range (Note 2) Voltage-Output Slew Rate SR.6 V/µs Output Settling Time to V DD To ±1 LSB of FS, V STEP =.25 V REF to.75 V REF 25 µs Output Noise Code = 84 hex, 1kHz 175 nv/ Hz V Reference Feedthrough Code = hex at 1kHz, V REF = 1V P-P 1 mv P-P DAC Glitch Impulse Digital Feedthrough Wake-Up Time Power-Up Time Major carry transition (code 7FFF hex to code 8 hex) Code = hex; CS = V DD ; LDAC = ;, DIN = or V DD levels From software shutdown to 9% of output code = FFFF hex From power applied to 9% of output code = FFFF hex 1 nv s 1 nv s 5 µs 1 ms 4

5 ELECTRICAL CHARACTERISTICS MAX522/MAX523 (continued) (V DD = +2.7V to +3.6V, f = 1MHz (5% duty cycle), output load = 1kΩ in parallel with 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL REFERENCE V REF Output Voltage T A = +25 C V V REF Tempco DIGITAL INPUTS (DIN,, CS, CLR, LDAC) T A = C to +7 C ±15 T A = -4 C to +15 C ±2 Input High Voltage V IH 2.1 V Input Low Voltage V IL.6 V Input Hysteresis V HYST 2 mv Input Leakage I IN Digital inputs = or V DD ±1 µa Input Capacitance C IN 15 pf POWER REQUIREMENTS Positive Power Supply V DD V Positive Supply Current I DD All digital inputs at or V DD (Note 5) ma Shutdown Supply Current I SHDN All digital inputs at or V DD 1 1 µa TIMING CHARACTERISTICS Frequency f 1 MHz Clock Period t CP 1 ns Pulse Width High t CH 4 ns Pulse Width Low t CL 4 ns DIN Setup Time t DS 4 ns DIN Hold Time t DH ns CS Fall to Rise Setup Time t CSS 4 ns Rise to CS Rise Hold Time t CSH ns Rise to CS Fall Ignore t CS 1 ns CS Rise to Rise Ignore t CS1 4 ns LDAC Pulse Width t LDAC 4 ns CS Rise to LDAC Low Setup t LDACS 4 ns Fall to CS Fall Ignore t CSOL 1 ns C S P ul se W i d th Low for S hutd ow n t CSWL 4 ns CS Pulse Width High t CSWH 1 ns ppm/ C Note 1: Static performance tested at V DD = +5.V (MAX52/MAX521) and at V DD = +3.V (MAX522/MAX523). Note 2: INL and DNL are guaranteed for outputs between.5v to (V DD -.5V). Note 3: Guaranteed monotonic. Note 4: V REF = 2.5V (MAX52/MAX521) and V REF = 1.5V (MAX522/MAX523). Note 5: R L =, digital inputs are at V DD or DGND. 5

6 (V DD = +5V, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) MAX52 toc1 INL (LSB) INTEGRAL NONLINEARITY vs. CODE 1, 2, 3, 4, 5, 6, 7, DAC CODE Typical Operating Characteristics MAX52 toc2 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. CODE -1. 1, 2, 3, 4, 5, 6, 7, DAC CODE MAX52 toc3 GAIN ERROR (%FSR) GAIN ERROR vs. TEMPERATURE TEMPERATURE ( C) MAX52 toc4 OFFSET ERROR (mv) OFFSET ERROR vs. TEMPERATURE TEMPERATURE ( C) MAX52 toc5 HALF-SCALE PUT SETTLING TIME (CODE FROM 4H TO CH) 4µs/div MAX52 toc6a LARGE SIGNAL (1V/div) SMALL SIGNAL (1mV/div) R LOAD = 1kΩ C LOAD = 25pF 1V/div 1mV/div HALF-SCALE PUT SETTLING TIME (CODE FROM CH TO 4H) R LOAD = 1kΩ C LOAD = 25pF 4µs/div MAX52 toc6b LARGE SIGNAL (1V/div) SMALL SIGNAL (1mV/div) 1V/div 1mV/div VOLTAGE NOISE DENSITY (nv/ Hz) PUT NOISE DENSITY vs. FREQUENCY DAC CODE = 84 HEX 1 1k 1k 1k FREQUENCY (Hz) MAX52 toc7 6

7 Typical Operating Characteristics (continued) (V DD = +5V, T A = +25 C, unless otherwise noted.) PUT VOLTAGE (V) SOURCE-CURRENT CAPABILITY CODE = FFFF HEX CODE = C HEX CODE = 8 HEX SOURCE CURRENT (ma) MAX52 toc8 PUT VOLTAGE (V) SINK-CURRENT CAPABILITY CODE = 4 HEX CODE = HEX SINK CURRENT (ma) MAX52 toc9 MAJOR-CARRY PUT GLITCH (CODE FROM 8H TO 7FFFH) 1µs/div MAX52 toc1 (AC-COUPLED, 5mV/div) MAJOR-CARRY PUT GLITCH (CODE FROM 7FFFH TO 8H) MAX52 toc11 (AC-COUPLED, 5mV/div) SHUTDOWN CURRENT (µa) SHUTDOWN CURRENT vs. TEMPERATURE MAX52 toc µs/div TEMPERATURE ( C) 7

8 PIN NAME FUNCTION 1 CLR Detailed Description The serial 16-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices offer full 16-bit performance with less than ±2LSB integral linearity error and less than ±1LSB differential linearity error, thus ensuring monotonic performance. Serial data transfer minimizes the number of package pins required. The MAX52 MAX523 include control-logic circuitry, a 16-bit data-in shift register, and a DAC register. In addition, these devices employ a precision-bandgap reference and trimmed internal resistors to produce a gain of 2V/V, maximizing the output voltage swing. The output is buffered and the fullscale output voltage is 2 V REF. The feature a hardware reset input (CLR) that, when pulled low, clears the DAC output to zero code H (MAX521/MAX523) or resets the DAC output to midscale code 8 hex (MAX52/ MAX522). For normal operation, connect CLR to V DD. Internal Reference The MAX52/MAX521 (+5V supply) include an internal reference of 2.5V while the MAX522/MAX523 (+3V supply) include an internal reference of 1.5V. The DAC output range is from to 2 V REF. Do not drive external circuitry from this reference. To improve DAC output noise performance, bypass with a low leakage.1µf minimum capacitor to AGND. Pin Description Reset DAC Active-Low Input. Pull CLR low to reset the DAC output to midscale output (8 hex) for MAX52/MAX522 and to zero-scale output ( hex) for MAX521/MAX523. For normal operation, connect CLR to V DD. 2 REF Reference Voltage Output. Provides a +2.5V (MAX52/MAX521) or +1.5V (MAX522/MAX523) nominal output. For improved noise performance, bypass with a minimum.1µf capacitor to AGND. 3 AGND Analog Ground Positive Supply Voltage. Bypass V 4 V DD to AGND with a 1µF capacitor in parallel with a.1µf DD capacitor. 5 DAC Output Voltage 6 CS Active-Low Chip-Select Input 7 LDAC Load DAC Input 8 DIN Serial Data Input 9 Serial Clock Input. Duty cycle must be 4% to 6%. 1 DGND Digital Ground CLR CS DIN LDAC BANDGAP REF CONTROL LOGIC REF V DD 16-BIT DAC 16-BIT DATA LATCH SERIAL INPUT REGISTER DGND MAX52 MAX523 Figure 1. Simplified Functional Diagram AGND Digital Interface The digital interface is a standard 3-wire connection compatible with SPI/QSPI/ MICROWIRE and most DSP interfaces. All of the digital input pins (CS,, DIN, CLR, and LDAC) are TTL compatible. can accept clock frequencies as high as 1MHz for a +5V supply and 1MHz for a +3V or +3.3V supply. One of two methods can be used when interfacing and updating the. The first requires three digital inputs: CS, DIN, and (Figure 2). The active-low chip-select input (CS) enables the serial 8

9 t CP t CH t CL t CSS t CS DS t CS t CSWH DIN NOTE: LDAC IS LOGIC LOW. Figure 2. 3-Wire Interface Timing Diagram D15 t DH D14 D t CSH t CS1 data loading at the data input (DIN). Pull CS low and clock in each bit of the 16-bit digital word on the rising edge of the serial clock (). Two 8-bit bytes can be used, and do not require any additional time between them. Pulling CS high after loading the 16-bit word transfers that code into the DAC register and then updates the output. If CS is not kept low during the entire loading of the 16-bit word, data is corrupted. In this case, a new 16-bit word must be loaded. LDAC must be kept low at all times for the above instructions. An alternate method of interfacing and updating the can be done with a fourth digital input, the active-low load DAC (LDAC). LDAC allows the output to update asynchronously after CS goes high. It is useful when updating multiple MAX52 MAX523s synchronously when sharing a single LDAC and CS line. LDAC must be kept high at all times during the data-loading sequence and must only be asserted when CS is high. Asserting LDAC when CS is low can cause corrupted data. To operate the using LDAC, pull LDAC high, pull CS low, load the 16-bit word as described in the previous paragraph, and pull CS high again. Following these commands, the DAC output only updates when LDAC is asserted low (Figure 3). Shutdown Mode The low-power shutdown mode reduces supply current to typically 1µA and a maximum of 1µA. Shutdown mode is not activated through command words, as is common among D/A converters. These devices require careful manipulation of CS and (Figure 4). Shutting Down To shut down the, change the state of (either a high to low or low to high transition can be used) and pulse two falling CS edges. In order to keep the device in shutdown mode, must not change state. must remain in the state it is in after the two CS pulses. Waking Up There are two methods to wake up the MAX52 MAX523. Pulse one falling CS edge or transition. It takes 5µs typically from the CS falling edge or transition for the DAC to return to normal operation. Power-On Reset The have a power-on reset circuit to set the DAC s output to a known state when V DD is first applied. The MAX52/MAX522 reset to midscale (code 8 hex) upon power-up. The MAX521/MAX523 reset to zero scale (code hex) upon power-up. This ensures that unwanted output voltages do not occur immediately following a system power-up, such as a loss of power. It is required to apply VDD first before any other inputs (DIN,, CLR, LDAC, and CS). 9

10 CS DIN LDAC t CSWH t CS t CH t CP t CL t CSS t DS D15 t DH D14 D t CSH t CS1 t LDACS t LDAC Figure 3. 4-Wire Interface Timing Diagram t CSL SHUTDOWN WAKE-UP CS t CSWL t CSWH A. WAKING UP USING A THIRD FALLING EDGE ON CS. t CSL SHUTDOWN WAKE-UP CS t CSWL t CSWH B. WAKING UP USING A TRANSITION ON. Figure 4. Shutdown Timing Applications Information Power-Supply and Bypassing Considerations Bypass the power supply with a 1µF capacitor in parallel with a.1µf capacitor to AGND. Minimize lead lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. Output Buffer The include low-offset, low-noise buffers enabling the output to source 15mA or sink 5mA. The output buffer operates at a slew rate of.6v/µs. With a 1/4 FS to 3/4 FS output transition, the buffer output typically settles to 1 LSB in less than 25µs. The output buffers provide a low.2ω typical output impedance. The MAX52 MAX523 buffer amplifiers typically produce 175nV/ Hz noise at 1kHz. 1

11 MC68XXXX PCS MOSI CLR CS DIN LDAC DGND V DD 1µF.1µF MAX52 MAX523 AGND REF +5V MAX4-5V BIPOLAR (±V REF ) Figure 5. Typical Operating Circuit Bipolar Output Table 1. Bipolar Code Table DAC LATCH CONTENTS MSB LSB ANALOG PUT, V V REF (32,767 / 32,768) 1 1 +V REF (1 / 32,768) 1 V V REF (1 / 32,768) -V REF (32,768 / 32,768) Bipolar Configuration The are designed for unipolar operation, but can be used in bipolar applications with an external amplifier and resistors. Figure 5 shows the configured for bipolar operation. The op amp is set for unity gain. Table 1 lists the offset binary code for this circuit. The output voltage range is ±V REF. Layout Considerations Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND pins together at the IC. The best ground connection is achieved by connecting the DAC s DGND and AGND together, and then connecting that point to the system analog ground plane. If the DAC s DGND is connected to the system digital ground, digital noise can get through the DAC s analog portion. Chip Information TRANSISTOR COUNT: 8764 PROCESS: BiCMOS 11

12 PART INTEGRAL NONLINEARITY (LSB, MAX) SUPPLY VOLTAGE RANGE (V) REFERENCE INPUT RANGE (V) Selector Guide POWER-ON-RESET VALUE MAX52AEUB to Midscale MAX52ACUB to Midscale MAX52BEUB to Midscale MAX521AEUB to Zero MAX521ACUB to Zero MAX521BEUB to Zero MAX522AEUB to Midscale MAX522ACUB to Midscale MAX522BEUB to Midscale MAX523AEUB to Zero MAX523ACUB to Zero MAX523BEUB to Zero 12

13 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to e.5±.1.6±.1 TOP VIEW 4X S H BOTTOM VIEW 1 1 DIM A A1 MIN -.2 MAX.43.6 MIN -.5 MAX A D D2 E1 E2 H L L1 b e c S α INCHES MILLIMETERS REF.94 REF BSC.5 BSC REF.498 REF 6 6 1LUMAX.EPS D2 E2 GAGE PLANE A2 A c D1 b A1 α E1 L L1 FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE LINE, 1L umax/usop APPROVAL DOCUMENT CONTROL NO. REV I 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.