EEPROM-Programmable TFT VCOM Calibrator

Transcription

1 Rev 3; 8/6 EVALUATION KIT AVAILABLE EEPROM-Programmable TFT Calibrator General Description The is a programmable -adjustment solution for thin-film transistor (TFT) liquid-crystal displays (LCDs). The simplifies the labor-intensive -adjustment process and replaces mechanical potentiometers, which significantly reduces labor costs, increases reliability, and enables automation. The attaches to an external resistive voltagedivider and sinks a programmable current to set the voltage level. An internal 7-bit digital-to-analog converter (DAC) controls the sink current. The DAC is ratiometric relative to and is guaranteed to be monotonic over all operating conditions. This calibrator IC includes an EEPROM to store the desired voltage level. The EEPROM can be programmed repeatedly, giving TFT LCD manufacturers the flexibility to calibrate the display panel as many times as the manufacturing process requires. The IC features a single-wire interface between the LCD panel and the programming circuit. The singlewire interface delivers both programming power and DAC-adjustment commands to minimize changes to panel connectors and production equipment. The is available in an 8-pin 3mm x 3mm TDFN package. A complete evaluation kit is available to simplify evaluation and production development. LCD Panels Notebook Computers Monitors LCD TVs Applications Features 7-Bit Adjustable Sink-Current Output Resistor-Adjustable Full-Scale Range Guaranteed Monotonic Output Over Operating Range Single-Wire Adjustment and Programming* EEPROM Stores Setting Interface Enable/Disable Control (CE) 2.6V to 3.6V Logic Supply-Voltage Operating Range (VDD) 4.5V to 2V Analog Supply-Voltage Range (V ) VDD UVLO Protection 8-Pin 3mm x 3mm TDFN (.8mm max) Ordering Information PART TEMP RANGE PIN-PACKAGE ETA -4 C to +85 C 8 TDFN 3mm x 3mm ETA+ -4 C to +85 C 8 TDFN 3mm x 3mm +Denotes lead-free package. Typical Operating Circuit Pin Configuration TOP VIEW CE OUT N.C. GND TDFN SET CE GND OUT SET R2 A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. R SET *Patent Pending. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS, SET, CE to GND...-.3V to +4V OUT to GND...-.3V to +14V to GND...-.3V to +24V to GND...-.3V to +16V Continuous Power Dissipation (T A = +7 C)... 8-Pin Thin QFN 3mm x 3mm (derate 24.4mW/ C above +7 C) mW Operating Temperature Range...-4 C to +85 C Junction Temperature C Storage Temperature Range C to +16 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, = 3V, V = 1V, V OUT = 5V, R SET = 3.1kΩ, T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINK-CURRENT ADJUSTMENT SET Voltage Resolution 7 Bits SET Differential Nonlinearity Guaranteed monotonic LSB SET Zero-Scale Error LSB SET Full-Scale Error LSB SET Current I SET 12 µa To GND, V = 2V 1 2 SET External Resistance (Note 2) R SET To GND, V = 4.5V V SET / V Voltage Ratio DAC full scale.5 V/V kω V SET / V Factory-Set Voltage Ratio V/V SUPPLY Supply Range V CE = Supply Current I DD CE = GND 12 2 Power-On Reset Threshold Rising edge Falling edge Power-On Reset Hysteresis 1 mv CONTROL AND PROGRAMMING CE Input Low Voltage 2.6V < < 3.6V.4 V CE Input High Voltage 2.6V < < 3.6V 1.6 V CE Startup Time (Note 3) 1 ms High Voltage 2.6V < < 3.6V.7 x.82 x V Float Voltage 2.6V < < 3.6V.4 x.62 x V Low Voltage 2.6V < < 3.6V.2 x.32 x V Rejected Pulse Width 2 µs Minimum Pulse Width 2 µs Minimum Time Between Pulses Input Current = GND -1 = 1 2 µa V 1 µs µa

3 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, = 3V, V = 1V, V OUT = 5V, R SET = 3.1kΩ, T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Program Voltage V PP (Note 3) V OUTPUT VOLTAGE OUT Leakage Current = 2.1V 1 na OUT Settling Time To ±.5 LSB error band 2 µs V OUT Voltage Range V OUT V SET +.5V 13 V SUPPLY V Supply Range V V = 2.1V, V = 2V.4 Operating Current I V = 2V 1 2 µa ELECTRICAL CHARACTERISTICS ( = 3V, V = 1V, V OUT = 5V, R SET = 3.1kΩ, T A = -4 C to +85 C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINK-CURRENT ADJUSTMENT SET Differential Nonlinearity Guaranteed monotonic LSB SET Zero-Scale Error LSB SET Full-Scale Error LSB SET Current I SET 12 µa To GND, V = 2V 1 2 SET External Resistance (Note 2) R SET To GND, V = 4.5V SUPPLY Supply Range V CE = 55 Supply Current I DD CE = GND 2 Power-On Reset Threshold CONTROL AND PROGRAMMING Rising edge Falling edge CE Input Low Voltage 2.6V < < 3.6V.4 V CE Input High Voltage 2.6V < < 3.6V 1.6 V SUPPLY V Supply Range V V Operating Current I V = 2V 2 µa Note 1: Limits are 1% production tested at T A = +25 C. Limits over the operating temperature range are guaranteed through correlation using standard quality control (SQC) methods. Note 2: SET external resistor range is verified at DAC full scale. Note 3: Guaranteed by design. Not production tested. kω µa V 3

4 Typical Operating Characteristics (Circuit of Figure 1, = 3V, V = 1V, V OUT = 5V, R SET = 24.9kΩ, T A = +25 C, DAC half scale, unless otherwise noted.) VDD SUPPLY CURRENT (µa) CE = = 3V -2 SUPPLY CURRENT vs. TEMPERATURE 2 4 TEMPERATURE ( C) 6 8 toc1 VDD SUPPLY CURRENT (µa) SUPPLY CURRENT vs. CE = FALLING RISING (V) toc2 IOUT (µa) 1, I OUT vs. R SET V = 2V V = 4.5V = V OUT = 3V R SET (kω) toc3 IOUT SINK-CURRENT ERROR (LSB) I OUT SINK-CURRENT ERROR vs. toc4 IOUT SINK-CURRENT ERROR (LSB) I OUT SINK-CURRENT ERROR vs. V toc (V) V (V) IOUT SINK-CURRENT ERROR (LSB) I OUT SINK-CURRENT ERROR vs. V OUT toc6 IOUT SINK-CURRENT ERROR (LSB) I OUT SINK-CURRENT ERROR vs. TEMPERATURE toc V OUT (V) TEMPERATURE ( C) 6 8 4

5 Typical Operating Characteristics (continued) (Circuit of Figure 1, = 3V, V = 1V, V OUT = 5V, R SET = 24.9kΩ, T A = +25 C, DAC half scale, unless otherwise noted.) TOTAL UNADJUSTED ERROR (LSB) TOTAL UNADJUSTED ERROR vs. DAC SETTING R SET = 25kΩ R SET = 1kΩ DAC SETTING toc8 INTEGRAL NON-LINEARITY (LSB) INTEGRAL NONLINEARITY vs. DAC SETTING R SET = 1kΩ R SET = 25kΩ DAC SETTING toc9 DIFFERENTIAL NON-LINEARITY (LSB) DIFFERENTIAL NONLINEARITY vs. DAC SETTING DAC SETTING toc1 POWER-UP RESPONSE toc11 C OUT = 1pF V 1V/div V OUT 1V/div POWER-UP RESPONSE toc12 C OUT = 1pF 5V V OUT 4V 1V V 4µs/div 2V/div 4µs/div 2V/div SINGLE LSB STEP-UP RESPONSE toc13 C OUT = 1pF SINGLE LSB STEP-DOWN RESPONSE toc14 C OUT = 1pF V OUT 5mV/div V OUT 5mV/div 2V V 2V V 4µs/div 4µs/div 5

6 PIN NAME FUNCTION 1 OUT Pin Description Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider between and GND that sets the voltage. I OUT lowers the divider voltage by an adjustable amount. See the SET pin description. 2 High-Voltage Analog Supply. Connects to the panel source-driver supply rail. 3 N.C. No Connect. Not internally connected. 4 GND Ground 5 Supply Input. +2.6V to +3.6V input range. 6 7 CE 8 SET Adjustment and EEPROM Programming Control. sets the internal DAC code and programs the EEPROM. A pulse-control method is used to adjust the level. See the Adjustment () section. To program the DAC setting into the EEPROM as the power-on default, drive to the EEPROM programming voltage using the correct timing and voltage ramp rates. See the EEPROM Programming () section. Control Interface Enable. Connect CE to to enable the input. Connect CE to GND to disable the input and reduce the supply current. Full-Scale Sink-Current Adjustment Input. Connect a resistor, R SET, from SET to GND to set the full-scale adjustable sink current. The full-scale adjustable sink current is equal to: V I OUT is equal to the current through R SET. 2 R SET Detailed Description The is a solid-state alternative to mechanical potentiometers used for adjusting the LCD backplane voltage () in TFT LCD displays. The attaches to an external resistive voltage-divider and sinks a programmable current (I OUT ), which sets the level (Figure 1). An internal 7-bit DAC controls the sink current and allows the user to increase or decrease the level (Figure 2). The DAC is ratiometric relative to and is monotonic over all operating conditions. The user can store the DAC setting in an internal EEPROM. On power-up, the EEPROM presets the DAC to the last stored setting. The single-wire interface between the LCD panel and the programming circuit adjusts the DAC, programs the EEPROM, and provides programming power. The resistive voltage-divider and the supply set the maximum value of. The sinks current from the voltage-divider to reduce the level. The external resistor R SET sets the full-scale sink current and the minimum value of. CE 3V GND OUT SET 1V R SET 25kΩ Figure 1. Standard Application Circuit 2kΩ R2 245kΩ 5V 6

7 CE CONTROL INTERFACE 7 DAC 19R R OUT R2 7 EEPROM SET R SET GND Figure 2. Simplified Functional Diagram Setting the Adjustment Range (R SET ) The external resistive voltage-divider sets the maximum value of the adjustment range. R SET sets the full-scale sink current, I OUT, which determines the minimum value of the adjustment range. Large R SET values increase resolution but decrease the adjustment range. Calculate, R2, and R SET using the following procedure: 1) Choose the maximum level (V MAX ), the minimum level (V MIN ), and the supply voltage (V ). 2) Calculate the / R2 ratio: 3) Calculate the / R SET ratio: RSET R2 V -1 VMAX VMAX -VMIN VMAX ( ) 2 4) Choose R SET according to the limits shown in the Electrical Characteristics section and calculate the values for and R2. 5) The resulting resolution is: A complete design example is given below: 1) V MAX = 5V, V MIN = 3V, V = 1V 1 2 ) R 1 R 2 5-1=1 3) Re solution ( 5-3 ) = 2 = 8 R SET 5 ( VMAX -VMIN ) = 127 4) If R SET = 24.9kΩ, then = 2kΩ and R2 = 2kΩ 5) Resolution = 15.75mV 7

8 MECHANICAL POTENTIOMETER Ra EQUIVALENT CIRCUIT Rb Rc OUT SET R2 = Ra R2 = Rb + Rc Ra (Rb + Rc) R SET = 2 Rb R SET Figure 3. Replacement of Mechanical/Potentiometer Circuit MECHANICAL POTENTIOMETER EQUIVALENT CIRCUIT Rd Re Rf OUT SET R2 = Rd R2 = Rf Rd (Rd + Re + Rf) R SET = 2 Re R SET Figure 4. Replacement of Mechanical/Potentiometer Circuit Translating Existing Potentiometer Circuits Existing adjustment circuits using conventional mechanical potentiometers can be translated into circuits. Figures 3 and 4 show two common adjustment circuits and their equivalent circuits. Interface Enable/Disable (CE) The control interface can be disabled to reduce the supply current. Connect CE to GND to reduce the typical supply current from 32µA to 12µA. Connect CE to to enable the control interface. 8

9 PROGRAMMING CIRCUIT R CE CE GND The programming circuit in Figure 5 drives CE high to enable the input when it is connected. When the programming circuit is not connected, CE is pulled low through resistor R CE, which disables the input. The input is relatively immune to noise and brief voltage transients. It can be safely left continuously enabled if higher supply current is acceptable. Adjustment () Pulse low for more than 2µs to increment the DAC setting, which increases the OUT sink current and lowers the level by 1 least-significant bit (LSB) (Figure 6). Similarly, pulse high for more than 2µs to decrement the DAC setting, which decreases the OUT sink current and increases the level by 1 LSB. Figure 5. Optional Circuit to Drive CE >1ms >2µs >2µs >2µs >1µs >2µs <2µs <2µs HIGH /2 LOW FIRST COUNT IGNORED UP DOWN SHORT COUNTS IGNORED CE / ENABLED DAC SETTING UNDEFINED Figure 6. Adjustment 9

10 To avoid unintentional adjustment, the is guaranteed to reject pulses shorter than 2µs. In addition, to avoid the possibility of a single false pulse caused by power-up sequencing between and, the very first pulse is ignored. VOLTAGE V PP / 2 T1 T2 T3 T4 Figure 7. EEPROM Programming TIME EEPROM Programming () To program the EEPROM, apply the EEPROM programming waveform through the interface (Figure 7). The control interface delivers programming power and DAC adjustment commands on the same wire. This single-wire approach minimizes the number of connections from the programming circuit to the LCD panel. To apply the EEPROM programming waveform, carefully ramp from midscale ( / 2) to the programming voltage, V PP, in 7.5ms as shown in Figure 7. If the ramp is generated digitally, use at least 45 steps to achieve the required 32mV ramp resolution. During the ramp time, adjustment is disabled and the EEPROM cells are biased in preparation for programming. After reaching V PP, hold at V PP for 1ms. During the EFPROM program time, the EEPROM stores the DAC setting. Next, drive to ground in less than 1ms and hold for at least 2µs. Finally, drive to / 2 to complete the write cycle. The EEPROM is factory set to half scale. Follow the EEPROM Programming Specifications in Table 1 to guarantee reliable EEPROM programming. Violating the specifications can damage the EEPROM or affect data retention. A complete evaluation kit is available to simplify evaluation and production development. Table 1. EEPROM Programming Specifications PARAMETER SYMBOL MIN TYP MAX UNITS Programming Voltage V PP V Programming Ramp T ms EEPROM Program Time T ms V PP Fall Time T3 1 1 µs Done Hold Time T4 2 µs 1

11 USER INTERFACE µc DAC TO 2.5V REF TO 15.5V V PP VERIFY Figure 8. Conceptual Programming Circuit Applications Information The adjustment and the EEPROM programming must be performed with an external programming circuit. Refer to the evaluation kit for a complete programming circuit solution. Use a circuit similar to the conceptual diagram shown in Figure 8 to drive. The accuracy of the programming voltage (V PP ) is critical for proper data retention. The use of a comparator is recommended to verify the correct programming voltage has been reached. A complete design example of a programming circuit is presented in the evaluation kit data sheet. Electrostatic Discharge (, CE) Often, and CE are exposed at the panel connector and are therefore subject to electrostatic discharge (ESD). Resistor-capacitor (RC) filters can be employed at these inputs to improve their ESD performance (Figure 9). DURING PROGRAMMING, FLOATING AFTER PROGRAMING FLOATING AFTER PROGRAMMING 1kΩ R CE 1kΩ 1kΩ.1µF.1µF Figure 9. Improved EOS/Surge Performance CE GND If the CE panel connector is to be left floating after programming, be sure to include a resistor to ground (R CE ) to ensure a valid logic-low on CE. The time constant for a CE filter is not critical but the driving resistor must have a much lower resistance than RCE to properly drive CE. If a filter is used at the panel connector, its RC timeconstant should be short enough to avoid interfering with pulses or EEPROM programming timing. A time constant less than 2µs does not interfere with EEP- ROM programming. To avoid interfering with pulses, make the time constant small compared to the pulsewidth used. Leakage Current () The pin is internally biased to / 2, but it is sensitive to leakage currents above.1µa. When is not driven, avoid leakage currents around the pin. Otherwise, reinforce the / 2 set point with an external resistive voltage-divider. Layout Information Use the following guidelines for good layout: Place the buffer and the /R2 voltagedivider close to the OUT pin (Figure 1). Keep the buffer and the /R2 voltage-divider close to each other. Place R SET close to SET. In noisy environments, bypass capacitors may be desired on and/or V. Keep any bypass capacitors close to the IC with short connections to the pins. Refer to the evaluation kit for an example of proper board layout. 11

12 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to 6, 8, &1L, DFN THIN.EPS PACKAGE OUTLINE, 6,8,1 & 14L, TDFN, EXPOSED PAD, 3x3x.8 mm H

13 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to COMMON DIMENSIONS SYMBOL MIN. MAX. A.7.8 D E A1..5 L.2.4 k.25 MIN. A2.2 REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e T ±.1 2.3±.1.95 BSC MO229 / WEEA.4± REF T ±.1 2.3±.1.95 BSC MO229 / WEEA.4± REF T833-1 T133-1 T ±.1 1.5±.1 2.3±.1 1.7±.1 2.3±.1.65 BSC.3± REF 2.3±.1.5 BSC MO229 / WEED-3.25±.5 2. REF 2.3±.1.5 BSC MO229 / WEED-3.25±.5 2. REF.4 BSC MO229 / WEEC T ±.1 2.3±.1.65 BSC MO229 / WEEC.3± REF T ±.1 2.3±.1.65 BSC MO229 / WEEC.3± REF T ±.1 T ±.1 2.3± ± REF.4 BSC ± REF PACKAGE OUTLINE, 6,8,1 & 14L, TDFN, EXPOSED PAD, 3x3x.8 mm -DRAWING NOT TO SCALE H 2 2 Revision History Pages changes at Rev 3: 1, 11, 12 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 13 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.