I 2 C BUS. Maxim Integrated Products 1

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1 9-3624; Rev ; 3/5 EVLUTION KIT VILBLE EEPROM-Programmable TFT General escription The is an I 2 C-programmable -adjustment solution for thin-film transistor (TFT) liquid-crystal displays (LCs) The simplifies the labor-intensive -adjustment process and replaces mechanical potentiometers, which significantly reduces labor costs, increases reliability, and enables automation The attaches to an external resistive voltagedivider and sinks a programmable current to set the voltage level n internal 7-bit digital-to-analog converter (C) controls the sink current The C is ratiometric relative to and is guaranteed to be monotonic over all operating conditions This calibrator IC includes an EEPROM to store the desired voltage level The EEPROM can be programmed repeatedly, giving TFT LC manufacturers the flexibility to calibrate the display panel as many times as the manufacturing process requires The features a 2-wire I 2 C interface for Cadjustment commands and EEPROM programming The interface utilizes the existing I 2 C bus on the LC panel connector so no additional panel connector pins are required The MX52 is a similar product with a -wire interface and is recommended for applications with no existing I 2 C interface The is available in an 8-pin µmx package complete evaluation kit is available to simplify evaluation and production development Features 7-Bit djustable Sink-Current Output Resistor-djustable, Full-Scale Range Guaranteed Monotonic Output Over Operating Range 2-Wire I 2 C Interface EEPROM Stores Setting 45V to 2V nalog Supply Voltage Range (V) 6µ (max) Supply Current 6V to 28V EEPROM Programming Supply Voltage Range (VHV) <µ HV Supply Current (Not in Program Mode) 8-Pin µmx Ordering Information PRT TEMP RNGE PIN-PCKGE EU -4 o C to +85 o C 8 µmx EU+ -4 o C to +85 o C 8 µmx +enotes lead-free package pplications Typical Operating Circuit LC Panels Notebook Computers +33V VGON isplay Products LC TVs V HV µmx is a registered trademark of Maxim Integrated Products, Inc Pin Configuration I 2 C BUS S SCL OUT R TOP VIEW GN SET R2 OUT 8 SET V SCL S GN 4 5 HV μmx Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/allas irect! at , or visit Maxim s website at wwwmaxim-iccom

2 BSOLUTE MXIMUM RTINGS V, SET, SCL, S to GN-3V to +6V OUT to GN -3V to +8V, HV to GN -3V to +3V Continuous Power issipation 8-Pin µmx (derate 45mW/ C above +7 C) 362mW Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICL CHRCTERISTICS Operating Temperature Range -4 C to +85 C Junction Temperature+5 C Storage Temperature Range -65 C to +6 C Lead Temperature (soldering, s) +3 C (V = 5V, V HV = 2V, V OUT = 675V, = 3kΩ, T = C to +85 C, unless otherwise noted) (Figure ) PRMETER SYMBOL CONITIONS MIN TYP MX UNITS SINK CURRENT JUSTMENT SET Voltage Resolution 7 Bits SET ifferential Nonlinearity Monotonic overtemperature - + LSB SET Zero-Scale Error LSB SET Full-Scale Error LSB SET Current I SET 2 µ SET External Resistance (Note ) V SET /V Voltage Ratio 2-WIRE INTERFCE To GN, V = 2V 2 To GN, V = 45V C full scale 5 Factory set Logic-Input Low Voltage V IL S, SCL 8 V Logic-Input High Voltage V IH S, SCL 2 V Logic-Output Low Sink Current S forced to 4V 6 m Logic-Input Current V S = +33V or GN, V SCL = +33V or GN 2 kω V/V - + µ S and SCL Input Capacitance S, SCL 5 pf SCL Frequency f CLK C khz SCL High Time t CLH 4 ns SCL Low Time t CLL 47 ns S and SCL Rise Time t R (Note 2) ns S and SCL Fall Time t F (Note 2) 3 ns STRT Condition Hold Time t HSTT % of S to 9% of SCL 4 ns STRT Condition Setup Time t SUSTT 47 ns ata Input Hold Time t HT ns ata Input Setup Time t SUT 25 ns STOP Condition Setup Time t SUSTP 4 ns Bus Free Time t BF 47 ns Input Filter Spike Suppression t SP S, SCL (Note 2) µs V REGULTOR V Output Voltage V 45V < V < 2V, I V = V V Power-On Reset Threshold Rising edge, mv hysteresis 3 V

3 ELECTRICL CHRCTERISTICS (continued) (V = 5V, V HV = 2V, V OUT = 675V, = 3kΩ, T = C to +85 C, unless otherwise noted) (Figure ) SUPPLY PRMETER SYMBOL CONITIONS MIN TYP MX UNITS Supply Range V 45 2 V Operating Current I V = 2V 25 6 µ HV SUPPLY HV Input Voltage Range V HV 6 28 V HV Power-On Reset Threshold Rising edge, 6mV hysteresis 56 6 V Not in program mode (Note 3) HV Input Bias Current I HV Program mode (Note 3) 5 3 uring program (Note 4) 6 µ OUTPUT VOLTGE OUT Leakage Current ± n OUT Settling Time To ±5 LSB error band 2 µs OUT Voltage Range V OUT V SET + 5V 3 V ELECTRICL CHRCTERISTICS (V = 5V, V HV = 2V, V OUT = 675V, = 3kΩ, T = -4 C to +85 C, unless otherwise noted) (Figure ) (Note 5) PRMETER SYMBOL CONITIONS MIN TYP MX UNITS SINK CURRENT JUSTMENT SET ifferential Nonlinearity Monotonic overtemperature - + LSB SET Zero-Scale Error - +2 LSB SET Full-Scale Error LSB SET Current I SET 2 µ SET External Resistance (Note ) 2-WIRE INTERFCE To GN, V = 2V 2 To GN, V = 45V Logic-Input Low Voltage V IL S, SCL 8 V Logic-Input High Voltage V IH S, SCL 2 V Logic-Output Low Sink Current S forced to 4V 6 m Logic-Input Current I LI V S = +33V or GN, V SCL = +33V or GN kω - + µ SCL Frequency f CLK C khz SCL High Time t CLH 4 ns SCL Low Time t CLL 47 ns S and SCL Rise Time t R (Note 2) ns S and SCL Fall Time t F (Note 2) 3 ns 3

4 ELECTRICL CHRCTERISTICS (continued) (V = 5V, V HV = 2V, V OUT = 675V, = 3kΩ, T = -4 C to +85 C, unless otherwise noted) (Figure ) (Note 5) PRMETER SYMBOL CONITIONS MIN TYP MX UNITS STRT Condition Hold Time t HSTT % of S to 9% of SCL 4 ns STRT Condition Setup Time t SUSTT 47 ns ata Input Hold Time t HT ns ata Input Setup Time t SUT 25 ns STOP Condition Setup Time t SUSTP 4 ns Bus Free Time t BF 47 ns V REGULTOR V Output Voltage V 45V < V < 2V, I V = 3 45 V V Power-On Reset Threshold Rising edge, mv hysteresis 3 V SUPPLY Supply Range V 45 2 V Operating Current I V = 2V 6 µ HV SUPPLY HV Input Voltage Range V HV 6 28 V HV Power-On Reset Threshold Rising edge, 6mV hysteresis 6 V Not in program mode (Note 3) HV Input Bias Current I HV Program mode (Note 3) 3 uring program (Note 4) 6 µ OUTPUT VOLTGE OUT Voltage Range V OUT V SET + 5V Note : SET resistors are only checked at full scale Note 2: Guaranteed by design Not production tested Note 3: The enters program mode after any valid command is received, except the h command Note 4: Program time lasts for ms Note 5: Specifications from C to -4 C are guaranteed by design, not production tested 3 V t HSTT t R SCL t CLL t CLH t F t HT t SUT S V IH VIL t SUSTP t BF Figure Timing efinitions Used in the Electrical Characteristics 4

5 (V = 9V, V HV = 8V, = 249kΩ, T = +25 C, unless otherwise noted) SUPPLY CURRENT (µ) SUPPLY CURRENT vs TEMPERTURE 25 V = 9V 2 toc FULL-SCLE IOUT (µ) FULL-SCLE I OUT vs V = 2V V = 45V Typical Operating Characteristics toc2 IOUT SINK-CURRENT ERROR (LSB) I OUT SINK-CURRENT ERROR vs V toc TEMPERTURE ( C) (kω) V (V) I OUT SINK-CURRENT ERROR vs V OUT I OUT SINK-CURRENT ERROR vs TEMPERTURE TOTL UNJUSTE ERROR vs C SETTING IOUT SINK-CURRENT ERROR (LSB) toc4 IOUT SINK-CURRENT ERROR (LSB) toc5 TOTL UNJUSTE ERROR (LSB) toc6 V = 9V V = 9V V OUT (V) TEMPERTURE ( C) C SETTING INTEGRL NONLINERITY vs C SETTING IFFERENTIL NONLINERITY vs C SETTING INTEGRL NONLINERITY (LSB) toc7 IFFERENTIL NONLINERITY (LSB) toc C SETTING C SETTING 5

6 Typical Operating Characteristics (continued) (V = 9V, V HV = 8V, = 249kΩ, T = +25 C, unless otherwise noted) POWER-UP RESPONSE POWER-OWN RESPONSE SINGLE LSB STEP-UP RESPONSE toc9 toc toc 9V 9V B B 36V B C 4V C C 325mV V, 5V/div B V OUT, 2V/div 2µs/div C V, 2V/div V SET, 2V/div SINGLE LSB STEP-OWN RESPONSE toc2 V, 5V/div B V OUT, 2V/div 5ms/div C V, 2V/div V SET, 2V/div WRITE H RESPONSE toc3 SCL, 5V/div B S, 5V/div 5µs/div C V SET, 5mV/div V OUT, 5mV/div WRITE FFH RESPONSE toc4 B B B C 395V 345V 4mV C 395V 345V 45mV C SCL, 5V/div B S, 5V/div 5µs/div C V SET, 5mV/div V OUT, 5mV/div SCL, 5V/div B S, 5V/div 5µs/div C V OUT, 5mV/div V SET, 2mV/div SCL, 5V/div B S, 5V/div 5µs/div C V OUT, 5mV/div V SET, 2mV/div 6

7 PIN NME FUNCTION OUT djustable Sink-Current Output OUT connects to the resistive voltage-divider between and GN that sets the voltage I OUT lowers the divider voltage by an adjustable amount See the SET pin description 2 High-Voltage nalog Supply Bypass to GN with a µf capacitor 36V Regulator Output V 3 V provides the supply voltage to the entire IC V is not for external use Bypass to GN with a µf capacitor 4 GN Ground Connect to system ground 5 HV EEPROM High-Voltage Programming Supply Bypass to GN with a µf capacitor Connect this pin to the TFT LC VGON supply VGON should be between 6V and 28V The HV pin supplies the power for the internal EEPROM writing cycle The internal writing circuits are disabled when HV is less than 56V (typ) 6 S I 2 C-Compatible Clock Input 7 SCL I 2 C-Compatible Serial Bidirectional ata Line 8 SET Full-Scale Sink-Current djustment Input Connect a resistor,, from SET to GN to set the full-scale adjustable sink current The full-scale adjustable sink current is equal to: V 2 RSET I OUT is equal to the current through Pin escription +33V µf VGON µf 2 x 39kΩ I 2 C BUS V HV S SCL OUT µf R 649kΩ GN SET R2 5kΩ 249kΩ Figure 2 Standard pplication Circuit 7

8 I 2 C BUS +33V S SCL V I 2 C CONTROL INTERFCE LINER REGULTOR 7 C 9R R OUT R R2 VGON 7 EEPROM BLOCK SET HV GN Figure 3 Simplified Functional iagram etailed escription The is a solid-state alternative to mechanical potentiometers used for adjusting the LC backplane voltage () in TFT LC displays The attaches to an external resistive voltage-divider and sinks a programmable current (I OUT ), which sets the level (Figure 2) n internal 7-bit C controls the sink current and allows the user to increase or decrease the level (Figure 3) The C is ratiometric relative to V and is monotonic over all operating conditions The user can store the C setting in an internal EEPROM On power-up, the EEPROM presets the C to the last stored setting The 2-wire I 2 C interface between the LC panel and the programming circuit adjusts the C and programs the EEPROM The resistive voltage-divider and the supply set the maximum value of The sinks current from the voltage-divider to reduce the level The external resistor sets the full-scale sink current and the minimum value of Supply Voltages and V The has an internal linear regulator that generates a 36V V voltage from the supply voltage The V voltage supplies power to the and should not be used for external loads accepts voltages from 45V to 2V Bypass and V to GN with a µf capacitor each HV The HV input provides the high voltage required to program the EEPROM The HV pin is typically connected to the TFT LC positive gate driver supply (VGON) supply VGON should be between 6V and 28V EEPROM programming is disabled when HV is below 56V (typ) Bypass HV to GN with a µf capacitor The EEPROM programming block is turned off when the first powers up, and also immediately after the EEPROM is programmed When the EEPROM programming block is off, the HV supply current is less than µ fter the receives any command that changes the C value, the EEPROM programming block is enabled, and the HV supply current increases to 5µ (typ) uring the programming of the EEPROM, the HV supply current may draw up to 6µ (max) Setting the djustment Range ( ) The external resistive voltage-divider sets the maximum value of the adjustment range sets the full-scale sink current, I OUT, which determines the minimum value of the adjustment range Large values increase resolution but decrease the adjustment range Calculate R, R2, and using the following procedure: 8

9 ) Choose the maximum level (V MX ), the minimum level (V MIN ), and the supply voltage (V ) 2) Select R between kω and 5kΩ based on the acceptable power loss from the supply rail 3) Calculate R2: 4) Calculate : V R2 MX R ( V VMX) RSET = VMX 2 ( VMX VMIN) 5) Verify that I SET(MX) does not exceed 2µ: V I SET( MX) = 2 RSET 2µ R 6) If I SET exceeds 2µ, return to step 2 and choose a larger value for R 7) The resulting resolution is: ( VMX VMIN) 27 complete design example is given below: ) V MX = 5V, V MIN = 3V, V = V 2) If R = 2kΩ, then R2 = 2kΩ and = 249kΩ 3) I SET(MX) = 2µ 4) Resolution = 575mV Translating Existing Potentiometer Circuits Existing adjustment circuits using conventional mechanical potentiometers can be translated into circuits Figures 4 and 5 show two common adjustment circuits and their equivalent circuits MECHNICL POTENTIOMETER EQUIVLENT CIRCUIT R R B R R C OUT R = R R2 = R B + R C = R x (R B + R C ) 2 x R B GN SET R2 Figure 4 Replacement of Mechanical Potentiometer Circuit 9

10 MECHNICL POTENTIOMETER R R E EQUIVLENT CIRCUIT R R F OUT R = R R2 = R F = R x (R + R E + R F ) 2 x R E GN SET R2 Figure 5 Replacement of Mechanical Potentiometer Circuit pplications Information I 2 C-Bus-Compatible Interface The is a receive-only device with an I 2 C address of 5Eh The 2-wire, I 2 C-bus-compatible serial interface (pins SCL and S) is designed to attach to a I 2 C bus Connect both SCL and S lines to the positive bus supply through individual pullup resistors Calculate the required value of the pullup resistors using: RPULLUP tr CBUS where t R is the rise time in the Electrical Characteristics, and C BUS is the total capacitance on the bus The is compatible with the standard I 2 C interface protocol as defined in the following subsections See Figure 6 Bus Not Busy The I 2 C bus is not busy when both data and clock lines remain HIGH ata transfers may be initiated only when the bus is not busy STRT ata Transfer (S) Starting from an idle bus state (both S and SCL are high), a STRT condition consists of a HIGH to LOW transition of the S line while the clock (SCL) is HIGH ll commands must be preceded by a STRT condition STOP ata Transfer (P) STOP condition consists of a LOW to HIGH transition of the S line while the clock (SCL) is HIGH ll operations must be ended with a STOP condition S SCL S STRT CONITION T LINE STBLE T VLI CHNGE OF T LLOWE P STOP CONITION Figure 6 I 2 C Bus STRT, STOP, and ata Change Conditions

11 Slave ddress fter generating a STRT condition, the bus master transmits the slave address consisting of a 7-bit device code (b or 5Eh) for the Since the is a write-only device, the eighth bit of the slave address is zero The monitors the bus for its corresponding slave address continuously It generates an acknowledge bit when it recognizes its address S ata Valid The state of the data line represents valid data when, after a STRT condition, the data line is stable for the duration of the HIGH period of the clock signal The data on the line must be changed during the LOW period of the clock signal There is one clock pulse per bit of data cknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte The master device must generate an extra clock pulse that is associated with this acknowledge bit The device that acknowledges has to pull down the S line during the acknowledge clock pulse so that the S line is stable LOW during the HIGH period of the acknowledge-related clock pulse Of course, setup and hold times must be taken into account See Figure 7 The does not acknowledge the program EEPROM command (h) if HV is below 56V (typ) or if the is not in program mode The does not acknowledge any command while an internal programming cycle is in progress Once the internally timed EEPROM write cycle has started, acknowledge polling can be initiated This involves repeatedly sending a 55h command Only if the internal write cycle has completed does the acknowledge the command T OUTPUT BY MSTER 7 6 T OUTPUT BY NOT CKNOWLEGE CKNOWLEGE SCL FROM MSTER CLK 2 CLK2 8 CLK8 9 CLK9 S STRT CONITION CKNOWLEGE CLOCK PULSE Figure 7 I 2 C Bus cknowledge

12 Table Command Byte Functions BYTE FUNCTION FIGURE h ecrement the C setting by LSB 8 FFh Increment the C setting by LSB 8 h Write the current C setting to EEPROM 8 55h Load the EEPROM setting to the C 8 h Write a specific value to the C 8B Command Byte complete command consists of a STRT condition (S) followed by the s slave address (5Eh) and a command byte, or a command byte and a C value, followed by a STOP condition (P) There are five commands, and their functions are listed in Table C Values Table 2 lists the C values and the corresponding I SET, V SET, and V OUT values Layout Information Use the following guidelines for good layout: ) Place the buffer and the R/R2 voltagedivider close to the OUT pin (Figure 2) 2) Place close to SET Table 2 C Settings C VLUE I SET V SET (V) V OUT (V) FFh I SET(MX) V SET(MX) V MIN FEh h 3) Bypass V and with µf capacitors placed close to the IC with short connections to the pins 4) Refer to the evaluation kit for an example of proper board layout Chip Information TRNSISTOR COUNT: 698 PROCESS: BiCMOS I SET(MX) - LSB I SET(MIN) + LSB V SET(MX) - LSB V SET(MIN) + LSB V MIN + LSB V MX - LSB h I SET(MIN) V SET(MIN) V MX STRT STOP S SLVE RESS COMMN BYTE P () FOR THE H, FFH, H, N 55H COMMNS CK CK STRT STOP S SLVE RESS SET C VLUE (H) C VLUE P CK CK CK (B) FOR THE C INITIL VLUE-SETTING COMMN Figure 8 I 2 C Bus ata Transfer Summary 2

13 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications For the latest package outline information, go to wwwmaxim-iccom/packages) 6± 6± 8 Ø5± TOP VIEW E H 4X S BOTTOM VIEW 8 IM INCHES MIN MX BSC 2 3 b c e E 6 H 88 L 6 α S 27 BSC MILLIMETERS MIN MX BSC BSC 8LUMXEPS 2 e b c L α FRONT VIEW SIE VIEW PROPRIETRY INFORMTION TITLE: PCKGE OUTLINE, 8L umx/usop PPROVL OCUMENT CONTROL NO REV 2-36 J Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products, 2 San Gabriel rive, Sunnyvale, C Maxim Integrated Products Printed US is a registered trademark of Maxim Integrated Products, Inc