PART. Note: All devices are specified over the -40 C to +125 C operating PART. Maxim Integrated Products 1

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1 9-2424; Rev 2; 5/6 Ultra-Low Offset/Drift, Low-Noise, General Description The are low-noise, low-drift, ultrahigh precision amplifiers that offer near-zero DC offset and drift through the use of autocorrelating zeroing techniques. This method constantly measures and compensates the input offset, eliminating drift over time and temperature and the effect of /f noise. Both devices feature rail-to-rail outputs, operate from a single 2.7V to 5.5V supply, and consume only 6µA. An active-low shutdown mode decreases supply current to.µa. The is unity-gain stable with a gain-bandwidth product of MHz, while the decompensated is stable with A V V/V and a GBWP of 6.5MHz. The are available in 8-pin narrow SO, 6-pin TDFN and SOT23 packages. Thermocouples Strain Gauges Electronic Scales Medical Instrumentation Instrumentation Amplifiers Applications Typical Application Circuit 5V 36Ω STRAIN GUAGE 8kΩ 8kΩ A V = / AIN ADC Ultra-Low,.µV Offset Voltage 2.µV (max) at +25 C 2.5µV (max) at -4 C to +85 C 3.5µV (max) at -4 C to +25 C Low nv/ o C Drift Features Specified over the -4 o C to +25 o C Automotive Temperature Range Low Noise:.5µV P-P from DC to Hz 5dB A VOL, 4dB PSRR, 4dB CMRR High Gain-Bandwidth Product MHz () 6.5MHz ().µa Shutdown Mode Rail-to-Rail Output (R L = kω) Low 6µA Supply Current Ground-Sensing Input Single 2.7V to 5.5V Supply Voltage Range Available in a Space-Saving 6-Pin SOT23 and TDFN Packages PART Ordering Information PIN- PACKAGE TOP MARK Note: All devices are specified over the -4 C to +25 C operating temperature range. +Denotes lead-free package. *EP = Exposed paddle. Pin Configurations appear at end of data sheet. PKG CODE AUT-T 6 SOT23-6 AAZZ U6F-6 ASA 8 SO S8-4 ATT+T 6 TDFN-EP* +ANG T633-2 AUT-T 6 SOT23-6 ABAA U6F-6 ASA 8 SO S8-4 ATT+T 6 TDFN-EP* +ANH T633-2 PART MINIMUM STABLE GAIN Selector Guide GAIN BANDWIDTH (MHz) V/V V/V 6.5 Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage (V CC to GND)...6V All Other Pins...(GND -.3V) to (V CC +.3V) Output Short-Circuit Duration ( shorted to V CC or GND)...Continuous Continuous Power Dissipation (T A = +7 C) 6-Pin Plastic SOT23 (derate 9.mW/ C above +7 C)...727mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS 8-Pin Plastic SO (derate 5.88mW/ C above +7 C)...47mW 6-Pin TDFN-EP (derate 8.2mW above +7 C)...454mW Operating Temperature Range...-4 C to +25 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C (2.7V V CC 5.5V, V CM = GND = V, V = V CC /2, R L = kω connected to V CC /2, SHDN = V CC, T A = +25 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Offset Voltage V OS (Note ). 2 µv Long-Term Offset Drift 5 nv/hr Input Bias Current I B (Note 2) pa Input Offset Current I OS (Note 2) 2 pa Peak-to-Peak Input Noise Voltage e np-p R S = Ω,.Hz to Hz.5 µv P-P Input Voltage-Noise Density e n f = khz 3 NV/ Hz Common-Mode Input Voltage Range V CM Inferred from CMRR test Common-Mode Rejection Ratio CMRR -.V V CM V CC -.3V (Note ) 2 4 db Power-Supply Rejection Ratio PSRR 2.7V V CC 5.5V (Note ) 2 4 db.5v V OU T V C C -.5V ( N ote ) Large-Signal Voltage Gain A VOL.V V V CC -.V (Note ) R L = kω Output Voltage Swing V OH /V OL R L = kω GND -. R L = kω 25 5 R L = kω V CC -.3 V CC - V OH 4 V OL 4 V CC - V OH 35 5 V OL 35 5 Output Short-Circuit Current To either supply 4 ma Output Leakage Current V V CC, SHDN = GND (Note 2). µa Slew Rate Gain-Bandwidth Product Minimum Stable Closed-Loop Gain GBWP V CC = 5V, C L = pf,.35 V = 2V step.6 R L = kω, C L = pf, measured at f = khz 6.5 R L = kω, C L = pf, phase margin = 6 o V db mv V/µs MHz V/V 2

3 ELECTRICAL CHARACTERISTICS (continued) (2.7V V CC 5.5V, V CM = GND = V, V = V CC /2, R L = kω connected to V CC /2, SHDN = V CC, T A = +25 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum Closed-Loop Gain Settling Time Overload Recovery Time R L = kω, C L = pf, phase margin = 6 o 67 -V step A V = (Note 4) Startup Time A V =.% ( bit).5.25% (2 bit)..6% (4 bit).7.5% (6 bit) 2.3.% ( bit) % (2 bit) 4..6% (4 bit) 4.9.5% (6 bit) 5.7.% ( bit).8.25% (2 bit) 2.6.6% (4 bit) 3.4.5% (6 bit) 4.3 Supply Voltage Range V CC Inferred by PSRR test V SHDN = V CC, no load, V CC = 5.5V 6 85 Supply Current I CC SHDN = GND, V CC = 5.5V. V/V ms ms ms µa Shutdown Logic-High V IH 2.2 V Shutdown Logic-Low V IL.8 V Shutdown Input Current V V SHDN V CC. µa 3

4 ELECTRICAL CHARACTERISTICS (2.7V V CC 5.5V, V CM = GND = V, V = V CC /2, R L = kω connected to V CC /2, SHDN = V CC, T A = -4 C to +25 C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Offset Voltage V OS (Note ) T A = -4 C to +85 C 2.5 T A = -4 C to +25 C 3.5 Input Offset Drift TCV OS (Note ) nv/ C Common-Mode Input Voltage Range Common-Mode Rejection Ratio V CM CMRR Inferred from CMRR test GND -.5 GN D -.5V T A = -4 C to +85 C 5 V C M V C C -.4V ( N ote ) T A = -4 C to +25 C 9 Power-Supply Rejection Ratio PSRR 2.7V V CC 5.5V (Note ) 2 db Large-Signal Voltage Gain A VOL R L = kω,.v V T A = -4 C to +85 C 25 V CC -.V (Note ) T A = -4 C to +25 C 95 R L = kω (Note ) R L = kω Output Voltage Swing V OH /V OL R L = kω Output Leakage Current.V V V CC -.V, T A = -4 C to +85 C.2V V V CC -.2V, T A = -4 C to +25 C 2 V CC -.4 V CC - V OH 2 V OL 2 V CC - V OH V OL V V V CC, SHDN = GND (Note 3) 8 µv V db db db mv 2 µa Supply Voltage Range V CC Inferred by PSRR test V SHDN = V CC, no load, V CC = 5.5V 9 Supply Current I CC SHDN = GND, V CC = 5.5V 2 µa Shutdown Logic High V IH 2.2 V Shutdown Logic Low V IL.7 V Shutdown Input Current V V SHDN V CC 2 µa Note : Guaranteed by design. Thermocouple and leakage effects preclude measurement of this parameter during production testing. Devices are screened during production testing to eliminate defective units. Note 2: IN+ and IN- are gates to CMOS transistors with typical input bias current of pa. CMOS leakage is so small that it is impractical to test and guarantee in production. Devices are screened during production testing to eliminate defective units. Note 3: Leakage does not include leakage through feedback resistors. Note 4: Overload recovery time is the time required for the device to recover from saturation when the output has been driven to either rail. Note 5: Specifications are % tested at T A = +25 C, unless otherwise noted. Limits over temperature are guaranteed by design. 4

5 Typical Operating Characteristics (V CC = 5V, VCM = V, R L = kω connected to V CC /2, SHDN = V CC, T A = +25 C, unless otherwise noted.) PERCENTAGE OF UNITS (%) INPUT OFFSET DISTRIBUTION OFFSET VOLTAGE (μv) /39 toc OFFSET VOLTAGE (μv) OFFSET VOLTAGE vs. SUPPLY VOLTAGE T A = +25 C T A = +25 C SUPPLY VOLTAGE (V) T A = -4 C /39 toc2 OFFSET VOLTAGE (μv) OFFSET VOLTAGE vs. COMMON-MODE VOLTAGE T A = +25 C T A = +25 C T A = -4 C COMMON-MODE VOLTAGE (V) /39 toc3 PUT HIGH VOLTAGE (V) PUT HIGH VOLTAGE vs. PUT SOURCE CURRENT V OH = V CC - V V CC = 2.7V V CC = 5V SOURCE CURRENT (ma) V CC = 5V GAIN = 6dB -4 R L = kω -6 C L = pf -8 k k k M M /39 toc4 /39 toc7 PUT LOW VOLTAGE (V) PUT LOW VOLTAGE vs. PUT SINK CURRENT V CC = 2.7V V CC = 5V SINK CURRENT (ma) V CC = 5V GAIN = 4dB -4 R L = kω -6 C L = pf -8 k k k M M /39 toc5 /39 toc V CC = 5V GAIN = 6dB -4 R L = kω -6 C L = pf -8 k k k M M V CC = 5V GAIN = 4dB -4 R L = kω -6 C L = 68pF -8 k k k M M /39 toc6 /39 toc9 5

6 Typical Operating Characteristics (continued) (V CC = 5V, VCM = V, R L = kω connected to V CC /2, SHDN = V CC, T A = +25 C, unless otherwise noted.) V CC = 5V GAIN = 4dB -4 R L = kω -6 C L = pf -8 E+2 E+3 E+4 E+5 E+6 E POWER-SUPPLY REJECTION RATIO vs. FREQUENCY /39 toc /39 toc V CC = 5V GAIN = 4dB -4 R L = kω -6 C L = pf -8 E+2 E+3 E+4 E+5 E+6 E COMMON-MODE REJECTION RATIO vs. FREQUENCY /39 toc /39 toc4 SUPPLY CURRENT (μa) SUPPLY CURRENT vs. SUPPLY VOLTAGE 6 T A = +25 C T A = +25 C SUPPLY VOLTAGE (V) T A = -4 C LARGE-SIGNAL TRANSIENT RESPONSE /39 toc5 MAx4238/39 toc2 IN V/div PSRR (db) CMRR (db) V/div -6.. FREQUENCY (khz) SMALL-SIGNAL TRANSIENT RESPONSE /39 toc6-6.. FREQUENCY (khz) SMALL-SIGNAL TRANSIENT RESPONSE /39 toc7 A V = V/V R L = 2kΩ C L = pf μs/div OVERVOLTAGE RECOVERY TIME /39 toc8 IN 5mV/div IN 5mV/div IN 5mV/div 5mV/div 5mV/div V/div A V = V/V R L = 2kΩ C L = pf μs/div A V = V/V R L = 2kΩ C L = pf μs/div A V = V/V R L = kω V CC = 2.5V V EE = -2.5V 4μs/div 6

7 Typical Operating Characteristics (continued) (V CC = 5V, VCM = V, R L = kω connected to V CC /2, SHDN = V CC, T A = +25 C, unless otherwise noted.) V CC = 2.5V V EE = -2.5V DC TO Hz NOISE s/div /39 toc9 2μV/div SHDN R L = kω C L = pf SHUTDOWN WAVEFORM μs/div /39 toc2 2V/div V/div PIN TDFN SOT23 SO NAME FUNCTION 6 Amplifier Output GND Ground IN+ Noninverting Input IN- Inverting Input 5 5 SHDN Shutdown Input. Active-low shutdown, connect to V CC for normal operation V CC Positive Power Supply 5, 8 N.C. EP EP Pin Description No Connection. Not internally connected. Exposed Pad. Connect EP to GND. Detailed Description The are high-precision amplifiers that have less than 2.5µV of input-referred offset and low /f noise. These characteristics are achieved through an autozeroing technique that samples and cancels the input offset and noise of the amplifier. The pseudorandom clock frequency varies from khz to 5kHz, reducing intermodulation distortion present in chopper-stabilized amplifiers. Offset Error Sources To achieve very low offset, several sources of error common to autozero-type amplifiers need to be considered. The first contributor is the settling of the sampling capacitor. This type of error is independent of inputsource impedance, or the size of the external gain-setting resistors. Maxim uses a design technique to avoid large changes in the voltage on the sampling capacitor to reduce settling time errors. The second error contributor, which is present in both autozero and chopper-type amplifiers, is the charge injection from the switches. The charge injection appears as current spikes at the input, and combined with the impedance seen at the amplifier s input, contributes to input offset voltage. Minimize this feedthrough by reducing the size of the gain-setting resistors and the input-source impedance. A capacitor in parallel with the feedback resistor reduces the amount of clock feedthrough to the output by limiting the closed-loop bandwidth of the device. The design of the minimizes the effects of settling and charge injection to allow specification of an input offset voltage of.µv (typ) and less than 2.5µV over temperature (-4 C to +85 C). /f Noise /f noise, inherent in all semiconductor devices, is inversely proportional to frequency. /f noise increases 3dB/octave and dominates amplifier noise at lower frequencies. This noise appears as a constantly changing voltage in series with any signal being measured. The treat /f noise as a slow varying offset error, inherently canceling the /f noise. 7

8 Output Overload Recovery Autozeroing amplifiers typically require a substantial amount of time to recover from an output overload. This is due to the time it takes for the null amplifier to correct the main amplifier to a valid output. The / require only 3.3ms to recover from an output overload (see Electrical Characteristics and Typical Operating Characteristics). Shutdown The feature a low-power (.µa) shutdown mode. When SHDN is pulled low, the clock stops and the device output enters a high-impedance state. Connect SHDN to V CC for normal operation. Applications Information Minimum and Maximum Gain Configurations The is a unity-gain stable amplifier with a gainbandwidth product (GBWP) of MHz. The is decompensated for a GBWP of 6.5MHz and is stable with a gain of V/V. Unlike conventional operational amplifiers, the have a maximum gain specification. To maintain stability, set the gain of the between A V = V/V to V/V, and set the gain of the between A V = 67V/V and V/V. ADC Buffer Amplifier The low offset, fast settling time, and /f noise cancellation of the make these devices ideal for ADC buffers. The are well suited for low-speed, high-accuracy applications such as strain gauges (see Typical Application Circuit). 2 TOP VIEW 3 4 / SO VCC 6 EP* *CONNECT EP TO GND. N.C. V CC N.C. Pin Configurations SHDN 5 / GND GND IN+ IN- IN IN+ TDFN (3mm x 3mm x.8mm) / 6 V CC SOT23 5 SHDN SHDN IN- IN+ GND Error Budget Example When using the as an ADC buffer, the temperature drift should be taken into account when determining the maximum input signal. With a typical offset drift of nv/ C, the drift over a C range is nv. Setting this equal to /2LSB in a 6-bit system yields a full-scale range of 3mV. With a single 2.7V supply, an acceptable closed-loop gain is A V = 2. This provides sufficient gain while maintaining headroom. TRANSISTOR COUNT: 82 PROCESS: BiCMOS Chip Information 8

9 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 6LSOT.EPS PACKAGE LINE, SOT 6L BODY 2-58 I 2 PACKAGE LINE, SOT 6L BODY I 2 9

10 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to N TOP VIEW E H INCHES MILLIMETERS DIM MIN MAX MIN MAX A A B C e.5 BSC.27 BSC E H L VARIATIONS: DIM D D D INCHES MILLIMETERS MIN MAX MIN MAX N MS AA AB AC SOICN.EPS D A C e B A FRONT VIEW L SIDE VIEW -8 PROPRIETARY INFORMATION TITLE: PACKAGE LINE,.5" SOIC APPROVAL DOCUMENT CONTROL NO. REV. 2-4 B

11 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 6, 8, &L, DFN THIN.EPS COMMON DIMENSIONS SYMBOL MIN. MAX. A.7.8 D E A..5 L.2.4 k.25 MIN. A2.2 REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-] x e T ±. 2.3±..95 BSC MO229 / WEEA.4±.5.9 REF T ±. 2.3±..65 BSC MO229 / WEEC.3±.5.95 REF T ±. 2.3±..65 BSC MO229 / WEEC.3±.5.95 REF T33-.5±. 2.3±..5 BSC MO229 / WEED-3.25±.5 2. REF T33-2 T ±..7±. 2.3±. T ±. 2.3±. 2.3±..5 BSC MO229 / WEED-3.25±.5 2. REF.4 BSC ± REF.4 BSC ± REF Package Code: T633-2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.