Micropower, Rail-to-Rail, 300kHz Op Amp with Shutdown in a Tiny, 6-Bump WLP

Transcription

1 EVALUATION KIT AVAILABLE MAX46 General Description The MAX46 op amp features a maximized ratio of gain bandwidth (GBW) to supply current and is ideal for batterypowered applications such as handsets, tablets, notebooks, and portable medical equipment. This CMOS op amp features an ultra-low input-bias current of pa, rail-torail input and output, low supply current of 4.5μA, and operates from a single.7v to 5.5V supply. For additional power conservation, the IC also features a low-power shutdown mode that reduces supply current to.µa and puts the amplifier s outputs in a high-impedance state. This device is unity-gain stable with a 3kHz GBW product. The MAX46 is available in a space-saving,.73mm x.7mm, 6-bump wafer-level package (WLP), as well as a 6-pin SOT-23 package. The device is specified over the -4 C to +25 C automotive operating temperature range. Applications Portable Media Players Tablet/Notebook Computers Electronic Toys Portable Medical Devices Wearable Fitness Devices Pin Configurations Benefits and Features 3kHz GBW Ultra-Low 4.5μA Supply Current Single.7V to 5.5V Supply Voltage Range Ultra-Low pa Input Bias Current Rail-to-Rail Input and Output Voltage Ranges Low ±2μV Input Offset Voltage Low.μA Shutdown Current High-Impedance Output During Shutdown Unity-Gain Stable Available in Tiny,.73mm x.7mm, 6-Bump WLP and SOT-23 Packages -4 C to +25 C Temperature Range Ordering Information appears at end of data sheet. Typical Operating Characteristic QUIESCENT SUPPLY CURRENT (μa) SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = -4 C T A = +25 C T A = +25 C toc SUPPLY VOLTAGE (V) 9-876; Rev ; /6

2 Absolute Maximum Ratings V DD to GND...-.3V to +6V IN+, IN-,, OUT to GND V to (V DD +.3V) Differential Input Voltage (IN+, IN-)...±(V DD +.3V) Output Short Circuit Duration to either Supply...Continuous Continuous Current into any input/output...±ma Continuous Power Dissipation (T A = +7 C) 6-Bump WLP (Derate.9mW/ C above +7 C)...85mW 6-Pin SOT (Derate 4.3mW/ C above +7 C mW Package Thermal Characteristics (Note ) WLP Junction-to-Ambient Thermal Resistance (θ JA ) C/W Operating Temperature Range C to +25 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C Soldering Temperature (reflow) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SOT23 Junction-to-Ambient Thermal Resistance (θ JA )...23 C/W Junction-to-Ambient Thermal Resistance (θ JC )...76 C/W Note : Package thermal resistances were obtained using the method described in JEDEC specification JESD5-7, using a four-layer board. For detailed information on package thermal considerations, refer to Electrical Characteristics V DD = 3.6V, V GND = V, V CM = V DD /2, V OUT = V DD /2, R L =, V = V DD, T A = T MIN to T MAX. Typical values are at T A = +25ºC, unless otherwise noted. (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY VOLTAGE Supply Voltage Range V DD V Supply Current I DD V DD = 3.6V, T A = +25 C µa V DD = 3.6V, T A = -4 C to +25 C 6.5 Shutdown Supply Current I V DD = 3.6V, T A = -4 C to +25 C 55 na V DD = 5.5V, T A = -4 C to +25 C 9 Power Up Time V DD = to 5.5V step, output settles to 5% final value 35 µs Input Common-Mode Range V CM Guaranteed by CMRR test -.5 V DD +.5 V Input Offset Voltage V OS T A = +25 C ±.2 ± mv Input Offset Drift T A = -4 C to +25 C µv/ C Input Bias Current I B T A = +25 C 2 pa T A = -4 C to +25 C 3 na Input Offset Current I OS T A = +25 C 2 pa T A = -4 C to +25 C 3 na Input Capacitance C IN Either input 3 pf Maxim Integrated 2

3 Electrical Characteristics (continued) V DD = 3.6V, V GND = V, V CM = V DD /2, V OUT = V DD /2, R L =, V = V DD, T A = T MIN to T MAX. Typical values are at T A = +25ºC, unless otherwise noted. (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Common-Mode Rejection Ratio CMRR DC, V DD = 3.6V, -.5V < V CM < V DD +.5V DC, V DD =.7V, -.5V < V CM < V DD +.5V T A = -4 C to +25 C 5 db T A = -4 C to +25 C 42 db AC, mv PP at khz 55 db Power Supply Rejection DC,.7V < V DD < 5.5V 6 PSRR Ratio AC, mv PP at khz 65 db Open Loop Gain A VOL V DD = 3.6V, R L = kω 25mV < V OUT < V DD - 25mV 8 V DD =.7V, R L = kω 25mV < V OUT < V DD - 25mV 69 db R L = kω, measured relative to V DD 5 Output Voltage Swing High V OH R L = 5kΩ, measured relative to V DD 7 mv Output Voltage Swing Low V OL R L = kω, measured relative to GND 5 R L = 5kΩ, measured relative to GND 7 mv Short Circuit Current To V DD or GND 5 ma Shutdown High Level Input V IH.7 x V DD V.3 x Shutdown Low Level Input V IL V DD V Shutdown Input Bias Current.5 µa Output Leakage in Shutdown Mode V < V OUT < V DD.5 µa -3dB Bandwidth Amplifier connected as unity gain buffer 3 khz Phase Margin Amplifier connected as unity gain buffer 5 Slew Rate A V = V/V, V DD /2 -.5V to V DD /2 +.5V step, R L = kω to V DD /2, C L = 3pF.4 V/µs Settling Time.% settling, A V = V/V, V DD /2 -.5V to V DD /2 +.5V step, R L = kω to V DD /2, C L = 3pF Note 2: All devices are % production tested at T A = +25 C. Temperature limits are guaranteed by design. 2 us Capacitive Load C L A V = V/V, no sustain oscillations 3 pf Input Voltage Noise Density e N At khz 44 nv/ Hz Input Current Noise Density i N At khz. pa/ Hz Shutdown Delay Time t V DD = 5.5V, V = 5.5V to V step 2 µs Enable Delay Time t EN V DD = 5.5V, V = V to 5.5V step 35 µs Maxim Integrated 3

4 Typical Operating Characteristics (V DD = 3V, V GND = V, V CM = V DD /2, R L = kω to V DD /2, T A = 25ºC, unless otherwise noted. 5.5 SUPPLY CURRENT vs. SUPPLY VOLTAGE toc 7 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE vs. TEMPERATURE toc2 INPUT OFFSET VOLTAGE vs. INPUT COMMON MODE VOTLAGE toc3a 5 QUIESCENT SUPPLY CURRENT (μa) T A = -4 C T A = +25 C T A = +25 C SUPPLY VOLTAGE (V) SHUTDOWN CURRENT (na) T A = 25 C T A = -4 C SUPPLY VOLTAGE (V) T A = 25 C INPUT OFFSET VOTLAGE (mv) 4 T A = -4 C 3 2 T A = - C T A = 25 C T A = 7 C - -2 T A = 25 C INPUT COMMON MODE VOLTAGE (V) OCCURRENCES (%) INPUT OFFSET VOLTAGE HISTOGRAM T A = +25 C toc3b OCCURRENCES (%) INPUT OFFSET VOLTAGE HISTOGRAM T A = +25 C toc3c OCCURRENCE (%) INPUT OFFSET VOLTAGE HISTOGRAM T A = -4 C toc3d INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOTLAGE (mv) INPUT OFFSET VOLTAGE vs. TEMPERATURE toc INPUT BIAS CURRENTS (pa). INPUT BIAS CURRENTS vs. TEMPERATURE I B- I B+ toc5 INPUT BIAS CURRENTS (pa) INPUT BIAS CURRENTS vs. INPUT COMMON MODE VOLTAGE I B+ toc TEMPERATURE ( C) TEMPERATURE ( C) INPUT COMMON MODE VOLTAGE (V) Maxim Integrated 4

5 Typical Operating Characteristics (continued) (V DD = 3V, V GND = V, V CM = V DD /2, R L = kω to V DD /2, T A = 25ºC, unless otherwise noted. -2 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY toc7 9 DC CMRR vs. TEMPERATURE toc8-3 COMMON-MODE REJECTION RATIO vs. FREQUENCY toc9 POWER-SUPPLY REJECTION RATIO (db) DC CMRR (db) V DD =.7V V DD = 5.5V V DD = 3.V COMMON-MODE REJECTION RATIO (db) FREQUENCY (khz) TEMPERATURE ( C) -9.. FREQUENCY(kHz) SLEW RATE (V/µs) SLEW RATE vs. V DD V IN = V DD /2 ± 5mV GAIN = V/V, R L = kω SUPPLY VOLTAGE (V) toc OUTPUT VOTLAGE HIGH (V DD -V OUT ) (mv) V DD = 3.V, R L TO GND OUTPUT VOLTAGE HIGH vs. TEMPERATURE R L = 5kΩ R L = kω TEMPERATURE ( C) R L = kω R L = 5kΩ toc OUTPUT VOTLAGE LOW (V OUT ) (mv) V DD = 3.V, R L TO V DD OUTPUT VOLTAGE LOW vs. TEMPERATURE R L = 5kΩ R L = kω R L = kω TEMPERATURE ( C) R L = 5kΩ toc2 2 OPEN LOOP GAIN vs. V DD vs. TEMPERATURE toc3 9 DC PSRR vs. TEMPERATURE V DD =.7V TO 5.5V toc4 85 OPEN-LOOP GAIN (db) V DD =.7V V DD = 3.V V DD = 5.5V DC PSRR (db) V OUT = 25mV to V DD - 25mV, R L =kω to V DD / TEMPERATURE ( C) TEMPERATURE ( C) Maxim Integrated 5

6 Typical Operating Characteristics (continued) (V DD = 3V, V GND = V, V CM = V DD /2, R L = kω to V DD /2, T A = 25ºC, unless otherwise noted. 8 6 GAIN AND PHASE vs. FREQUENCY (R L = 5kΩ, C L = pf) GAIN A V = V/V toc TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY toc V OUT = 2V PP VOLTAGE NOISE DENSITY vs. FREQUENCY toc8 GAIN (db) PHASE PHASE ( ) THD + N (db) VOLTAGE NOISE (nv/ Hz) FREQUENCY (khz) -9.. FREQUENCY(kHz)... FREQUENCY (khz) STABILITY vs. CAPACITIVE LOAD AND ISOLATION RESISTANCE toc9 POWER UP RESPONSE (V /\ = V DD, BUFFER) toc2 SHUTDOWN RESPONSE (V DD = 5V,V IN+ = V DD /2) toc2 A V = V/V STABLE V DD V R ISO (Ω) UNSTABLE V OUT (.5V/div) V OUT CAPACITIVE LOAD (pf) 2μs/div µs/div LARGE-SIGNAL PULSE RESPONSE (C LOAD = 5pF) toc24 A V=V/V V = V IN+ V OUT µs/div Maxim Integrated 6

7 Typical Operating Characteristics (continued) (V DD = 3V, V GND = V, V CM = V DD /2, R L = kω to V DD /2, T A = 25ºC, unless otherwise noted. LARGE-SIGNAL PULSE RESPONSE (C LOAD = pf) toc25 A A V V = =V/V V/V V IN+ (.V/ div) GAIN (db) SMALL-SIGNAL GAIN vs. FREQUENCY A V = V/V, V OUT = mv P-P, C LOAD = 5pF toc26 V OUT µs/div -2.. FREQUENCY (khz) GAIN (db) A V = V/V, V OUT = 2V P-P C LOAD = 5pF LARGE-SIGNAL GAIN vs. FREQUENCY -6.. FREQUENCY (khz) toc27 PERCENT OVERSHOOT (%) PERCENT OVERSHOOT vs. CAPACITIVE LOAD V IN = V DD /2 ± 5mV, khz GAIN = V/V, R L = kω POSITIVE NEGATIVE CAPACITIVE LOAD (pf) toc28 OUTPUT WAVEFORM WITHOUT R ISO (C L = pf) toc3 A A V V = =V/V V IN+ (.V/div) V OUT (.V/div) µs/div Maxim Integrated 7

8 Pin Configurations TOP VIEW OUT MAX46 A3 B3 GND OUT + 6 VDD IN- A2 B2 VDD GND 2 MAX46 5 IN+ + A B IN+ 3 4 IN- WLP SOT23-6 Functional Block Diagram OUT VDD MAX46 VDD GND VDD GND GND GND VDD VDD IN+ 5kΩ 5kΩ IN- GND GND Pin Description PIN WLP SOT23 NAME A 3 IN+ Noninverting Input A2 4 IN- Inverting Input A3 OUT Output B 5 Active Low Shutdown Input B2 6 VDD Positive Supply Voltage B3 2 GND Ground FUNCTION Maxim Integrated 8

9 Detailed Description Featuring a maximized ratio of GBW-to-supply current, low operating supply voltage, low input bias current, and rail-to-rail inputs and outputs, the MAX46 is an excellent choice for precision or general-purpose, low-current, lowvoltage, battery-powered applications. This CMOS device consumes an ultra-low 4.5μA (typ) supply current and has a 2μV (typ) offset voltage. For additional power conservation, the IC features a low-power shutdown mode that reduces supply current to.µa (typ) and puts the amplifier s output in a high-impedance state. This device is unity-gain stable with a 3kHz GBW product, driving capacitive loads up to 3pF. The capacitive load can be increased to 25pF when the amplifier is configured for a V/V gain. Input Differential Voltage Protection During normal operation, the inverting and noninverting inputs of the device are at essentially the same voltage. However, either due to fast input voltage transients or other fault conditions, these inputs can be forced to be at two different voltages. Internal back-to-back diodes protect the inputs from an excessive differential voltage (see Functional Block Diagram). Therefore, V IN+ and V INcan be any voltage within the range shown in the Absolute Maximum Ratings section. Note the protection time is still dependent on the package thermal limits. If the input signal is fast enough to create the internal diodes forward bias condition, the input signal current must be limited to 5mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the signal input current. Care should be taken in choosing the input series resistor value, since it degrades the input noise performance of the amplifier. Rail-to-Rail Inputs and Outputs The MAX46 has a parallel-connected n-channel and p-channel differential input stage that allows an input common-mode voltage range that extends 5mV beyond the positive and negative supply rails. This device is capable of driving the output to within 5mV of both supply rails with a kω load. This device can drive a 5kΩ load with swings to within 7mV of the rails. Figure shows the output voltage swing of the amplifier, configured as a unity-gain buffer, and powered from a single 3V supply. Low Input Bias Current The MAX46 features ultra-low pa (typ) input bias current. The variation in the input bias current is minimal with changes in the input voltage due to very high input impedance (in the order of GΩ). Applications Information Driving Capacitive Loads The amplifier is unity-gain stable for loads up to 3pF. However, the capacitive load can be increased to 25pF when the amplifier is configured for a minimum gain of V/V. Applications that require greater capacitive-drive capability should use an isolation resistor between the output and the capacitive load (Figure 2). Also, in unitygain applications with relatively small R L (approximately 5kΩ), the capacitive load can be increased up to 2pF. 3V V 3V V RAIL-TO-RAIL OUTPUT VOLTAGE RANGE 2µs/div Figure. Rail-to-Rail Output Voltage Range MAX46 R ISO Figure 2. Using a Resistor to Isolate a Capacitive Load from the Op Amp R L V IN+ V OUT C L R L A V = V/V R L + R ISO Maxim Integrated 9

10 Power-Supply Considerations The MAX46 is optimized for single.7v to 5.5V supply operation. A high amplifier power-supply rejection ratio of 8dB (typ) allows the devices to be powered directly from a battery, simplifying design and extending battery life. Power-Up Settling Time The MAX46 settling time depends primarily on the output voltage and is slew rate limited. Figure 3 shows the MAX46 in a noninverting voltage follower configuration with the input held at midsupply. The output settles in approximately 35µs for V DD = 3V (see the Typical Operating Characteristics for power-up settling time). Power-Supply Bypassing and Layout To minimize noise, bypass V DD with a.μf capacitor to ground, as close to the pin as possible. Good layout techniques optimize performance by decreasing the amount of stray capacitance and inductance to the op amps inputs and outputs. Minimize stray capacitance and inductance by placing external components close to the IC. Shutdown The shutdown input () is an active-low input. For normal operating conditions, connect to a logic-high or V DD. Drive low to place the device in shut down and reduce the supply current to.µa. The MAX46 s output is high impedance in shutdown mode; however, due to the back-to-back diode protection circuit at the inputs and the feedback path, the output sees a voltage of one diode drop below the noninverting input voltage in unity buffer configuration (see Figure 4). The device typically enters shutdown in 2µs and exits in 35µs. Figure 5 and Figure 6 show the output voltage behavior during into and out of the shutdown mode in unity buffer configuration with V DD = 5V, V IN+ = 2.5V and V, respectively. Figure 7 and Figure 8 show the output with MΩ in the feedback path, limiting the leakage current from the positive input due to the internal back-to-back diodes in shutdown mode. V 5.5V kω IN- IN+ V DD MAX46 V SS OUT kω Figure 3. Power-Up Test Configuration Figure 4. MAX46 Leakage Path During Shutdown When Configured as A Buffer Maxim Integrated

11 µs a. Buffer, V DD = 5V, V IN+ = 2.5V 5V/div V 2µs 2µs b. Buffer, V DD = 5V, V IN+ = 2.5V (Zoomed In, Rising) c. Buffer, V DD = 5V, V IN+ = 2.5V (Zoomed In, Falling) Figure 5. Buffer, V DD = 5V, V IN+ = 2.5V Maxim Integrated

12 µs a. Buffer, V DD = 5V, V IN+ = V 2µs 2µs b. Buffer, V DD = 5V, V IN+ = V (Zoomed In, Rising) c. Buffer, V DD = 5V, V IN+ = V (Zoomed In, Falling) Figure 6. Buffer, V DD = 5V, V IN+ = V Maxim Integrated 2

13 OUT µs a. Buffer, V DD = 5V, V IN+ = 2.5V, R FB = MΩ 2µs 2µs b. Buffer, V DD = 5V, V IN+ = 2.5V, R FB = MΩ (Zoomed In, Rising) c. Buffer, V DD = 5V, V IN+ = 2.5V, R FB = MΩ (Zoomed In, Falling) Figure 7. Buffer, V DD = 5V, V IN+ = 2.5V, R FB = MΩ Maxim Integrated 3

14 OUT µs a. Buffer, V DD = 5V, V IN+ = V, R FB = MΩ 2µs b. Buffer, V DD = 5V, V IN+ = V, R FB = MΩ (Zoomed In, Rising) 2µs c. Buffer, V DD = 5V, V IN+ = V, R FB = MΩ (Zoomed In, Falling) Figure 8. Buffer, V DD = 5V, V IN+ = V, R FB = MΩ Maxim Integrated 4

15 Chip Information PROCESS: BiCMOS Ordering Information PART TEMP RANGE PIN- PACKAGE +Denotes a lead(pb)-free/rohs-compliant package. *Future product contact factory for availability. TOP MARK MAX46ANT+ -4 C to +25 C 6 WLP +V MAX46AVT+* -4 C to +25 C 6 SOT +ACUQ Maxim Integrated 5

16 Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 6 WLP N6D Refer to Application Note AN89 6 SOT23 U A COMMON DIMENSIONS Pin E Indicator Marking see Note 7 A.5 MAX A.7.3 A A2.3 REF AAAA D A3.4 BASIC b.23.3 TOP VIEW SIDE VIEW D E A3 D.35 BASIC E.7 BASIC A e.35 BASIC A2 S SD.8 BASIC SE. BASIC FRONT VIEW.5 S DEPOPULATED BUMPS: NONE B B A SE A E 2 e 3 BOTTOM VIEW SD D b.5 M S AB NOTES:. Terminal pitch is defined by terminal center to center value. 2. Outer dimension is defined by center lines between scribe lines. 3. All dimensions in millimeter. 4. Marking shown is for package orientation reference only. 5. Tolerance is ±.2 unless specified otherwise. 6. All dimensions apply to PbFree (+) package codes only. 7. Front - side finish can be either Black or Clear. TITLE APPROVAL DOCUMENT CONTROL NO. maxim integrated TM PACKAGE OUTLINE 6 BUMPS THIN WLP PKG..35 mm PITCH, N6D+ - DRAWING NOT TO SCALE B REV. Maxim Integrated 6

17 Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED /6 Initial release For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim Integrated s website at Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 26 Maxim Integrated Products, Inc. 7