Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers

Transcription

1 3-3087; Rev 0; /04 EVALUATION KIT AVAILABLE Low-Cost, High-Reliability, 0.5V to 3.3V ORing General Description Critical loads often employ parallel-connected power supplies with redundancy to enhance system reliability. The are highly integrated, inexpensive MOSFET controllers that provide isolation and redundant power capability in high-reliability systems. The are used in 0.5V to 3.3V systems, and have an internal charge pump to drive the gates of the N-channel pass elements to (V CS+ + 5V). During startup, the monitor the voltage drop across the external MOSFETs. Once V CS+ approaches or exceeds the bus voltage (V CS- ), the MOSFETs are turned on. The feature a dual-purpose input. A single external resistor from to ground sets the turn-on speed of the external MOSFETs. Optionally, the input can be used as a logic enable input. Once the external MOSFET is turned on, these controllers monitor the load, protecting the bus against overvoltage, undervoltage, and reverse-current fault conditions. The MAX8555 is available with a 40mV reverse-current threshold, while the MAX8555A is available with a 20mV reverse-current threshold. Overvoltage and undervoltage fault thresholds are adjustable and can be disabled. The current-limit trip points are set by the external MOSFETs R DS(ON), reducing component count. An open-drain, logic-low fault output indicates if an overvoltage, undervoltage, or reverse-current fault occurs. The MAX8555 and the MAX8555A can shut down in response to a reversecurrent fault condition as quickly as 200ns. Both devices come in space-saving 0-pin µmax or TDFN packages and are specified over the extended -40 C to +85 C temperature range. Applications Point-of-Load Supplies Power-Supply Modules Servers Telecom Power Supplies Rectifiers Redundant Power Supplies in High-Availability Systems Features Simple, Integrated, and Inexpensive MOSFET Controllers ORing FET Drive for 0.5V to 3.3V Eliminate ORing Diode Power Dissipation Provide N+ Redundant Supply Capability for Highly Reliable Systems Isolate Failed Short-Circuit Supply from Output BUS Respond to Reverse Short-Circuit Current in 200ns Adjustable Blank Time Programmable Soft-Start Logic Enable Input Adjustable Overvoltage and Undervoltage Trip Points Fault-Indicator Output Space-Saving Packages PART Ordering Information TEMP RANGE MAX8555ETB -40 C to 85 C PIN- PACKAGE 0 TDFN 3mm x 3mm* TOP MARK ACC MAX8555EUB -40 C to 85 C 0 µmax 8555EUB MAX8555AETB -40 C to 85 C 0 TDFN 3mm x 3mm* ADD MAX8555AEUB -40 C to 85 C 0 µmax 8555AEUB *Exposed paddle TOP VIEW GATE GND 2 3 V DD 4 MAX8555/ MAX8555A Pin Configurations GATE GND V DD MAX8555/ MAX8555A 0 CS+ 9 CS- 8 OVP 7 0 CS+ 9 CS- 8 OVP 7 UVP 5 6 UVP 5 6 Typical Operating Circuit appears at end of data sheet. µmax TDFN Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS GATE to GND V to +2V, to GND V to +6V OVP, UVP,, CS+, CS- to GND V to +(V + 0.3V) V DD to GND...(V - 0.3V) to +8V Continuous Power Dissipation (T A = +70 C) 0-Pin µmax (derate 5.6mW/ C above +70 C)...444mW 0-Pin TDFN (derate 24.4mW/ C above +70 C)...95mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +50 C Lead Temperature (soldering, 0s) C (V DD = 2V, V CS- =.4V, V CS+ =.5V, R = 25kΩ, V UVP = V, V OVP = 0.25V, R = 50kΩ, C VDD = C GATE = C = 0.0µF, T A = 0 C to +85 C, unless otherwise noted.) V DD SUPPLY PARAMETER CONDITIONS MIN TYP MAX UNITS V DD Input Voltage V = 2.5V V DD Supply Current unconnected = V DD unconnected, V = 2.5V, V DD = 3.25V V DD = V = 5V, V = 2.5V V DD Shutdown Current V = 0V, V DD = 3.25V 3.0 ma V DD Overvoltage Internal Rising threshold Threshold Falling threshold SUPPLY Input Voltage V DD = V V Supply Current V DD = V = 5V, V = 2.5V ma Current in Shutdown Mode = GND, V DD = V = 5V ma Output Voltage V DD = 8V to 3.25V, I = 0A V Undervoltage Lockout CS INPUTS = V DD, rising threshold = V DD, falling threshold CS+, CS- Input Current V = 2.5V, V CS = 3.0V 5.2 µa Offset Input Current (CS+, CS-) V CS = 3.0V, Figure na CS+/CS- Input Range (Note ) 0.5 V V CS Isolation CHARGE-PUMP VOLTAGE V CS+ = +3V, V CS- = 0V, I CS V CS- = +3V, V CS+ = 0V, I CS V DD = 8V to 3.25V GATE Voltage, V GATE Measured from GATE to CS+ VDD = V = 5V V ma V V µa V Charge-Pump Switching Frequency R = 20kΩ 87 R = 25kΩ 450 R = open 500 V =.5V 550 khz 2

3 ELECTRICAL CHARACTERISTICS (continued) (V DD = 2V, V CS- =.4V, V CS+ =.5V, R = 25kΩ, V UVP = V, V OVP = 0.25V, R = 50kΩ, C VDD = C GATE = C = 0.0µF, T A = 0 C to +85 C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage V Maximum Source Current V =.0V µa High Input Current V =.5V 0 5 µa Maximum Frequency Select Voltage Input Range (Note ).5 V V Logic High, V IH Charge pump enabled.0 V Logic Low, V IL Charge pump disabled 0.5 V Fault Output Low Voltage I = 0mA 0.2 V Fault Sink Current V = 0.4V 5 ma Fault Leakage Current V = 5.5V, T A = +25 C µa GATE Gate-On Threshold Gate-Drive Current Gate Shutdown Delay (Note 2) Measured from CS- to CS+ V GATE = V CS+ = 2.5V MAX MAX8555A R = open R = 25kΩ V GATE = V CS+ = 2.5V, R = open 5 V DD = V = 3V R = 25kΩ 7.5 V GATE = V CS+ = 2.5V, R = open 30 V DD = V = 5V R = 25kΩ 5 V falling I REV fault Gate Discharge Current V GATE = V CS+ = +5V 000 ma GATE Fall Time CURRENT SENSE Reverse-Current Threshold Gate voltage fall from to V GATE = V CS+, R = 2Ω, Figure 3 or Figure 4 Measured from CS- to CS+ mv µa ns 0.2 µs MAX MAX8555A Startup I REV Blank Time = unconnected 4. ms Forward-Current Threshold Measured from CS+ to CS mv mv 3

4 ELECTRICAL CHARACTERISTICS (continued) (V DD = 2V, V CS- =.4V, V CS+ =.5V, R = 25kΩ, V UVP = V, V OVP = 0.25V, R = 50kΩ, C VDD = C GATE = C = 0.0µF, T A = 0 C to +85 C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS OVERVOLTAGE PROTECTION OVP rising OVP Fault Threshold, V OVP OVP falling 0.4 OVP Bias Current UNDERVOLTAGE PROTECTION T A = +25 C 0. T A = +85 C 0.02 UVP rising UVP Fault Threshold, V UVP UVP falling 0.4 UVP Bias Current ELECTRICAL CHARACTERISTICS T A = +25 C 0. T A = +85 C (V DD = 2V, V CS- =.4V, V CS+ =.5V, R = 25kΩ, V UVP = V, V OVP = 0.25V, R = 50kΩ, C VDD = C GATE = C = 0.0µF, T A = -40 C to +85 C, unless otherwise noted.) (Note 3) V µa V µa V DD SUPPLY PARAMETER CONDITIONS MIN TYP MAX UNITS V DD Input Voltage V = 2.5V V DD Supply Current unconnected = V DD unconnected, V = 2.5V, V DD = 3.25V 3.3 V DD = V = 5V, V = 2.5V 0.2 V DD Shutdown Current V = 0V, V DD = 3.25V 3.0 ma V DD Overvoltage Internal Rising threshold Threshold Falling threshold SUPPLY Input Voltage V DD = V V Supply Current V DD = V = 5V, V = 2.5V 3.0 ma Current in Shutdown Mode = GND, V DD = V = 5V 3.0 ma Output Voltage V DD = 8V to 3.25V, I = 0A V Undervoltage Lockout CS INPUTS = V DD, rising threshold = V DD, falling threshold Offset Input Current (CS+, CS-) V CS = 3.0V, Figure na CS+/CS- Input Range (Note ) 0.5 V V CHARGE-PUMP VOLTAGE V DD = 8V to 3.25V GATE Voltage, V GATE Measured from GATE to CS+ VDD = V = 5V V ma V V V 4

5 ELECTRICAL CHARACTERISTICS (continued) (V DD = 2V, V CS- =.4V, V CS+ =.5V, R = 25kΩ, V UVP = V, V OVP = 0.25V, R = 50kΩ, C VDD = C GATE = C = 0.0µF, T A = -40 C to +85 C, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage V Maximum Source Current V =.0V 85 5 µa High Input Current V =.5V 5 µa Maximum Frequency Select Voltage Input Range (Note ).5 V V Logic High, V IH Charge pump enabled. V Logic Low, V IL Charge pump disabled 0.5 V Fault Output Low Voltage I = 0mA 0.2 V Fault Sink Current V = 0.4V 5 ma GATE Gate-On Threshold Measured from CS- to CS+ Gate-Drive Current V GATE = V CS+ = 2.5V Gate Shutdown Delay CURRENT SENSE Reverse-Current Threshold Measured from CS- to CS+ MAX MAX8555A R = open 7 33 R = 25kΩ 8 6 V falling 200 I REV fault 50 MAX MAX8555A 6 24 Forward-Current Threshold Measured from CS+ to CS- 6 4 mv OVERVOLTAGE PROTECTION OVP Fault Threshold, V OVP OVP rising V UNDERVOLTAGE PROTECTION UVP Fault Threshold, V UVP UVP rising V Note : Guaranteed by design. Not production tested. Note 2: Gate shutdown delay is measured from reverse-current fault to the start of gate-voltage falling or from to the start of gate-voltage falling. Note 3: Specifications to -40 C are guaranteed by design and not production tested. mv µa ns mv 5

6 Typical Operating Characteristics (V DD = 2V, V CS+ =.5V, R = 25kΩ, V UVP = V, V OVP = 0.4V, R = 50kΩ to output bus, C VDD = C GATE = C = 0.0µF, T A = +25 C, R = 2Ω in Figure 3, MAX8555A, unless otherwise noted.) GATE CURRENT (µa) GATE-CHARGE CURRENT vs. RESISTOR (V DD = 2V) T A = +85 C T A = +25 C T A = -40 C RESISTOR (kω) MAX8555/55A toc0 GATE-CHARGE CURRENT (µa) GATE-CHARGE CURRENT vs. RESISTOR (V DD = V = 3V) 8 T A = +85 C T A = +25 C T A = -40 C RESISTOR (kω) MAX8555/55A toc02 VDD CURRENT (ma) V DD CURRENT vs. TEMPERATURE = OPEN = GND V DD = 3.25V TEMPERATURE ( C) MAX8555/55A toc03 REVERSE-CURRENT THRESHOLD (mv) REVERSE-CURRENT THRESHOLD vs. TEMPERATURE TEMPERATURE ( C) POWER-UP WAVEFORMS BUS VOLTAGE HIGH IMPEDANCE MAX8555/55A toc06 MAX8555/55A toc04 LEAKAGE CURRENT (na) OVP AND UVP LEAKAGE CURRENT vs. TEMPERATURE OVP UVP TEMPERATURE ( C) POWER-UP WAVEFORMS BUS VOLTAGE IS LIVE MAX8555/55A toc07 MAX8555/55A toc05 V CS+ V GATE 5V/div 5V/div V CS+ V GATE V CS- V CS- A/div I MOSFET 500mA/div I MOSFET ms/div 2ms/div 6

7 Typical Operating Characteristics (continued) (V DD = 2V, V CS+ =.5V, R = 25kΩ, V UVP = V, V OVP = 0.4V, R = 50kΩ to output bus, C VDD = C GATE = C = 0.0µF, T A = +25 C, R = 2Ω in Figure 3, MAX8555A, unless otherwise noted.) V V GATE I MOSFET POWER-UP AND DOWN WAVEFORMS USING 5ms/div MAX8555/55A toc08 2V/div 5V/div A/div V GATE V V CS- I MOSFET REVERSE-CURRENT SHUTDOWN WAVEFORMS 200ns/div MAX8555/55A toc09 5V/div 00mV/div 0A -2A UVP SHUTDOWN WAVEFORMS MAX8555/55A toc0 OVP SHUTDOWN WAVEFORMS MAX8555/55A toc V 2V/div V OVP 2V/div V GATE 5V/div V CS- AC-COUPLED 00mV/div V CS- AC-COUPLED 00mV/div V GATE 5V/div V UVP 2V/div V 200ns/div 200ns/div POWER-SUPPLY OUTPUT SHORT-CIRCUIT SHUTDOWN WAVEFORMS MAX8555/55A toc2 V DD SHUTDOWN WAVEFORMS MAX8555/55A toc3 5V/div V GATE V CS- V CS+ V GATE 5V/div V CS- AC-COUPLED 00mV/div V DD 0V/div I MOSFET2 200mA/div V 200ns/div µs/div 7

8 PIN NAME FUNCTION GATE Gate-Drive Output. Nominal GATE load is a 0.0µF capacitor to ground. Gate is discharged to GND in shutdown. 2 GND Ground 3 Low-Voltage Optional Input Power. Leave disconnected when V DD = 8V to 3.25V, or connect V DD to when V DD = 3V to 5.5V. Bypass to GND with a 0.0µF capacitor. 4 V DD Power-Supply Input. Connect to an 8V to 3.25V supply or connect to when using a 3V to 5.5V supply. Bypass V DD with a 0.0µF capacitor to ground. 5 UVP OVP 9 CS- 0 CS+ Pin Description Undervoltage-Protection Input. Connect UVP to the center of a resistor-divider from CS+ to GND. Connect UVP to to disable the undervoltage protection. Timer Input. Connect a resistor from to GND to select the charge-pump operating frequency. Drive low (< 0.5V) to disable the gate drive. Drive high (above.5v) for charge-pump operation at 550kHz. Open-Drain Fault Output. is high impedance during normal operation and is pulled to GND when a fault condition occurs. Connect a pullup resistor of 0kΩ or higher value (50kΩ typ) to a voltage rail of 5.5V or lower. Overvoltage-Protection Input. Connect OVP to the center of a resistor-divider from the output bus to GND. Connect OVP to GND to disable the overvoltage protection. Current-Sensing Input. Connect CS- to the positive side of the system bus. Bypass with a 000pF capacitor to GND. Current-Sensing Input. Connect CS+ to the positive side of the input power. Bypass with a 000pF capacitor to GND. 8

9 CLK GATE CHARGE PUMP SHUTDOWN VOLTAGE SHARE 00mV (50mV) CS+ 40mV (20mV) CS- 0mV REVERSE CURRENT CONTROL LOGIC FORWARD CURRENT OVERVOLTAGE INTERNAL OVERVOLTAGE EXTERNAL 4.5V UNDERVOLTAGE OVP 0.5V I OSC.25V REF ENABLE UVP MAX8555/ (MAX8555A) REGULATOR 0.4V V DD GND Figure. Functional Diagram 9

10 CS- + 0mV CS- CS- - 40mV/20mV CS- - 00mV/50mV V SHARE LATCH SET CS+ 4.ms I FORWARD I REVERSE V CC > V CCOK STANDBY: CPMP: OFF GATE: LOW WAIT FOR V SHARE > V ALL TRANSITIONS ARE ASYNCHRONOUS CS- - CS+ > 0.V State Diagram V SHARE = ((CS-) - CS+) < 0.V/0.05V I FORWARD = ((CS+) - CS-) > 0.0V I REVERSE = ((CS-) -CS+ ) > 40mV/20mV CS- - CS+ < 0.V UVP SHUTDOWN GATE NOT LATCHED UVP UVP-OK ON: SET V SHARE LATCH, CHARGE PUMP ON I FORWARD and OVP Fault OVP OK AND I REVERSE DURING FIRST 4.ms SHUTDOWN GATE LATCHED V CC OR CYCLED UVP = OK I REVERSE CONDITION DETECTED AFTER 4.ms BLANK TIME V DD OR CYCLED SHUTDOWN GATE: LATCHED 0

11 General Description Critical loads often employ parallel-connected power supplies with redundancy to enhance system reliability. The are highly integrated, inexpensive MOSFET controllers that provide isolation and redundant power capability in high-reliability systems. The are used in 0.5V to 3.3V systems, and have an internal charge pump to drive the gates of the N-channel pass elements to V CS+ + 5V. During startup, the monitor the voltage drop across the external MOSFETs. Once V CS+ approaches or exceeds the bus voltage (V CS- ), the MOSFETs are turned on. The feature a dual-purpose input. A single external resistor from to ground sets the turn-on speed of the external MOSFETs. Optionally, the input can be used as a logic enable input. Once the external MOSFET is turned on, these controllers monitor the load, protecting the bus against overvoltage, undervoltage, and reverse-current fault conditions. The MAX8555 is available with a 40mV reverse-current threshold, while the MAX8555A is available with a 20mV reverse-current threshold. Overvoltage and undervoltage fault thresholds are adjustable and can be disabled. The current-limit trip points are set by the external MOSFETs R DS(ON), reducing component count. An open-drain, logic-low fault output indicates if an overvoltage, undervoltage, or reverse-current fault occurs. The MAX8555 and the MAX8555A can shut down in response to a reversecurrent fault condition as quickly as 200ns. V DD V DD is the power-supply input for the MAX8555/ MAX8555A and the input to the internal preregulator. Bypass V DD to GND with a 0.0µF capacitor. The input supply range for V DD is 8V to 3.25V. The internal charge pump is disabled for input voltages above 4.4V (typ). For 3V to 5.5V input voltages, connect V DD to. is the regulated power supply for the. The monitor at all times. During startup the device turns on when rises above OK (2.82V typ). After V exceeds OK and V CS+ is typically greater than (V CS- - 00mV), the charge pump turns on and drives GATE high, turning on the external MOSFETs. For operation from 3V to 5.5V input supplies, connect to V DD. GATE is the output of the internal charge pump that drives the external MOSFETS. During startup, the voltage at GATE ramps up according to the charge-pump frequency. At 250kHz, the GATE drive current for the is 2µA. Increasing the chargepump frequency increases the GATE drive current. To change charge-pump frequency, change the value of R. See the Selecting the Resistor section. CS+, CS- The voltage drop across the external MOSFETs is measured between the CS+ and CS- inputs. CS+ connects to the positive side of the input voltage. CS- connects to the positive side of the system bus. The MAX8555/ MAX8555A use the voltage drop across CS+ and CS- to determine operating mode. I FORWARD is defined as V CS+ - V CS- and must be greater than 0.0V (typ) to properly detect an overvoltage fault condition. I REVERSE is defined as V CS- - V CS+ and must be greater than 0.02V (MAX8555A) or 0.04V (MAX8555) (typ) for a reverse-current fault. The I FORWARD and I REVERSE thresholds can be effectively increased by placing an external divider such as R8 and R9 as shown in Figure 4. The values shown increase the thresholds by 50%. When R8 and R9 are used, also add R0 (a parallel combination of R8 and R9) to eliminate any input offset errors caused by impedance differences and input-bias-current differences. Fault Conditions The have an open-drain output that signals overvoltage, undervoltage, or reverse-current fault conditions. During a fault condition, is pulled to GND, the charge pump shuts down, and GATE discharges to CS- in 200ns (typ). See Table for fault modes. Undervoltage Fault The turn off the external MOSFETs if V UVP falls below the UVP threshold (0.4V). Connect UVP to the center of a resistor-divider from the input supply to GND. Once V UVP rises above the UVP rising threshold (0.5V), clears and GATE is driven high. is not latched. Connect UVP to to disable the undervoltage-protection feature. Overvoltage Fault The are protected from overvoltage conditions using an adjustable overvoltage-protection input. A resistor-divider from the output bus to GND with OVP connected to the center tap sets the overvoltage threshold. When V OVP exceeds the OVP threshold (0.5V) and the device is in the I FORWARD condition

12 Table. Fault Modes OVP MODE CONDITIONS GATE LATCHING UO < OK LOW High Impedance NO UVP Undervoltage Protection OVP Overvoltage Protection Reverse-Current Protection R2B 6.04kΩ R2A 47kΩ 50pF R5 2.87kΩ R6 kω 50pF SYSTEM BUS R2A 47kΩ R2B 6.04kΩ Figure 2. OVP Connection when Multiple MAX8555s Are Used (defined as V CS+ > V CS V), the MAX8555/ MAX8555A discharge GATE to GND and is latched low. If the I FORWARD condition is not detected, OVP is disabled. In redundant systems, when one input supply approaches its OVP threshold, some of the other input supplies may be pulled up with it, thereby tripping those OVP comparators with a slightly lower set point. The I FORWARD condition for the pulled-up supplies may not be detected until the first supply is shut down. An alternate application schematic for and OVP is shown in Figure 2. The output of the first channel, which has both OVP and I FORWARD conditions, temporarily reduces the common OVP signal by 25mV. This ensures that only the input supply, which is causing the overvoltage condition, is turned off in a redundant power-system application. Exceeding the OVP threshold causes the MAX8555/ MAX8555A to be latched off. Toggle V DD or to reset the IC. Connect OVP to GND to disable the overvoltage-protection feature. V UVP < 0.4V LOW LOW NO V OVP > 0.5V V CS+ > V CS V V CS+ < V CS V (0.02V for MAX8555A) and GATE is on for > 2048 charge-pump cycles OVP LOW LOW YES LOW LOW YES V DD Internal Overvoltage Protection V DD > 4.5V LOW LOW NO Reverse-Current Fault The provide a reverse-current fault-protection feature that turns off the oring MOSFET when a reverse-current fault condition is detected. Once a reverse-current fault condition is detected, the discharge GATE to GND and latch low. Toggle V DD,, or to reset the IC. The reverse-current-protection feature is blanked for 2048 charge-pump cycles at startup. Selecting the Resistor Connect a resistor from to GND to set the internal charge pump s frequency of operation. Determine the resistor with the following equation: 25. V R = f 00µ A 5kHz/ µ A Drive above.5v for the maximum chargepump frequency (550kHz). Drive below 0.5V to disable the charge pump and shut down the MAX8555/ MAX8555A. Selecting the GATE Capacitor and GATE Resistor The charge pump uses an internal monolithic transfer capacitor to charge the external MOSFET gates. Normally, the external MOSFET s gate capacitance is sufficient to serve as a reservoir capacitor. To slow down turn-on times further, add a small capacitor between GATE and GND. Adding a small resistor between GATE and the gate of the Oring MOSFET reduces the high-frequency ringing due to gate trace inductance. However, the resistor increases the turn-off time. 2

13 INPUT SUPPLY OUT+ R3 5kΩ R4 0kΩ C 000pF C4 0.0µF 2V C2 0.0µF CS+ V DD UVP Q GATE R 2Ω MAX8555/ MAX8555A R7 24.9kΩ Q2 GND CS- OVP C3 000pF Applications Information R5 5kΩ R6 0kΩ OUTPUT:.5V/20A R2 5kΩ +VO OUTPUT BUS -VO OUT- Figure 3. Application Circuit for 2V IC Supply Voltage R8 kω R9 2kΩ OUT+ Q Q2 OUTPUT:.5V/20A +VO -VO R3 5kΩ C4 000pF C 0.0µF R 2Ω R0 665Ω C3 000pF R5 5kΩ R2 5kΩ INPUT SUPPLY 5V CS+ GATE CS- OUTPUT BUS V DD UVP MAX8555/ MAX8555A OVP R4 0kΩ C2 0.0µF R7 24.9kΩ GND R6 0kΩ OUT- Figure 4. Application Circuit for 5V IC Supply Voltage 3

14 Set the UVP Fault Threshold Use a resistor-divider from the input supply to GND with the center tap connected to UVP to set the undervoltage threshold. Use a 0kΩ resistor from UVP to GND (R4 in Figure 4) and calculate R3 as follows: V R R UV 3 = 4 VUVP where V UV is the desired undervoltage trip point and V UVP is the UVP reference threshold (0.4V typ). Connect UVP to to disable the undervoltage-protection feature. Set the OVP Fault Threshold For a single-supply application, use a resistor-divider from the output bus to GND with the center tap connected to OVP to set the overvoltage threshold. Use a 0kΩ resistor from OVP to GND (R6 in Figure 4) and calculate R5 as follows: V R R OV 5 = 6 VOVP where V OV is the desired overvoltage threshold and V OVP is the OVP reference threshold (0.5V typ). Connect OVP to GND to disable the overvoltage-protection feature. For (n + ) applications, the required circuit values are: R6= kω V R R OV 5= 6 VOVP RA 2 = 47kΩ RB 2 = 2 R5 where the resistors are as shown in Figure 2. MOSFET Selection The drive N-channel MOSFETs. The most important specification of the MOSFETs is R DS(ON). As load current flows through the external MOSFET, V DS is generated from source to drain due to the MOSFET s on-resistance, R DS(ON). The MAX8555/ MAX8555A monitor V DS of the MOSFETs at all times to determine the state of the monitored power supply. Selecting a MOSFET with a low R DS(ON) allows more current to flow through the MOSFETs before the detect reverse-current (I REVERSE ) and forward-current (I FORWARD ) conditions. Using Two MOSFETs Two MOSFETs must be used for overvoltage protection. When using two external MOSFETs, the monitored voltage equation becomes: V DSTOTAL = R DS(ON) x I LOAD + R DS(ON)2 x I LOAD Using One MOSFET A single MOSFET can be used if the overvoltage-protection function is not needed. Connect CS+ to the source of the MOSFET and CS- to the drain of the MOSFET. Calculating GATE Current The charge-pump output current is proportional to both oscillator frequency and V. There is also a small internal load of approximately 6MΩ. The GATE current for a given V and R is calculated as: V I L GATE A ( 08. ) 2, 500 R µ 34. Layout Guidelines It is important to keep all traces as short as possible and to maximize the high-current trace dimensions to reduce the effect of undesirable parasitic inductance. The MOSFET dissipates a fair amount of heat due to the high currents involved, especially during an overcurrent condition. To dissipate the heat generated by the MOSFET, make the power traces very wide with a large amount of copper area and place the MAX8555 as close as possible to the drain of the external MOS- FET. A more efficient way to achieve good power dissipation on a surface-mount package is to lay out two copper pads directly under the MOSFET package on both sides of the board. Use enlarged copper mounting pads on the top side of the board. Use a ground plane to minimize impedance and inductance. In addition to the usual high-power considerations, here are three tips to prevent false faults: ) Kelvin connect CS+ and CS- to the external MOSFET and route the two traces in parallel, as close as possible, back to the IC. 2) Bypass V DD with a 0.0µF capacitor to ground and bypass CS+ and CS- with a 000pF capacitor to ground. 3) Make the traces connected to UVP and OVP as short as possible. Refer to the evaluation kit for an example of good PC board layout. 4

15 INPUT SUPPLY OUT+ 8V TO 3.25V CS+ V DD UVP GATE MAX8555/ MAX8555A GND CS- OVP Typical Operating Circuit OUTPUT:.5V AT 20A +VO OUTPUT BUS -VO OUT- Chip Information TRANSISTOR COUNT: 2309 PROCESS: BiCMOS 5

16 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to PIN INDEX AREA D E A A A2 L DETAIL A E2 LC b e N C0.35 D2 L C k L L PIN ID [(N/2)-] x e REF. 6, 8, &0L, DFN THIN.EPS e e A DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY TITLE: PACKAGE OUTLINE, 6, 8 & 0L, TDFN, EXPOSED PAD, 3x3x0.80 mm APPROVAL DOCUMENT CONTROL NO. REV D 2 COMMON DIMENSIONS SYMBOL MIN. MAX. A D E A L k 0.25 MIN. A REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-] x e T ± ± BSC MO229 / WEEA 0.40± REF T ± ± BSC MO229 / WEEC 0.30± REF T ± ± BSC MO229 / WEED ± REF PROPRIETARY INFORMATION TITLE: APPROVAL DALLAS SEMICONDUCTOR PACKAGE OUTLINE, 6, 8 & 0L, TDFN, EXPOSED PAD, 3x3x0.80 mm DOCUMENT CONTROL NO REV. D 2 2 6

17 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 0.6±0. 0 e ÿ 0.50±0. 0.6±0. TOP VIEW 4X S H BOTTOM VIEW 0 DIM A A MIN MAX MIN MAX A D D2 E E2 H L L b e c S α INCHES MILLIMETERS REF REF BSC BSC REF REF LUMAX.EPS D2 E2 GAGE PLANE A2 A c D b A α E L L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 0L umax/usop APPROVAL DOCUMENT CONTROL NO. REV I Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.