Maxim Integrated Products 1

Transcription

1 ; Rev ; 7/4 EVAUATION KIT AVAIABE 256-Tap, Nonvolatile, SPI-Interface, General Description The nonvolatile, lineartaper, digital potentiometers perform the function of a mechanical potentiometer, but replace the mechanics with a simple 3-wire SPI -compatible digital interface. Each device performs the same function as a discrete potentiometer or variable resistor and has 256 tap points. The devices feature an internal, nonvolatile EEPROM used to store the wiper position for initialization during power-up. The 3-wire SPI-compatible serial interface allows communication at data rates up to 5Mz, minimizing board space and reducing interconnection complexity in many applications. The provide three nominal resistance values: 5kΩ (), 1kΩ (MAX5423), or 2kΩ (MAX5424). The nominal resistor temperature coefficient is 35ppm/ C end-to-end and only 5ppm/ C ratiometric. This makes the devices ideal for applications requiring a low-temperature-coefficient variable resistor, such as low-drift, programmable gainamplifier circuit configurations. The are available in a 3mm x 3mm 8-pin TDFN package, and are specified over the extended -4 C to +85 C temperature range. V DD GND CS SCK DIN Applications Mechanical Potentiometer Replacement ow-drift Programmable Gain Amplifiers Audio Volume Control iquid-crystal Display (CD) Contrast Control ow-drift Programmable Filters 8-BIT SIFT REGISTER SPI INTERFACE BIT POSITION ATC DECODER POR Functional Diagram 8-BIT NV MEMORY MAX5423 MAX5424 Features iper Position Stored in Nonvolatile Memory (EEPROM) and Recalled Upon Power-Up or Interface Command 3mm x 3mm x.8mm TDFN Package 35ppm/ C End-to-End Resistance Temperature Coefficient 5ppm/ C Ratiometric Temperature Coefficient 5kΩ, 1kΩ, and 2kΩ Resistor Values 5Mz SPI-Compatible Serial Interface 5nA (typ) Static Supply Current Single-Supply Operation: +2.7V to +5.25V 256 Tap Positions ±.5 SB DN in Voltage-Divider Mode ±.5 SB IN in Voltage-Divider Mode SPI is a trademark of Motorola, Inc. TOP VIE V DD SCK DIN CS 1 Pin Configuration 2 3 MAX5423 MAX TDFN (3mm x 3mm) Ordering Information/Selector Guide 8 GND PART TEMP RANGE END-TO-END RESISTANCE (kω) PIN-PACKAGE TOP MARK ETA -4 C to +85 C 5 8 TDFN-EP* AIJ MAX5423ETA -4 C to +85 C 1 8 TDFN-EP* AII MAX5424ETA -4 C to +85 C 2 8 TDFN-EP* AI *EP = Exposed pad. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOUTE MAXIMUM RATINGS V DD to GND...-.3V to +6.V All Other Pins to GND...-.3V to (V DD +.3V) Maximum Continuous Current into,, and...±1.3ma MAX ±.6mA MAX ±.3mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EECTRICA CARACTERISTICS Continuous Power Dissipation (T A = +7 C) 8-Pin TDFN (derate 24.4m/ C above +7 C) m Operating Temperature Range...-4 C to +85 C Junction Temperature C Storage Temperature Range...-6 C to +15 C ead Temperature (soldering, 1s)...+3 C (V DD = +2.7V to +5.25V, = V DD, = GND, T A = -4 C to +85 C. Typical values are at V DD = +5.V, T A = +25 C, unless otherwise noted.) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS DC PERFORMANCE (VOTAGE-DIVIDER MODE) Resolution N 256 Taps Integral Nonlinearity IN (Note 1) ±.5 SB Differential Nonlinearity DN (Note 1) ±.5 SB End-to-End Resistance Temperature Coefficient Ratiometric Resistance Temperature Coefficient Full-Scale Error Zero-Scale Error DC PERFORMANCE (VARIABE-RESISTOR MODE) Integral Nonlinearity (Note 2) TC R 35 ppm/ C IN -.6 MAX MAX MAX MAX ppm/ C V DD = 3V ±3. V DD = 5V ±1.5 V DD = 3V,, -4 C T A +85 C, guaranteed monotonic SB SB SB Differential Nonlinearity (Note 2) DN DC PERFORMANCE (RESISTOR CARACTERISTICS) V DD = 3V,, C T A +85 C, guaranteed monotonic V DD = 3V, MAX5423 ±1. V DD = 3V, MAX5424 ±1. V DD = 5V ±1. iper Resistance R V DD = 3V to 5.25V (Note 3) Ω iper Capacitance C 1 pf End-to-End Resistance MAX MAX SB kω 2

3 EECTRICA CARACTERISTICS (continued) (V DD = +2.7V to +5.25V, = V DD, = GND, T A = -4 C to +85 C. Typical values are at V DD = +5.V, T A = +25 C, unless otherwise noted.) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS DIGITA INPUTS (CS, DIN, SCK) Input igh Voltage (Note 4) V I V DD < 3.4V V DD = 3.4V to 5.25V 2.4 Input ow Voltage V I V DD = 2.7V to 5.25V (Note 4).8 V Input eakage Current I IN ±.1 ±1 µa Input Capacitance C IN 5 pf DYNAMIC CARACTERISTICS 1 iper -3dB Bandwidth (Note 5) MAX kz MAX NONVOATIE MEMORY REIABIITY Data Retention T A = +85 C 5 Years Endurance POER SUPPY.7 x V DD T A = +25 C 2, T A = +85 C 5, Supply Voltage V DD V Standby Current I DD Digital inputs = V DD or GND, T A = +25 C.5 1 µa Programming Current I PG During nonvolatile write to memory; digital inputs = V DD or GND (Note 6) V Stores 2 4 µa TIMING CARACTERISTICS (V DD = +2.7V to +5.25V, = V DD, = GND, T A = -4 C to +85 C. Typical values are at V DD = +5.V, T A = +25 C, unless otherwise noted. See Figure 1.) (Note 7) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS ANAOG SECTION 4 iper Settling Time (Note 8) t S MAX MAX ns DIGITA SECTION SCK Frequency f SCK 5 Mz SCK Clock Period t CP 2 ns SCK Pulse-idth igh t C 8 ns SCK Pulse-idth ow t C 8 ns CS Fall to SCK Rise Setup t CSS 8 ns SCK Rise to CS Rise old t CS ns DIN to SCK Setup t DS 5 ns 3

4 TIMING CARACTERISTICS (continued) (V DD = +2.7V to +5.25V, = V DD, = GND, T A = -4 C to +85 C. Typical values are at V DD = +5.V, T A = +25 C, unless otherwise noted. See Figure 1.) (Note 7) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS DIN old after SCK t D ns SCK Rise to CS Fall Delay t CS 2 ns CS Rise to SCK Rise old t CS1 8 ns CS Pulse-idth igh t CS 2 ns rite NV Register Busy Time t BUSY 12 ms Note 1: The DN and IN are measured with the potentiometer configured as a voltage-divider with = V DD and = GND. The wiper terminal is unloaded and measured with a high-input-impedance voltmeter. Note 2: The DN and IN are measured with the potentiometer configured as a variable resistor. is unconnected and = GND. For the 5V condition, the wiper terminal is driven with a source current of 8µA for the 5kΩ configuration, 4µA for the 1kΩ configuration, and 2µA for the 2kΩ configuration. For the 3V condition, the wiper terminal is driven with a source current of 4µA for the 5kΩ configuration, 2µA for the 1kΩ, and 1µA for the 2kΩ configuration. Note 3: The wiper resistance is measured using the source currents given in Note 2. For operation to V DD = 2.7V, see Maximum iper Resistance vs. Temperature in the Typical Operating Characteristics. Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (V DD -.5V) and (GND +.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 5: iper at midscale with a 1pF load (DC measurement). = GND; an AC source is applied to ; and the output is measured. A 3dB bandwidth occurs when the AC / value is 3dB lower than the DC / value. Note 6: The programming current operates only during power-up and NV writes. Note 7: Digital timing is guaranteed by design and characterization, and is not production tested. Note 8: iper-settling time is the worst-case % to 5% rise-time measured between consecutive wiper positions. = V DD, = GND, and the wiper terminal is unloaded and measured with a 1pF oscilloscope probe. (V DD = 5.V, T A = +25 C, unless otherwise noted.) Typical Operating Characteristics DN vs. VOTAGE-DIVIDER MODE toc IN vs. VOTAGE-DIVIDER MODE toc2 7 6 IPER RESISTANCE vs. V DD = 2.7V I SRC = 5μA toc DN (SB) IN (SB) RESISTANCE (Ω)

5 Typical Operating Characteristics (continued) (V DD = 5.V, T A = +25 C, unless otherwise noted.) IPER TRANSIENT AT POER-ON 4μs/div RESISTANCE (Ω) toc4 C = 1pF TAP = 128 = V DD V DD 1V/div 1V/div END-TO-END RESISTANCE % CANGE MAXIMUM IPER RESISTANCE vs. TEMPERATURE V DD = 2.7V V DD = 3.V V DD = 4.5V V DD = 5.25V END-TO-END RESISTANCE % CANGE vs. TEMPERATURE TEMPERATURE ( C) toc7 SUPPY CURRENT (µa) toc5 SUPPY CURRENT (μa) STANDBY SUPPY CURRENT vs. TEMPERATURE V DD = 5.25V.5.4 V DD = 4.V.3.2 V DD = 3.V.1 V DD = 2.7V TEMPERATURE ( C) SUPPY CURRENT vs. DIGITA INPUT VOTAGE toc8 toc6 TD+N (%) TEMPERATURE ( C) TD+N RESPONSE 1:1 RATIO 2z TO 2kz BANDPASS k 1k 1k FREQUENCY (z) toc9 IN (SB) DIGITA INPUT VOTAGE (V) IN vs. () VARIABE-RESISTOR MODE V DD = 2.7V I SRC = 5μA toc1 5

6 Typical Operating Characteristics (continued) (V DD = 5.V, T A = +25 C, unless otherwise noted.) IN (SB) IN vs. (MAX5423) VARIABE-RESISTOR MODE V DD = 2.7V I SRC = 2μA DN (SB) toc11 IN (SB) DN vs. (MAX5423) VARIABE-RESISTOR MODE IN vs. (MAX5424) VARIABE-RESISTOR MODE V DD = 2.7V I SRC = 1μA toc14 DN (SB) toc12 DN (SB) DN vs. () VARIABE-RESISTOR MODE DN vs. (MAX5424) VARIABE-RESISTOR MODE toc15 toc

7 PIN NAME FUNCTION 1 V DD Power-Supply Input. Bypass V DD with a.1µf capacitor from V DD to GND. 2 SCK Serial-Interface Clock Input 3 DIN Serial-Interface Data Input 4 CS Active-ow Digital-Input Chip Select 5 GND Ground 6 ow Terminal. The voltage at can be greater than or less than the voltage at. Current can flow into or out of. 7 iper Terminal 8 igh Terminal. The voltage at can be greater than or less than the voltage at. Current can flow into or out of. EP Exposed Pad. The exposed pad is not internally connected. Connect to GND or leave floating. CS SCK t CS t CSS t DS t C t D t C Pin Description t CS t CP t CS t CS1 DIN Figure 1. Digital Interface and Timing Diagram Detailed Description The contain a resistor array with 255 resistive elements. The has a total end-to-end resistance of 5kΩ; the MAX5423 has an end-to-end resistance of 1kΩ; and the MAX5424 has an end-to-end resistance of 2kΩ. The allow access to the high, low, and wiper terminals for a standard voltage-divider configuration.,, and can be connected in any desired configuration as long as their voltages fall between GND and V DD. A simple, 3-wire, SPI serial interface moves the wiper among the 256 tap points. The nonvolatile memory stores the wiper position and recalls the stored wiper position upon power-up. The nonvolatile memory is guaranteed for 5 years for wiper data retention and up to 2, wiper store cycles. Analog Circuitry The consist of a resistor array with 255 resistive elements; 256 tap points are accessible to the wiper,, along the resistor string between and. Select the wiper tap point by programming the potentiometer through the 3-wire (SPI) interface. Eight data bits, and a control byte program the wiper position. The and terminals of the are similar to the two end terminals of a mechanical potentiometer. The feature power-on reset circuitry that loads the wiper position from the nonvolatile memory at power-up. Digital Interface The use a 3-wire, SPIcompatible, serial data interface (Figure 1 and 2). This write-only interface contains three inputs: chip-select 7

8 (CS), data clock (SCK), and data in (DIN). Drive CS low to enable the serial interface and clock data synchronously into the shift register on each SCK rising edge. The RITE commands (C1, C = or 1) require 16 clock cycles to clock in the command and data (Figure 2a). The COPY commands (C1, C = 1, 11) can use either eight clock cycles to transfer the command bits (Figure 2b) or 16 clock cycles with 8 data bits that are disregarded by the device (Figure 2a). Table 1. Register Map After loading data into the shift register, drive CS high to latch the data into the appropriate potentiometer control register and disable the serial interface. Keep CS low during the entire serial-data stream to avoid corruption of the data. The serial-data timing for the potentiometer is shown in Figures 1 and 2. COCK EDGE Bit name C1 C D7 D6 D5 D4 D3 D2 D1 D rite wiper register D7 D6 D5 D4 D3 D2 D1 D rite NV register 1 D7 D6 D5 D4 D3 D2 D1 D Copy wiper register to NV register Copy NV register to wiper register A) 16-BIT COMMAND/DATA ORD CS SCK DIN C1 C D7 D6 D5 D4 D3 D2 D1 D B) 8-BIT COMMAND ORD CS SCK DIN C1 C Figure 2. Digital-Interface Format 8

9 rite iper Register Data written to this register (C1, C = ) controls the wiper positions. The 8 data bits (D7 to D) indicate the position of the wiper. For example, if DIN =, the wiper moves to the position closest to. If DIN = , the wiper moves closest to. This command writes data to the volatile random access memory (RAM), leaving the NV registers unchanged. hen the device powers up, the data stored in the NV registers transfers to the volatile wiper register, moving the wiper to the stored position. rite NV Register The write NV register command (C1, C = 1) stores the position of the wipers to the NV registers for use at power-up. Alternatively, the copy wiper register to NV register command writes to the NV register. riting to the NV registers, does not affect the position of the wipers. Copy iper Register to NV Register The copy wiper register to NV register command (C1, C = 1) stores the current position of the wiper to the NV register for use at power-up. Copy NV Register to iper Register The copy NV register to wiper register (C1, C = 11) restores the wiper position to the current value stored in the NV register. Standby Mode The feature a low-power standby mode. hen the device is not being programmed, it enters into standby mode and supply current drops to.5µa (typ). Nonvolatile Memory The internal EEPROM consists of a nonvolatile register that retains the last value stored prior to power-down. The nonvolatile register is programmed to midscale at the factory. The nonvolatile memory is guaranteed for 5 years for wiper data retention and up to 2, wiper write cycles. Power-Up Upon power-up, the load the data stored in the nonvolatile wiper register into the volatile wiper register, updating the wiper position with the data stored in the nonvolatile wiper register. This initialization period takes 1µs. Applications Information The are intended for circuits requiring digitally controlled adjustable resistance, such as CD contrast control (where voltage biasing adjusts the display contrast), or programmable filters with adjustable gain and/or cutoff frequency. Positive CD Bias Control Figures 3 and 4 show an application where a voltagedivider or variable resistor is used to make an adjustable, positive CD-bias voltage. The op amp provides buffering and gain to the resistor-divider network made by the potentiometer (Figure 3) or to a fixed resistor and a variable resistor (see Figure 4). 5V 5V 3V 3V MAX5423 MAX5424 V OUT MAX5423 MAX5424 V OUT Figure 3. Positive CD-Bias Control Using a Voltage-Divider Figure 4. Positive CD-Bias Control Using a Variable Resistor 9

10 Programmable Filter Figure 5 shows the configuration for a 1st-order programmable filter. The gain of the filter is adjusted by R2, and the cutoff frequency is adjusted by R3. Use the following equations to calculate the DC gain (G) and the 3dB cutoff frequency (f C ): V IN MAX5423 MAX5424 R1 G = 1 + R2 1 fc = 2π R3 C C R3 R2 R1 V OUT Adjustable Voltage Reference Figure 6 shows the used as the feedback resistors in an adjustable voltage-reference application. Independently adjust the output voltage of the MAX616 from 1.23V to VIN -.2V by changing the wiper position of the / MAX5423/MAX5424. Offset Voltage and Gain Adjustment Connect the high and low terminals of one potentiometer of a between the NU inputs of a MAX41 and the wiper to the op amp s positive supply to nullify the offset voltage over the operating temperature range. Install another potentiometer in the feedback path to adjust the gain of the MAX41 (see Figure 7) V 1 MAX41 4-5V 8 6 Figure 5. Programmable Filter Figure 7. Offset Voltage Adjustment Circuit +5V Chip Information TRANSISTOR COUNT: 1,191 V IN OUT V REF PROCESS: BiCMOS MAX616 ADJ MAX5423 MAX5424 GND V = 1.23V 5kΩ FOR TE R 2 (kω) V = 1.23V 1kΩ FOR TE MAX5423 R 2 (kω) V = 1.23V 2kΩ FOR TE MAX5424 R 2 (kω) Figure 6. Adjustable Voltage Reference 1

11 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 6, 8, &1, DFN TIN.EPS COMMON DIMENSIONS SYMBO MIN. MAX. A.7.8 D E A k.25 MIN. A2.2 REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e T ±.1 2.3±.1.95 BSC MO229 / EEA.4± REF T ±.1 2.3±.1.65 BSC MO229 / EEC.3± REF T ±.1 2.3±.1.65 BSC MO229 / EEC.3± REF T ±.1 2.3±.1.5 BSC MO229 / EED-3.25±.5 2. REF T133-2 T ±.1 1.7±.1 2.3±.1 T ±.1 2.3±.1 2.3±.1.5 BSC MO229 / EED-3.25±.5 2. REF.4 BSC ± REF.4 BSC ± REF Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

12 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & ifecycle Information: Maxim Integrated: ETA+T MAX5423ETA+T MAX5424ETA+T MAX5417PETA+