10-Bit, Nonvolatile, Linear-Taper Digital Potentiometers

Transcription

1 19-378; Rev 3; 4/7 1-Bit, Nonvolatile, inear-taper Digital General Description The 1-bit (124-tap) nonvolatile, linear-taper, programmable voltage-dividers and variable resistors perform the function of a mechanical potentiometer, but replace the mechanics with a pinconfigurable 3-wire serial SPI -compatible interface or up/down digital interface. The MAX5481/MAX5482 are 3-terminal voltage-dividers and the MAX5483/MAX5484 are 2-terminal variable resistors. The feature an internal, nonvolatile, electrically erasable programmable read-only memory (EEPROM) that stores the wiper position for initialization during power-up. The 3-wire SPI-compatible serial interface allows communication at data rates up to 7MHz. A pin-selectable up/down digital interface is also available. The are ideal for applications requiring digitally controlled potentiometers. Two end-toend resistance values are available (1kΩ and 5kΩ) in a voltage-divider or a variable-resistor configuration (see the Selector Guide). The nominal resistor temperature coefficient is 35ppm/ C end-to-end, and only 5ppm/ C ratiometric, making these devices ideal for applications requiring low-temperature-coefficient voltage-dividers, such as low-drift, programmable gain-amplifiers. The operate with either a +2.7V to +5.25V single power supply or ±2.5V dual power supplies. These devices consume 4µA (max) of supply current when writing data to the nonvolatile memory and 1.µA (max) of standby supply current. The are available in a space-saving (3mm x 3mm), 16-pin TQFN, or a 14-pin TSSOP package and are specified over the extended (-4 C to +85 C) temperature range. Gain and Offset Adjustment CD Contrast Adjustment Pressure Sensors Applications ow-drift Programmable Gain Amplifiers Mechanical Potentiometer Replacement Ordering Information PART PIN-PACKAGE PKG TOP MARK MAX5481ETE 16 TQFN-EP* T1633F-3 ACP MAX5481EUD 14 TSSOP U14-1 Note: All devices are specified over the -4 C to +85 C operating temperature range. *EP = Exposed pad. Ordering Information continued at end of data sheet. Features 124 Tap Positions Power-On Recall of iper Position from Nonvolatile Memory 16-Pin (3mm x 3mm x.8mm) TQFN or 14-Pin TSSOP Package 35ppm/ C End-to-End Resistance Temperature Coefficient 5ppm/ C Ratiometric Temperature Coefficient 1kΩ and 5kΩ End-to-End Resistor Values Pin-Selectable SPI-Compatible Serial Interface or Up/Down Digital Interface 1µA (max) Standby Current Single +2.7V to +5.25V Supply Operation Dual ±2.5V Supply Operation TOP VIE GND V DD V SS H *SEE FUNCTIONA DIAGRAM GND V DD V SS D. SCK(INC) INTERFACE 3 TQFN SCK(INC) 11 2 Pin Configurations 1 3 SPI/UD 9 MAX5481* MAX5482* INTERFACE TQFN 4 SPI/UD 9 MAX5483 MAX Selector Guide appears at end of data sheet. SPI is a trademark of Motorola, Inc V SS V SS Pin Configurations continued at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 1-Bit, Nonvolatile, inear-taper Digital ABSOUTE MAXIMUM RATINGS V DD to GND...-.3V to +6.V V SS to GND V to +.3V V DD to V SS...-.3V to +6.V H,, to V SS...(V SS -.3V) to (V DD +.3V), SCK(INC),, SPI/UD to GND..-.3V to (V DD +.3V) Maximum Continuous Current into H,, and MAX5481/MAX ±5mA MAX5482/MAX ±1.mA Maximum Current into Any Other Pin...±5mA Continuous Power Dissipation (T A = +7 C) 16-Pin TQFN (derate 17.5m/ C above +7 C) m 14-Pin TSSOP (derate 9.1m/ C above +7 C)...727m Operating Temperature Range...-4 C to +85 C Junction Temperature C Storage Temperature Range...-6 C to +15 C ead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EECTRICA CHARACTERISTI (V DD = +2.7V to +5.25V, V SS = GND =, V H = V DD, V =, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V DD = +5.V, T A = +25 C, unless otherwise noted.) (Note 1) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS DC PERFORMANCE (MAX5481/MAX5482 programmable voltage-divider) Resolution N 1 Bits Integral Nonlinearity (Note 2) Differential Nonlinearity (Note 2) End-to-End Resistance Temperature Coefficient Ratiometric Resistance Temperature Coefficient Full-Scale Error Zero-Scale Error IN DN V DD = 2.7V ±2 V DD = 5V ±2 V DD = 2.7V ±1 V DD = 5V ±1 TC R 35 ppm/ C FSE ZSE MAX MAX MAX MAX SB SB 5 ppm/ C MAX End-to-End Resistance R H- MAX SB SB kω iper Capacitance C 6 pf Resistance from to and H at code = 15, H and shorted to V SS, measure MAX resistance from to H, Figures 1 and 2 MAX kω DC PERFORMANCE (MAX5483/MAX5484 variable resistor) Resolution N 1 Bits V DD = 2.7V -1.6 Integral Nonlinearity (Note 3) Differential Nonlinearity (Note 3) Variable-Resistor Temperature Coefficient IN_R DN_R V DD = 3V V DD = 5V V DD = 2.7V +.45 V DD = 3V V DD = 5V TC VR V DD = 3V to 5.25V; code = 128 to ppm/ C SB SB 2

3 1-Bit, Nonvolatile, inear-taper Digital EECTRICA CHARACTERISTI (continued) (V DD = +2.7V to +5.25V, V SS = GND =, V H = V DD, V =, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V DD = +5.V, T A = +25 C, unless otherwise noted.) (Note 1) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS Full-Scale iper-to-end MAX kω R Resistance - MAX kω Zero-Scale Resistor Error R Z Code = MAX MAX Ω iper Resistance R V DD 3V (Note 4) 5 Ω iper Capacitance C 6 pf DIGITA INPUTS (, SCK(INC),, SPI/UD) (Note 5) Input-High Voltage V IH Single-supply operation Dual-supply operation Single-supply operation Input-ow Voltage V I Dual-supply operation V DD = +3.6V to +5.25V VDD = +2.7V to +3.6V V DD = +2.5V, V SS = -2.5V V DD = +2.7V to +5.25V V DD = +2.5V, V SS = -2.5V Input eakage Current I IN ±1 µa Input Capacitance C IN 5 pf DYNAMIC CHARACTERISTI iper -3dB Bandwidth Total Harmonic Distortion NONVOATIE MEMORY REIABIITY THD x V DD iper at code = 1111 MAX , C = 1pF MAX V DD = 3V, wiper at code = , 1V RMS at 1kHz is applied at H, 1pF load on 2. MAX MAX Data Retention T A = +85 C 5 Years Endurance POER SUPPY T A = +25 C 2, T A = +85 C 5, Single-Supply Voltage V DD V SS = GND = V Dual-Supply Voltage V DD GND = V SS V DD - V SS 5.25V Average Programming Current I PG During nonvolatile write; digital inputs = V DD or GND Peak Programming Current During nonvolatile write only; digital inputs = V DD or GND.8.6 V V khz % Stores V 22 4 µa 4 ma Standby Current I DD Digital inputs = V DD or GND, T A = +25 C.6 1 µa 3

4 1-Bit, Nonvolatile, inear-taper Digital TIMING CHARACTERISTI (V DD = +2.7V to +5.25V, V SS = GND =, V H = V DD, V =, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V DD = +5.V, T A = +25 C, unless otherwise noted.) (Note 1) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS ANAOG SECTION MAX iper Settling Time (Note 6) t S MAX SPI-COMPATIBE SERIA INTERFACE (Figure 3) SCK Frequency f SCK 7 MHz SCK Clock Period t CP 14 ns SCK Pulse-idth High t CH 6 ns SCK Pulse-idth ow t C 6 ns Fall to SCK Rise Setup t S 6 ns SCK Rise to Rise Hold t H ns DIN to SCK Setup t DS 4 ns DIN Hold after SCK t DH ns SCK Rise to Fall Delay t 15 ns Rise to SCK Rise Hold t 1 6 ns Pulse-idth High t 15 ns rite NV Register Busy Time t BUSY 12 ms UP/DON DIGITA INTERFACE (Figure 8) to INC Setup t CI 25 ns INC High to U/D Change t ID 2 ns U/D to INC Setup t DI 25 ns INC ow Period t I 25 ns INC High Period t IH 25 ns INC Inactive to Inactive t IC 5 ns Deselect Time (Store) t CPH 5 ns INC Cycle Time t CYC 5 ns INC Active to Inactive t IK 5 ns iper Store Cycle t SC 12 ms µs Note 1: 1% production tested at T A = +25 C and T A = +85 C. Guaranteed by design to T A = -4 C. Note 2: The DN and IN are measured with the device configured as a voltage-divider with H = V DD and = V SS. The wiper terminal () is unloaded and measured with a high-input-impedance voltmeter. Note 3: The DN_R and IN_R are measured with D. unconnected and = V SS =. For V DD = 5V, the wiper terminal is driven with a source current of I = 8µA for the 5kΩ device and 4µA for the 1kΩ device. For V DD = 3V, the wiper terminal is driven with a source current of 4µA for the 5kΩ device and 2µA for the 1kΩ device. Note 4: The wiper resistance is measured using the source currents given in Note 3. Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (V DD -.5V) and (GND +.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 6: iper settling test condition uses the voltage-divider configuration with a 1pF load on. Transition code from to and measure the time from going high to the wiper voltage settling to within.5% of its final value. 4

5 1-Bit, Nonvolatile, inear-taper Digital (V DD = 5.V, V SS =, T A = +25 C, unless otherwise noted.) DN (SB) DN vs. (MAX5483) V DD = 2.7V MAX5481 toc1 DN (SB) DN vs. (MAX5483) Typical Operating Characteristics V DD = 5V MAX5481 toc2 IN (SB) IN vs. (MAX5483) V DD = 2.7V MAX5481 toc3 IN (SB) IN vs. (MAX5483) V DD = 3V MAX5481 toc4 IN (SB) IN vs. (MAX5483) V DD = 5V MAX5481 toc5 DN (SB) DN vs. (MAX5481) V DD = 2.7V MAX5481 toc DN vs. (MAX5481) V DD = 5V MAX5481 toc IN vs. (MAX5481) V DD = 2.7V MAX5481 toc IN vs. (MAX5481) V DD = 5V MAX5481 toc DN (SB) IN (SB) IN (SB)

6 1-Bit, Nonvolatile, inear-taper Digital Typical Operating Characteristics (continued) (V DD = 5.V, V SS =, T A = +25 C, unless otherwise noted.) DN (SB) DN vs. (MAX5484) V DD = 2.7V MAX5481 toc1 DN (SB) DN vs. (MAX5484) V DD = 5V MAX5481 toc11 IN (SB) IN vs. (MAX5484) V DD = 2.7V MAX5481 toc IN vs. (MAX5484) V DD = 5V MAX5481 toc DN vs. (MAX5482) V DD = 2.7V MAX5481 toc DN vs. (MAX5482) V DD = 5V MAX5481 toc IN (SB) DN (SB) DN (SB) IN (SB) IN vs. (MAX5482) V DD = 2.7V MAX5481 toc16 IN (SB) IN vs. (MAX5482) V DD = 5V MAX5481 toc17 R (Ω) IPER RESISTANCE vs. (VARIABE RESISTOR, T A = -4 C) MAX5481 toc

7 1-Bit, Nonvolatile, inear-taper Digital Typical Operating Characteristics (continued) (V DD = 5.V, V SS =, T A = +25 C, unless otherwise noted.) R (Ω) IPER RESISTANCE vs. (VARIABE RESISTOR, T A = +25 C) MAX5481 toc19 R (Ω) IPER RESISTANCE vs. (VARIABE RESISTOR, T A = +85 C) MAX5481 toc2 R (kω) TO- RESISTANCE vs. (MAX5484) MAX5481 toc21 R (kω) TO- RESISTANCE vs. (MAX5483) MAX5481 toc22 R (Ω) IPER RESISTANCE vs. IPER VOTAGE (VARIABE RESISTOR) V DD = 5V = MAX5481 toc23 END-TO-END RESISTANCE CHANGE (%) END-TO-END (R H ) % CHANGE vs. TEMPERATURE (VOTAGE-DIVIDER) MAX5481 toc IPER VOTAGE (V) TEMPERATURE ( C) IPER-TO-END RESISTANCE CHANGE (%) IPER-TO-END RESISTANCE (R ) % CHANGE vs. TEMPERATURE (VARIABE RESISTOR) = MAX5481 toc25 IDD (µa) STANDBY SUPPY CURRENT vs. TEMPERATURE V DD = 5.25V MAX5481 toc26 IDD (µa) 1, DIGITA SUPPY CURRENT vs. DIGITA INPUT VOTAGE V DD = 5V MAX5481 toc TEMPERATURE ( C) TEMPERATURE ( C) DIGITA INPUT VOTAGE (V) 7

8 1-Bit, Nonvolatile, inear-taper Digital Typical Operating Characteristics (continued) (Circuit of Figure 1, T A = +25 C, unless otherwise noted.) TAP-TO-TAP SITCHING TRANSIENT RESPONSE (MAX5481) 1µs/div MAX5481 toc28 H = V DD, = GND C = 1pF FROM TO 1 2V/div V (AC-COUPED) 2mV/div TAP-TO-TAP SITCHING TRANSIENT RESPONSE (MAX5482) 4µs/div MAX5481 toc29 H = V DD, = GND C = 1pF FROM TO 1 2V/div V (AC-COUPED) 2mV/div -5 IPER RESPONSE vs. FREQUENCY (MAX5481) C = 1pF MAX5481 toc3-5 IPER RESPONSE vs. FREQUENCY (MAX5482) C = 1pF MAX5481 toc THD+N vs. FREQUENCY (MAX5481) C = 1pF MAX5481 toc32 GAIN (db) C = 3pF GAIN (db) C = 3pF THD+N (%) = FREQUENCY (khz) -2 = FREQUENCY (khz) FREQUENCY (khz) THD+N (%) THD+N vs. FREQUENCY (MAX5482) C = 1pF FREQUENCY (khz) MAX5481 toc33 RATIOMETRIC TEMPCO (ppm) RATIOMETRIC TEMPERATURE COEFFICIENT vs. 5kΩ 1kΩ VOTAGE-DIVIDER V DD = +3V T A = -4 C TO +85 C MAX5481 toc34 TCVR (ppm) VARIABE-RESISTOR TEMPERATURE COEFFICIENT vs. 5kΩ 1kΩ V DD = +3V T A = -4 C TO +85 C MAX5481 toc35 8

9 1-Bit, Nonvolatile, inear-taper Digital (MAX5481/MAX5482 Voltage-Dividers) TQFN PIN TSSOP NAME 1 12 H High Terminal 2 11 iper Terminal 3 1 ow Terminal 4 7, 15 7, 8, 9, 13 No Connection. Not internally connected. FUNCTION Pin Description 8, V SS supply operation, -2.5V V SS -.2V as long as (V DD - V SS ) +5.25V. Bypass V SS to GND Negative Power-Supply Input. For single-supply operation, connect V SS to GND. For dual- with a.1µf ceramic capacitor as close to the device as possible. 9 6 SPI/UD 1 5 Interface-Mode Select. Select serial SPI interface when SPI/UD = 1. Select serial up/down interface when SPI/UD =. Serial SPI Interface Data Input (SPI/UD = 1) Up/Down Control Input (SPI/UD = ). ith low, a high-to-low SCK(INC) transition decrements the wiper position. ith high, a high-to-low SCK(INC) transition increments the wiper position. Serial SPI Interface Clock Input (SPI/UD = 1) 11 4 SCK(INC) iper-increment Control Input (SPI/UD = ). ith low, the wiper position moves in the direction determined by the state of on a high-to-low transition Active-ow Digital Input Chip Select 13 2 GND Ground Positive Power-Supply Input (+2.7V V 14 1 V DD +5.25V). Bypass V DD to GND with a.1µf DD ceramic capacitor as close to the device as possible. EP EP Exposed Pad. Externally connect EP to V SS or leave unconnected. 9

10 1-Bit, Nonvolatile, inear-taper Digital (MAX5483/MAX5484 Variable Resistors) TQFN PIN TSSOP NAME 4 7, 15 7, 8, 9, 13 No Connection. Not internally connected. Pin Description (continued) FUNCTION 1 12 D. Do Not Connect. eave unconnected for proper operation iper Terminal 3 1 ow Terminal 8, V SS supply operation, -2.5V V SS -.2V as long as (V DD - V SS ) 5.25V. Bypass V SS to GND Negative Power-Supply Input. For single-supply operation, connect V SS to GND. For dual- with a.1µf ceramic capacitor as close to the device as possible. 9 6 SPI/UD 1 5 Interface-Mode Select. Select serial SPI interface when SPI/UD = 1. Select serial up/down interface when SPI/UD =. Serial SPI Interface Data Input (SPI/UD = 1) Up/Down Control Input (SPI/UD = ). ith low, a high-to-low SCK(INC) transition decrements the wiper position. ith high, a high-to-low SCK(INC) transition increments the wiper position. Serial SPI Interface Clock Input (SPI/UD = 1) 11 4 SCK(INC) iper Increment Control Input (SPI/UD = ). ith low, the wiper position moves in the direction determined by the state of on a high-to-low transition Active-ow Digital Input Chip Select 13 2 GND Ground Positive Power-Supply Input (+2.7V V 14 1 V DD +5.25V). Bypass V DD to GND with a.1µf DD ceramic capacitor as close to the device as possible. EP EP Exposed Pad. Externally connect EP to V SS or leave unconnected. 1

11 1-Bit, Nonvolatile, inear-taper Digital V DD GND V SS SCK(INC) 1-BIT NV MEMORY SPI INTERFACE POR 1-BIT ATCH 1 DER Functional Diagrams H 1 MUX UP/DON INTERFACE SPI/UD MAX5481 MAX5482 NOTE: THE MAX5481/MAX5482 ARE NOT INTENDED FOR CURRENT TO FO THROUGH THE IPER (SEE THE MAX5481/MAX5482 PROGRAMMABE VOTAGE-DIVIDER SECTION). 11

12 1-Bit, Nonvolatile, inear-taper Digital V DD GND V SS SCK(INC) 1-BIT NV MEMORY SPI INTERFACE POR 1-BIT ATCH Functional Diagrams (continued) 1 1 DER H MUX UP/DON INTERFACE SPI/UD MAX5483 MAX5484 Detailed Description The MAX5481/MAX5482 linear programmable voltagedividers and the MAX5483/MAX5484 variable resistors feature 124 tap points (1-bit resolution) (see the Functional Diagrams). These devices consist of multiple strings of equal resistor segments with a wiper contact that moves among the 124 points through a pin-selectable 3-wire SPI-compatible serial interface or up/down interface. The MAX5481/MAX5483 provide a total end-to-end resistance of 1kΩ, and the MAX5482/MAX5484 have an end-to-end resistance of 5kΩ. The MAX5481/MAX5482 allow access to the high, low, and wiper terminals for a standard voltagedivider configuration. MAX5481/MAX5482 Programmable Voltage-Dividers The MAX5481/MAX5482 programmable voltagedividers provide a weighted average of the voltage between the H and inputs at the output. Both devices feature 1-bit resolution and provide up to 124 tap points between the H and voltages. Ideally, the V voltage occurs at the wiper terminal () when all data bits are zero and the V H voltage occurs at the wiper terminal when all data bits are one. The step size (1 SB) voltage is equal to the voltage applied across terminals H and divided by 2 1. Calculate the wiper voltage V as follows: ( ) VH VFSE + V ZSE V ( D) = D + V + V ZSE

13 1-Bit, Nonvolatile, inear-taper Digital R-H (kω) (DECIMA) 5kΩ DEVICE SCAES BY A FACTOR OF FIVE Figure 1. Resistance from to H vs. Code (1kΩ Voltage-Divider) where D is the decimal equivalent of the 1 data bits written ( to 123), V H is the voltage difference between the H and terminals: V FSE V H FSE =, and 124 V ZSE V H ZSE = 124 The MAX5481 includes a total end-to-end resistance value of 1kΩ while the MAX5482 features an end-toend resistance value of 5kΩ. These devices are not intended to be used as a variable resistor. iper current creates a nonlinear voltage drop in series with the wiper. To ensure temperature drift remains within specifications, do not pull current through the voltage-divider wiper. Connect the wiper to a high-impedance node. Figures 1 and 2 show the behavior of the MAX5481 s resistance from to H and from to. This does not apply to the variable-resistor devices MAX5483/MAX5484 Variable Resistors The MAX5483/MAX5484 provide a programmable resistance between and. The MAX5483 features a total end-to-end resistance value of 1kΩ, while the MAX5484 provides an end-to-end resistance value of 5kΩ. The programmable resolution of this resistance is equal to the nominal end-to-end resistance divided by 124 (1-bit resolution). For example, each nominal segment resistance is 9.8Ω and 48.8Ω for the MAX5483 and the MAX5484, respectively. R- (kω) Table 1. R at Selected Codes (DECIMA) (DECIMA) 5kΩ DEVICE SCAES BY A FACTOR OF FIVE Figure 2. Resistance from to vs. Code (1kΩ Voltage-Divider) MAX5483 (1kΩ DEVICE) R (Ω) The 1-bit data in the 1-bit latch register selects a wiper position from the 124 possible positions, resulting in 124 values for the resistance from to. Calculate the resistance from to (R ) by using the following formula: D R( D)= R + RZ 123 MAX5484 (5kΩ DEVICE) R (Ω) , ,7 5,11 where D is decimal equivalent of the 1 data bits written, R - is the nominal end-to-end resistance, and R Z is the zero-scale error. Table 1 shows the values of R at selected codes for the MAX5483/MAX5484. Digital Interface Configure the by a pin-selectable, 3-wire, SPI-compatible serial data interface or an up/down interface. Drive SPI/UD high to select the 3- wire SPI-compatible interface. Pull SPI/UD low to select the up/down interface. 13

14 1-Bit, Nonvolatile, inear-taper Digital Table 2. Command Decoding* COCK EDGE Bit Name C1 C D9 D8 D7 D6 D5 D4 D3 D2 D1 D rite iper Register D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X Copy iper Register to NV Register Copy NV Register to iper Register *D9 is the MSB and D is the SB. X = Don t care t t O t S t C t CH t CP t H t 1 SCK(INC) t DS t DH Figure 3. SPI-Compatible Serial-Interface Timing Diagram (SPI/UD = 1) SPI-Compatible Serial Interface Drive SPI/UD high to enable the 3-wire SPI-compatible serial interface (see Figure 3). This write-only interface contains three inputs: chip select (), data in (), and data clock (SCK(INC)). Drive low to load the data at synchronously into the shift register on each SCK(INC) rising edge. The RITE command (C1, C = ) requires 24 clock cycles to transfer the command and data (Figure 4a). The COPY commands (C1, C = 1 or 11) use either eight clock cycles to transfer the command bits (Figure 4b) or 24 clock cycles with the last 16 data bits disregarded by the device. After loading the data into the shift register, drive high to latch the data into the appropriate control register. Keep low during the entire serial data stream to avoid corruption of the data. Table 2 shows the command decoding. rite iper Register Data written to this register (C1, C = ) controls the wiper position. The 1 data bits (D9 D) indicate the position of the wiper. For example, if =, the wiper moves to the position closest to. If = , the wiper moves closest to H. This command writes data to the volatile random access memory (RAM), leaving the NV register unchanged. hen the device powers up, the data stored in the NV register transfers to the wiper register, moving the wiper to the stored position. Figure 5 shows how to write data to the wiper register. 14

15 1-Bit, Nonvolatile, inear-taper Digital a) 24-BIT COMMAND/DATA ORD SCK(INC) C1 C D9 D8 D7 D6 D5 D4 D3 D2 D1 D b) 8-BIT COMMAND ORD SCK(INC) C1 C Figure 4. Serial SPI-Compatible Interface Format SCK(INC) C1 C D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X X X X X ACTION IPER REGISTER UPDATED Figure 5. rite iper Register Operation 15

16 1-Bit, Nonvolatile, inear-taper Digital Table 3. Truth Table SCK(INC) Decrement H Increment X No Change H X X No Change X X No Change X Position Not Stored X H Position Stored = High-to-low transition. = ow-to-high transition. X = Don t care. Copy iper Register to NV Register The copy wiper register to NV register command (C1, C = 1) stores the current position of the wiper to the NV register for use at power-up. Figure 6 shows how to copy data from wiper register to NV register. The operation takes up to 12ms (max) after goes high to complete and no other operation should be performed until completion. SCK(INC) ACTION C1 C 1 t BUSY RITE NV REGISTER (DEVICE IS BUSY) Figure 6. Copy iper Register to NV Register Operation Copy NV Register to iper Register The copy NV register to wiper register (C1, C = 11) restores the wiper position to the current value stored in the NV register. Figure 7 shows how to copy data from the NV register to the wiper register. Digital Up/Down Interface Figure 8 illustrates an up/down serial-interface timing diagram. In digital up/down interface mode (SPI/UD = ), the logic inputs,, and SCK(INC) control the wiper position and store it in nonvolatile memory (see Table 3). The chip-select () input enables the serial interface when low and disables the interface when high. The position of the wiper is stored in the nonvolatile register when transitions from low to high while SCK(INC) is high. hen the serial interface is active ( low), a high-tolow (falling edge) transition on SCK(INC) increments or decrements the internal 1-bit counter depending on the state of. If is high, the wiper increments. If is low, the wiper decrements. The device stores the value of the wiper position in the nonvolatile memory when transitions from low to high while SCK(INC) is high. The host system can disable SCK(INC) ACTION C1 C 1 1 IPER REGISTER UPDATED Figure 7. Copy NV Register to iper Register Operation the serial interface and deselect the device without storing the latest wiper position in the nonvolatile memory by keeping SCK(INC) low while taking high. Upon power-up, the load the value of nonvolatile memory into the wiper register, and set the wiper position to the value last stored. 16

17 1-Bit, Nonvolatile, inear-taper Digital Standby Mode The feature a low-power standby mode. hen the device is not being programmed, it enters into standby mode and supply current drops to.5µa (typ). Nonvolatile Memory The internal EEPROM consists of a nonvolatile register that retains the last value stored prior to power-down. The nonvolatile register is programmed to midscale at the factory. The nonvolatile memory is guaranteed for 5 years of wiper data retention and up to 2, wiper write cycles. Power-Up Upon power-up, the load the data stored in the nonvolatile wiper register into the volatile wiper register, updating the wiper position with the data stored in the nonvolatile wiper register. Applications Information The are ideal for circuits requiring digitally controlled adjustable resistance, such as CD contrast control (where voltage biasing adjusts the display contrast), or programmable filters with adjustable gain and/or cutoff frequency. Positive CD Bias Control Figures 9 and 1 show an application where a voltagedivider or a variable resistor is used to make an adjustable, positive CD-bias voltage. The op amp provides buffering and gain to the voltage-divider network made by the programmable voltage-divider (Figure 9) or to a fixed resistor and a variable resistor (see Figure 1). Programmable Gain and Offset Adjustment Figure 11 shows an application where a voltage-divider and a variable resistor are used to make a programmable gain and offset adjustment. IPER POSITION STORED IPER POSITION NOT STORED t CYC t CI t IC t CPH t I t IH t IK SCK(INC) t ID t DI t SC t S V NOTES: V IS NOT A DIGITA SIGNA. IT REPRESENTS A IPER TRANSITION. SCK(INC) MUST BE AT OGIC HIGH HEN CHANGES STATE. Figure 8. Up/Down Serial-Interface Timing Diagram (SPI/UD = ) 17

18 1-Bit, Nonvolatile, inear-taper Digital MAX5481 MAX5482 H 5V 3V MAX48 V OUT Figure 9. Positive CD Bias Control Using a Voltage-Divider MAX5481 MAX5482 MAX5483 MAX5484 V IN V REF H Figure 11. Programmable Gain/Offset Adjustment V OUT 5V V IN C 3V V OUT MAX48 V OUT MAX5483 MAX5484 R3 R1 MAX5483 MAX5484 MAX5483 MAX5484 R2 Figure 1. Positive CD Bias Control Using a Variable Resistor Figure 12. Programmable Filter Programmable Filter Figure 12 shows the configuration for a 1st-order programmable filter using two variable resistors. Adjust R2 for the gain and adjust R3 for the cutoff frequency. Use the following equations to estimate the gain (G) and the 3dB cutoff frequency (f C ): R G = R2 1 fc = 2π R3 C 18

19 1-Bit, Nonvolatile, inear-taper Digital PART CONFIGURATION Selector Guide END-TO-END RESISTANCE (kω) MAX5481ETE Voltage-divider 1 MAX5481EUD Voltage-divider 1 MAX5482ETE Voltage-divider 5 MAX5482EUD Voltage-divider 5 MAX5483ETE Variable resistor 1 MAX5483EUD Variable resistor 1 MAX5484ETE Variable resistor 5 MAX5484EUD Variable resistor 5 Ordering Information (continued) PART PIN-PACKAGE PKG Chip Information TRANSISTOR COUNT: 2,29 PROCESS: BiCMOS TOP MARK MAX5482ETE 16 TQFN-EP* T1633F-3 ACQ MAX5482EUD 14 TSSOP U14-1 MAX5483ETE 16 TQFN-EP* T1633F-3 ACR MAX5483EUD 14 TSSOP U14-1 MAX5484ETE 16 TQFN-EP* T1633F-3 A MAX5484EUD 14 TSSOP U14-1 Note: All devices are specified over the -4 C to +85 C operating temperature range. *EP = Exposed pad. Pin Configurations (continued) TOP VIE V DD 1 14 V SS V DD 1 14 V SS GND 2 13 GND H 3 12 D. SCK(INC) 4 5 MAX5481* MAX5482* 11 1 SCK(INC) 4 5 MAX5483 MAX SPI/UD 6 9 SPI/UD TSSOP TSSOP *SEE FUNCTIONA DIAGRAM 19

20 1-Bit, Nonvolatile, inear-taper Digital Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to MARKING D D/2 E/2 E AAAA.1 C.8 C C A A2 A1 C C (ND - 1) X e e k (NE - 1) X e E2 E2/2 C D2/2 b D2.1 M C A B 12x16 QFN THIN.EPS e e PACKAGE OUTINE 8, 12, 16 THIN QFN, 3x3x.8mm I 2 PKG REF. A b D E e N ND NE A1 8 3x3 MIN. NOM. MAX BSC x3 MIN. NOM. MAX BSC x3 MIN. NOM. MAX BSC PKG. S MIN. EXPOSED PAD VARIATIONS D2 E2 PIN ID NOM. MAX. MIN. NOM. MAX. JEDEC TQ x 45 EEC T x 45 EED-1 T x 45 EED-1 T T x EED-2 T1633F-3.65 T x 45 EED x 45 EED-2 T1633FH x EED x 45 EED-2 A2.2 REF.2 REF.2 REF T x 45 EED-2 k NOTES: 1. DIMENSIONING & TOERANCING CONFORM TO ASME Y14.5M A DIMENSIONS ARE IN MIIMETERS. ANGES ARE IN DEGREES. 3. N IS THE TOTA NUMBER OF TERMINAS. 4. THE TERMINA #1 IDENTIFIER AND TERMINA NUMBERING CONVENTION SHA CONFORM TO JESD 95-1 SPP-12. DETAIS OF TERMINA #1 IDENTIFIER ARE OPTIONA, BUT MUST BE OCATED ITHIN THE ZONE INDICATED. THE TERMINA #1 IDENTIFIER MAY BE EITHER A MOD OR MARKED FEATURE. 5. DIMENSION b APPIES TO METAIZED TERMINA AND IS MEASURED BETEEN.2 mm AND.25 mm FROM TERMINA TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINAS ON EACH D AND E SIDE RESPECTIVEY. 7. DEPOPUATION IS POSSIBE IN A SYMMETRICA FASHION. 8. COPANARITY APPIES TO THE EXPOSED HEAT SINK SUG AS E AS THE TERMINAS. 9. DRAING CONFORMS TO JEDEC MO22 REVISION C. 1. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONY. 11. NUMBER OF EADS SHON ARE FOR REFERENCE ONY. 12. ARPAGE NOT TO EXCEED.1mm. PACKAGE OUTINE 8, 12, 16 THIN QFN, 3x3x.8mm I 2 2

21 1-Bit, Nonvolatile, inear-taper Digital Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to TSSOP4.4mm.EPS PACKAGE OUTINE, TSSOP 4.4mm BODY I 1 Revision History Pages changed at Rev 3: 1, 11, 19, 2, 21 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.