MAX547BCQH. Pin Configurations AGNDEF REFEF VOUTC AGNDEF REFEF 43 VOUTG 7 39 VOUTG V DD

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1 19-257; Rev 3; 12/95 Octal, 13-Bit Voltage-Output DAC with Parallel Interface General Description The contai eight 13-bit, voltage-output digital-toanalog converters (DACs). On-chip precision output amplifiers provide the voltage outputs. The operates from a ±5V supply. Bipolar output voltages with up to ±4.5V voltage swing can be achieved with no external components. The has four separate reference inputs; each is connected to two DACs, providing different fullscale output voltages for every DAC pair. The features double-buffered interface logic with a 13-bit parallel data bus. Each DAC has an input latch and a DAC latch. Data in the DAC latch sets the output voltage. The eight input latches are addressed with three address lines. Data is loaded to the input latch with a single write itruction. An asynchronous load ( L D _ ) input trafers data from the input latch to the DAC latch. The four L D _ inputs each control two DACs, and all DAC latches can be updated simultaneously by asserting all L D _ pi. An asynchronous clear ( C L R ) input resets the output of all eight DACs to AGND_. Asserting C L R resets both the DAC and the input latch to bipolar zero (1hex). On power-up, reset circuitry performs the same function as C L R. All logic inputs are TTL/CMOS compatible. The is available in 44-pin plastic quad flat pack and 44-pin PLCC packages. Applicatio Automatic Test Equipment Minimum Component-Count Analog Systems Digital Offset/Gain Adjustment Arbitrary Function Generators Industrial Process Controls Avionics Equipment Features Full 13-Bit Performance without Adjustments 8 DACs in One Package Buffered Voltage Outputs Calibrated Linearity Guaranteed Monotonic to 13 Bits ±5V Supply Operation Unipolar or Bipolar Outputs Swing to ±4.5V Fast Output Settling (5µs to ± 1 2 LSB) Double-Buffered Digital Inputs Asynchronous Load Inputs Load Pairs of DAC Latches Asynchronous C L R Input Resets DACs to Analog Ground Power-On Reset Circuit Resets DACs to Analog Ground Microprocessor and TTL/CMOS Compatible Ordering Information PART TEMP. RANGE PIN-PACKAGE ACQH C to +7 C 44 PLCC BCQH ACMH C to +7 C C to +7 C 44 PLCC 44 Plastic FP BCMH C to +7 C 44 Plastic FP BC/D C to +7 C Dice* Ordering Information continued at end of data sheet. *Contact factory for dice specificatio. INL (LSBs) Pin Configuratio ±2 ±4 ±2 ±4 ±4 TOP VIEW VOUTC VOUTD VSS REFCD AGNDCD CLR AGNDEF REFEF VSS VOUTE VOUTF VOUTC VOUTD VSS REFCD AGNDCD CLR AGNDEF REFEF VSS VOUTE VOUTF VOUTB VOUTA VDD REFAB AGNDAB LDAB LDCD CS WR A2 A VOUTG 32 VOUTH 31 VDD 3 REFGH 29 AGNDGH 28 GND 27 LDGH 26 LDEF 25 D 24 D1 23 D2 VOUTB VOUTA REFAB AGNDAB LDAB LDCD CS WR A2 A VOUTG VOUTH REFGH AGNDGH GND LDGH LDEF D D D2 A D12 D11 D1 D9 D8 D7 D6 D5 D4 D PLASTIC FP A D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 PLCC Maxim Integrated Products 1 For free samples & the latest literature: or phone

2 ABSOLUTE MAXIMUM RATINGS to GND...-.3V to +6V V SS to GND...-6V to +.3V Digital Input Voltage to GND...-.3V to ( +.3V) REF_...(AGND_ -.3V) to ( +.3V) AGND_...(V SS -.3V) to ( +.3V) VOUT_... to V SS Maximum Current into REF_ Pin...±1mA Maximum Current into Any Other Signal Pin...±5mA Continuous Power Dissipation (T A = +7 C) PLCC (derate 13.33mW/ C above +7 C)...167mW Plastic FP (derate 11.11mW/ C above +7 C )...889mW Operating Temperature Ranges C H... C to +7 C E H...-4 C to +85 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1sec)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( = +5V, V SS = -5V, REF_ = 4.96V, AGND_ = GND = V, R L = 1kΩ, C L = 5pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) Resolution PARAMETER Relative Accuracy Differential Nonlinearity Power-Supply Rejection Ratio Reference Input Range Reference Input Resistance SYMBOL STATIC PERFORMANCE ANALOG SECTION N INL DNL PSRR REF RREF A B CONDITIONS Guaranteed monotonic DYNAMIC PERFORMANCE ANALOG SECTION Voltage-Output Slew Rate Output Settling Time To ±1 2 LSB of full scale (Note 4) Digital Feedthrough Digital Crosstalk MIN TYP MAX Bipolar Zero-Code Error ±5 ±2 13 AGND 5 ±.5 ±2 ±.5 ±4 Gain Error ±1 ±8 Load Regulation REFERENCE (Note 2) ANALOG OUTPUT Maximum Output Voltage Minimum Output Voltage DIGITAL S ( = 5V ±5%) Input Voltage High Input Voltage Low Input Current Input Capacitance VIH VIL IIN CIN Gain/ (Note 1) Gain/ V SS (Note 1) R L = to 1kΩ (Notes 2, 3) Each REF pin (Note 3) V IN = V or (Note 5) V SS ±1 ±.25 ± UNITS Bits LSB LSB LSB LSB %/% LSB V kω V V V/µs µs nv-s nv-s V V µa pf 2

3 ELECTRICAL CHARACTERISTICS (continued) ( = +5V, V SS = -5V, REF_ = 4.96V, AGND_ = GND = V, R L = 1kΩ, C L = 5pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER POWER SUPPLIES Positive Supply Range Negative Supply Range Positive Supply Current Negative Supply Current SYMBOL V SS I DD I SS (Note 6) (Note 6) T A = T MIN to T MAX T A = T MIN to T MAX CONDITIONS MIN TYP MAX UNITS V V ma ma Note 1: PSRR is tested by changing the respective supply voltage by ±5%. Note 2: For best performance, REF_ should be greater than AGND_ + 2V and less than -.6V. The device operates with reference inputs outside this range, but performance may degrade. For further information on the reference, see the Reference and Analog-Ground Inputs section in the Detailed Description. Note 3: Reference input resistance is code dependent. See Reference and Analog-Ground Inputs section in the Detailed Description. Note 4: Typical settling time with 1pF capacitive load is 1µs. Note 5: Guaranteed by design. Not production tested. Note 6: Guaranteed by supply-rejection test. TIMING CHARACTERISTICS ( = +5V, V SS = -5V, REF_ = 4.96V, AGND_ = GND = V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER C S Pulse Width Low W R Pulse Width Low L D C L Pulse Width Low R Pulse Width Low C S Low to W R Low C S High to W R High Data Valid to W R Setup SYMBOL t 1 t 2 t 3 t 4 t 5 t 6 t 7 CONDITIONS MIN TYP MAX UNITS Data Valid to W R Hold t 8 Address Valid to W R Setup t 9 1 Address Valid to W R Hold t 1 3

4 Typical Operating Characteristics ( = 5V, V SS = -5V, REF_ = 4.96V, AGND_ = GND = V, T A = +25 C, unless otherwise noted.) RELATIVE ACCURACY (LSB) RELATIVE ACCURACY vs. DIGITAL CODE DIGITAL CODE (DECIMAL) Fg TOC-5 RELATIVE ACCURACY (LSB) RELATIVE ACCURACY vs. REFERENCE VOLTAGE REFERENCE VOLTAGE (V) -Fg TOC-11 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE I DD I SS TEMPERATURE ( C) -Fg TOC-2 THD + NOISE (%) TOTAL HARMONIC DISTORTION + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY REF = 2V p-p CODE = ALL 1s FREQUENCY (khz) -Fg TOC-4 THD + NOISE (%) TOTAL HARMONIC DISTORTION + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY REF = 4V p-p CODE = ALL 1s FREQUENCY (khz) -Fg TOC-3 SETTLING TIME (µs) SETTLING TIME vs. LOAD CAPACITANCE LOAD CAPACITANCE (nf) -Fg TOC-9 RELATIVE OUTPUT (db) REFERENCE SMALL-SIGNAL FREQUENCY RESPONSE SINE WAVE AT REF 2V ±1mV CODE ALL 1s -Fg TOC-1 RELATIVE OUTPUT (db) REFERENCE LARGE-SIGNAL FREQUENCY RESPONSE SINE WAVE AT REF_ 2V ±2V CODE ALL 1s -Fg TOC-6 RELATIVE OUTPUT (db) REFERENCE FEEDTHROUGH SINE WAVE AT REF_ 2V ±2V -Fg TOC , FREQUENCY (khz) , FREQUENCY (khz) FREQUENCY (khz) 4

5 Typical Operating Characteristics (continued) ( = 5V, V SS = -5V, REF_ = 4.96V, AGND_ = GND = V, T A = +25 C, unless otherwise noted.) -1-2 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY = V SS = 5V ±2mV NO LOAD -Fg TOC FULL-SCALE ERROR vs. LOAD RESISTANCE NEGATIVE FULL-SCALE -Fg TOC-8 PSRR (db) V SS ERROR (LSB) REF_ = 4.96V FREQUENCY (khz) POSITIVE FULL-SCALE LOAD RESISTANCE (kω) POSITIVE SETTLING TIME TO FULL-SCALE STEP (ALL BITS OFF TO ALL BITS ON) NEGATIVE SETTLING TIME TO FULL-SCALE STEP (ALL BITS ON TO ALL BITS OFF) DIGITAL S (5V/div) DIGITAL S (5V/div) OUTPUT (1mV/div) OUTPUT (1mV/div) 2µs/div REF = 4.96V, C L = 1pF, R L = 5kΩ DYNAMIC RESPONSE (ALL BITS OFF, ON, OFF) 2µs/div REF = 4.96V, C L = 1pF, R L = 5kΩ DIGITAL FEEDTHROUGH (GLITCH IMPULSE) DIGITAL S (5V/div) OUTPUT (2V/div) +5V V 1mV V -1mV 2µs/div REF = 4.96V, C L = 1pF, R L = 5kΩ 2/div TOP: DIGITAL TRANSITION ON ALL DATA BITS BOTTOM: DAC OUTPUT WITH WR HIGH 1mV/div 5

6 Typical Operating Characteristics (continued) ( = 5V, V SS = -5V, REF_ = 4.96V, AGND_ = GND = V, T A = +25 C, unless otherwise noted.) ADJACENT-CHANNEL CROSSTALK A 5V/div ADJACENT-CHANNEL CROSSTALK A: 5V/div B 5mV/div B: 5mV/div 5/div REF = 4.96V, C L = 5pF, R L = 1kΩ A: DIGITAL S, DAC A, DATA BITS from ALL Os to OAAAhex B: OUTPUT, DAC B 5/div REF = 4.96V, C L = 5pF, R L = 1kΩ A: DIGITAL S, DAC A, DATA BITS from OAAAhex to ALL Os B: OUTPUT, DAC B Pin Description PLCC PIN FLAT PACK NAME FUNCTION 1 39 C L R Clear Input (active low). Driving this asynchronous input low sets the content of all latches to 1hex. All DAC outputs are reset to AGND_. 2 4 AGNDCD Analog Ground for DAC C and DAC D 3 41 REFCD Reference Voltage Input for DAC C and DAC D. Bypass to AGNDCD with a.1µf to 1µF capacitor. Negative Power Supply, -5V (2 pi). Connect both pi to the supply voltage. Bypass each pin 4, 42 42, 36 V SS to the system analog ground with a.1µf to 1µF capacitor VOUTD DAC D Output Voltage 6 44 VOUTC DAC C Output Voltage 7 1 VOUTB DAC B Output Voltage 8 2 VOUTA DAC A Output Voltage Positive Power Supply, 5V (2 pi). Connect both pi to the supply voltage. Bypass each pin to 9, 37 3, 31 the system analog ground with a.1µf to 1µF capacitor. 1 4 REFAB Reference Voltage Input for DAC A and DAC B. Bypass to AGNDAB with a.1µf to 1µF capacitor AGNDAB Analog Ground for DAC A and DAC B 12 6 L D A B Load Input (active low). Driving this asynchronous input low trafers the contents of input latches A and B to the respective DAC latches L D C D C S W R Load Input (active low). Driving this asynchronous input low trafers the contents of input latches C and D to the respective DAC latches. Chip Select (active low) Write Input (active low). W R, along with C S, loads data into the DAC input latch selected by AA2. 6

7 Pin Description (continued) PIN FLAT NAME PLCC PACK 16 1 A2 Address Bit A1 Address Bit A Address Bit FUNCTION D12D Data Bits L D E F Load Input (active low). Driving this asynchronous input low trafers the contents of input latches E and F to the respective DAC latches L D G H Load Input (active low). Driving this asynchronous input low trafers the contents of input latches G and H to the respective DAC latches GND Digital Ground AGNDGH Analog Ground for DAC G and DAC H 36 3 REFGH Reference Voltage Input for DAC G and DAC H. Bypass to AGNDGH with a.1µf to 1µF capacitor VOUTH DAC H Output Voltage VOUTG DAC G Output Voltage 4 34 VOUTF DAC F Output Voltage VOUTE DAC E Output Voltage REFEF Reference Voltage Input for DAC E and DAC F. Bypass to AGNDEF with a.1µf to 1µF capaci AGNDEF Analog Ground for DAC E and DAC F Detailed Description Analog Section The contai eight 13-bit, voltage-output DACs. These DACs are inverted R-2R ladder networks that convert 13-bit digital inputs into equivalent analog output voltages, in proportion to the applied reference voltages. The has one reference input (REF_) and one analog-ground input (AGND_) for each pair of DACs. The four REF_ inputs allow different fullscale output voltages for each DAC pair, and the four AGND_ inputs allow different offset voltages for each DAC pair. 2R R R R R V DAC 2R 2R 2R 2R D D1 D11 D12 R OUT The DAC ladder outputs are buffered with op amps that operate with a gain of two. The inverting node of the amplifier is connected to the respective reference input, resulting in bipolar output voltages from -REF_ to 495/496 REF_. Figure 1 shows the simplified DAC circuit. REF AGND Figure 1. DAC Simplified Circuit Diagram 7

8 Reference and Analog-Ground Inputs The REF_ inputs can range between AGND_ and. However, the DAC outputs will operate to -.6V and V SS +.6V, due to the output amplifiers voltageswing limitatio. The AGND_ inputs can be offset by any voltage within the supply rails. The offset-voltage potential must be lower than the reference-voltage potential. For more information, refer to the Digital Code and Analog Output Voltage section in the Applicatio Information. The input impedance of the REF_ inputs is code dependent. It is at its lowest value (5kΩ min) when the input code of the referring DAC pair is (AAAhex). Its maximum value, typically 5kΩ, occurs when the code is hex. When all reference inputs are driven from the same source, the minimum load impedance is 1.25kΩ. Since the input impedance at REF_ is code dependent, load regulation of the reference used is important. For more information, see Reference Selection in the Applicatio Information section. The input capacitance at REF_ is also code dependent, and typically varies from 125pF to 3pF. Its minimum value occurs when the code of the referring DAC pair is set to all s. It is at its maximum value with all 1s on both DACs. Output Buffer Amplifiers The s voltage outputs are internally buffered by precision gain-of-two amplifiers with a typical slew rate of 3V/µs. With a full-scale traition at its output, the typical settling time to ± 1 2 LSB is 5µs when loaded with 1kΩ in parallel with 5pF, or 6µs when loaded with 1kΩ in parallel with 1pF. Digital Inputs and Interface Logic All digital inputs are compatible with both TTL and CMOS logic. The interfaces with microprocessors using a data bus at least 13 bits wide. The interface is double buffered, allowing simultaneous update of all DACs. There are two latches for each DAC (see Functional Diagram): an input latch that receives data from the data bus, and a DAC latch that receives data from the input latch. Address lines A, A1, and A2 select which DAC s input latch receives data from the data bus, as shown in Table 1. Trafer data from the input latches to the DAC latches by asserting the asynchronous LD_ signal. Each DAC s analog output reflects the data held in its DAC latch. All control inputs are level triggered. Data can be latched or traferred directly to the DAC. CS and WR control the input latch and LD_ trafers information from the input latch to the DAC latch. The input latch is traparent when CS and WR are low, and Table 1. DAC Addressing A2 A2 A1 A CS WR LDGH LDEF LDCD LDAB CLR A DAC A input latch 1 DAC B input latch 1 DAC C input latch 1 1 DAC D input latch 1 A1 Figure 2. Input Control Logic DAC E input latch 1 1 DAC F input latch 1 1 DAC G input latch DAC H input latch FUNCTION TO LATCH OF DAC H TO LATCH OF DAC G TO LATCH OF DAC F TO LATCH OF DAC E TO LATCH OF DAC D TO LATCH OF DAC C TO LATCH OF DAC B TO LATCH OF DAC A TO DAC LATCHES OF DAC G AND DAC H TO DAC LATCHES OF DAC E AND DAC G TO DAC LATCHES OF DAC C AND DAC D TO DAC LATCHES OF DAC C AND DAC B TO ALL AND DAC LATCHES the DAC latch is traparent when LD_ is low. The address lines (A, A1, A2) must be valid throughout the time CS and WR are low (Figure 3). Otherwise, the data can be inadvertently written to the wrong DAC. Data is latched within the input latch when either CS or WR is high. Taking LD_ high latches data into the DAC latches. If LD_ is brought low when WR and CS are low, it must be held low for t 3 or longer after WR and CS are high (Figure 3). Pulling the asynchronous CLR input low sets all DAC outputs to a nominal V, regardless of the state of CS, WR, and LD_. Taking CLR high latches 1hex into all input latches and DAC latches. 8

9 Table 2. Interface Truth Table C L R L D W R C S FUNCTION 1 Both latches traparent X Both latches latched 1 1 X 1 Both latches latched 1 X Input latch traparent 1 X 1 X Input latch latched 1 X X 1 Input latch latched 1 X X DAC latch traparent CS WR AA2 DD12 LD X X X t 1 t 5 t 6 t 2 t 9 t 1 All input and DAC latches at 1hex, outputs at AGND NOTES: 1. ALL RISE AND FALL TIMES MEASURED FROM 1% TO 9% OF +5V. t r = t f = MEASUREMENT REFERENCE LEVEL IS (V INH + V INL )/2. 3. IF LD IS ACTIVATED WHILE WR IS LOW THEN LD MUST STAY LOW FOR t 3 OR LONGER AFTER WR GOES HIGH. Figure 3. Write-Cycle Timing t 7 t 8 t 3 t 3 Applicatio Information Multiplying Operation The can be used for multiplying applicatio. Its reference accepts both DC and AC signals. The voltage at each REF_ input sets the full-scale output voltage for its respective DACs. Since the reference inputs accept only positive voltages, multiplying operation is limited to two quadrants. Do not bypass the reference inputs when applying AC signals to them. Refer to the graphs in the Typical Operating Characteristics for dynamic performance of the DACs and output buffers. Digital Code and Analog Output Voltage The uses offset binary coding. A 13-bit twoscomplement code can be converted to a 13-bit offset binary code by adding 2 12 = 496. Bipolar Output Voltage Range (AGND_ = V) For symmetrical bipolar operation, tie AGND_ to the system ground. Table 3 shows the relatiohip between digital code and output voltage. The following paragraphs give a detailed explanation of this mode. The DAC ladder output voltage (V DAC ) is multiplied by 2 and level shifted by the reference voltage, which is internally connected to the output amplifiers (Figure 1). Since the feedback resistors are the same size, the amplifier s output voltage is 2 times the voltage at its noninverting input, minus the reference voltage. VOUT = 2(V DAC ) REF where VDAC is the voltage at the amplifier s noninverting input (DAC ladder output voltage), and REF_ is the voltage applied to the reference input of the DAC. With AGND_ connected to the system ground, the DAC ladder output voltage is: D D VDAC = (REF ) = (REF ) n where D is the numeric value of the DAC s binary input code and n is the DAC s resolution (13 bits). Replace V DAC in the equation and calculate the output voltage. D VOUT_ = 2 REF REF 13 ( ) 2 D D = REF 1 REF 12 2 = D ranges from (2 ) to 8191 (2 13-1). 1 1LSB = REF 496 9

10 Table 3. Bipolar Code Table (AGND_ = V) REF R1 R2 1µF REFAB AGNDAB DIGITAL S NOT SHOWN. NOT ALL DACS SHOWN. Figure 4. Offsetting AGND 1µF OUTPUT +REF_ 495 ( ) 496 +REF_ 1 ( ) 496 V -REF_ 1 ( ) 496 -REF_ 495 ( ) 496 -REF_ Positive Unipolar Output Voltage Range (AGND_ = REF_/2) For positive unipolar output operation, set AGND_ to (REF_/2). For example, if you use Figure 4 s circuit with, a 4.96V reference and offset AGND_ by 2.48V with matched resistors (R1 = R2) and an op amp, it results in a V to 4.955V (nominal) unipolar output voltage, where 1LSB = 5µV. In general, the maximum current flowing out of any AGND_ pin is given by: I REF_ AGND_ AGND_ = 5kΩ DAC A DAC B +5V V SS V SS -5V 1µF 1µF 1µF VOUTA VOUTB Table 4. Positive Unipolar Code Table (AGND_ = REF _ ) OUTPUT +REF_ 8191 ( ) REF /2 Customizing the Output Voltage Range The AGND_ inputs can be offset by any voltage within the supply rails if the voltage at the referring REF_ input is higher than the voltage at the AGND_ input. Select the reference voltage and the voltage at AGND_ so the resulting output voltages do not come within ±.6V of the supply rails. Figure 4 s circuit shows one way to add positive offset to AGND_; make sure that the op amp used has sufficient current-sink capability to take up the remaining AGND_ current: I REF_ AGND_ AGND_ = 5kΩ Another way is to digitally offset AGND_ by connecting the output of one DAC to one or more AGND_ inputs. Do not connect a DAC output to its own AGND_ input. Table 5 summarizes the relatiohip between the reference and AGND_ potentials and the output voltage in the different modes of operation. Power-Supply Sequencing The sequence in which the supply voltages come up is not critical. However, we recommend that on power-up, V SS comes up first, next, followed by the reference voltages. If you use other sequences, limit the current into any reference pin to 1mA. Also, make sure that V SS is never more than 3mV above ground. If there is a risk that this can occur at power-up, connect a Schottky diode between V SS and GND, as shown in Figure 5. We recommend that you not power up the logic input pi before establishing the supply voltages. If this is not possible and the digital lines can drive more than 1mA, you should place current-limiting resistors (e.g., 47Ω) in series with the logic pi. Reference Selection If you want a ±2.5V full-scale output voltage swing, you can use the MAX873 reference. It operates from a single 5V supply and is specified to drive up to 1mA. Therefore, it can drive all four reference inputs simultaneously. Because the maximum load impedance can vary from 1.25kΩ to 12.5kΩ (four reference inputs in parallel), the reference load current ranges from 2mA to.2ma (1.8mA maximum load step). The MAX873 s V 1

11 Table 5. Reference, AGND and Output Relatiohips PARAMETER Bipolar Zero Level, or Unipolar Mid-scale, (Code = 1) BIPOLAR OPERATION (AGND_ = V) POSITIVE UNIPOLAR OPERATION (AGND_ = REF_/2) CUSTOM OPERATION REF_ AGND_ (=V) AGND (= AGND 2 ) Differential Reference Voltage (V DR ) REF REF /2 REF - AGND Negative Full-scale Output (Code = All s) Positive Full-Scale Output (Code = All 1s) LSB Weight VOUT as a Function of Digital Code (D, to 8191) -REF 495 ( )( 496 ) REF_ REF_ 496 ( D )( ) REF_ V 8191 ( )( 8192 ) REF_ REF_ ( ) 8192 D ( )( 8192 ) REF_ AGND - V DR 495 AGND _ + ( )( 496 DR) V VDR 496 D AGND _ + ( )( DR) - 1 V load regulation is specified to 2ppm/mA max over temperature, resulting in a maximum error of 36ppm (9µV). This corresponds to a maximum error caused by reference load regulation of only.147lsb [.147LSB = 9µV/(5V/8192)LSB] over temperature. If you want a ±4.96V full-scale output swing (1LSB = 1mV), you can use the calibrated, low-drift, low-dropout MAX676. Operating from a 5V supply, it is fully specified to drive two REF_ inputs with less than 6.4µV error (.64LSB) over temperature, caused by the maximum load step. Reference Buffering Another way to obtain high accuracy is to buffer a reference with an op amp. When driving all reference inputs simultaneously, keep the closed-loop output impedance of the op amp below.3ω to eure an error of less than.1lsb. The op amp must also drive the capacitive load (typically 5pF to 12pF). Each reference input can also be buffered separately by using the circuit in Figure 6. A reference load step caused by a digital traition only affects the DAC pair where the code traition occurs. It also allows the use of references with little drive capability. Keep the closed-loop output impedance of each op amp below.12ω, to eure an error of less than.1lsb. Figure 6 shows the op amp s inverting input directly connected to the s reference terminal. This eliminates the V SS SYSTEM GND 1N5817 Figure 5. Optional Schottky Diode between V SS and GND V SS influence of board lead resistance by seing the voltage with a low-current path see line directly at the reference input. Adding feedback resistors to individual reference buffer amplifiers enables different reference voltages to be generated from a single reference. GND 11

12 REFAB REFCD _Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE AEQH -4 C to +85 C 44 PLCC BEQH -4 C to +85 C 44 PLCC AEMH -4 C to +85 C BEMH -4 C to +85 C 44 Plastic FP 44 Plastic FP INL (LSBs) ±2 ±4 ±2 ±4 REFEF + - REFGH MAX494 Figure 6. Reference Buffering Power-Supply Bypassing and Ground Management For optimum performance, use a multilayer PC board with an unbroken analog ground. For normal operation, when all AGND_ pi are at the same potential, connect the four AGND_ pi directly to the ground plane or connect them together in a star configuration. The center of this star point is a good location to connect the digital system ground with the analog ground. If you are using a single common reference voltage, you can connect the reference inputs together using a star configuration. If you are using DC reference voltages, bypass each reference input with a.1µf to 1µF capacitor to AGND_. 12

13 Functional Diagram REFAB REFCD REFEF REFGH 9, LATCH A DAC LATCH A DAC A 8 11 VOUTA AGNDAB LATCH B DAC LATCH B DAC B 7 VOUTB LATCH C DAC LATCH C DAC C 6 2 VOUTC AGNDCD LATCH D DAC LATCH D DAC D 5 VOUTD D12D DATA BUS LATCH E DAC LATCH E DAC E VOUTE AGNDEF LATCH F DAC LATCH F DAC F 4 VOUTF LATCH G DAC LATCH G DAC G VOUTG AGNDGH LATCH H DAC LATCH H DAC H 38 VOUTH CS WR CONTROL LOGIC 16, 18 12, 13 32, , AA2 LDAB LDCD LDEF LDGH CLR V SS GND Pin numbers shown for PLCC package. 13

14 Chip Topography VOUTC VOUTD VSS REFCD AGNDCD CLR AGNDEF REFEF VOUTB VOUTG VOUTA VOUTH REFAB AGNDAB REFGH AGNDGH.242" (6.147mm) LDAB LDCD CS WR A2 A1 GND LDGH LDEF D D1 D2 A D12 D11 D1 VSS VOUTE VOUTF D9 D8 D7 D6 D5 D4 D3.199" (5.55mm) TRANSISTOR COUNT: 8987 SUBSTRATE CONNECTED TO VDD 14

15 Package Information D1 D C A2 e D2 B1 B DIM A A1 A2 A3 B B1 C D D1 D2 D3 e MIN INCHES MAX REF.5 REF MILLIMETERS MIN MAX REF 1.27 REF 21-35A D3 D1 D A A1 A3 44-PIN PLASTIC LEADED CHIP CARRIER PACKAGE 15

16 Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 16 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 (48) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.