Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Transcription

1 9-4368; Rev ; 4/9 Low-Power, Quad, 2-Bit General Description The /MAX55 integrate four low-power, 2-bit digital-to analog converters (DACs) and four precision output amplifiers in a small, 2-pin package. Each negative input of the four precision amplifiers is externally accessible providing flexibility in gain configurations, remote sensing, and high output drive capacity, making the /MAX55 ideal for industrial-process-control applications. Other features include software shutdown, hardware shutdown lockout, an active-low reset which clears all registers and DACs to zero, a user-programmable logic output, and a serial-data output. Each DAC provides a double-buffered input organized as an input register followed by a DAC register. A 6-bit serial word loads data into each input register. The serial interface is compatible with SPI /QSPI / MICROWIRE. The serial interface allows the input and DAC registers to be updated independently or simultaneously with a single software command. The 3-wire interface simultaneously updates the DAC registers. All logic inputs are TTL/CMOS-logic compatible. The operates from a single +5V power supply, and the MAX55 operates from a single +3V power supply. The /MAX55 are specified over the extended -4 C to +5 C temperature range. Applications Industrial Process Controls Automatic Test Equipment Microprocessor (μp)-controlled Systems Motion Control Digital Offset and Gain Adjustment Remote Industrial Controls Features Four 2-Bit DACs with Configurable Output Amplifiers +5V or +3V Single-Supply Operation Low Supply Current:.85mA Normal Operation µa Shutdown Mode () Force-Sense Outputs Power-On Reset Clears All Registers and DACs to Zero Capable of Recalling Last State Prior to Shutdown SPI/QSPI/MICROWIRE Compatible Simultaneous or Independent Control of DACs through 3-Wire Serial Interface User-Programmable Digital Output Guaranteed Over Extended Temperature Range (-4 C to +5 C) PART Ordering Information PIN- PACKAGE INL (LSB) Pin Configuration appears at end of data sheet. SUPPLY (V) AGAP+ 2 SSOP ± BGAP+ 2 SSOP ±2 +5 MAX55AGAP+ 2 SSOP ± MAX55BGAP+ 2 SSOP ± Denotes a lead(pb)-free/rohs-compliant package. Note: All devices are specified over the -4 C to +5 C operating temperature range. Functional Diagram /MAX55 CL PDL DGND AGND V DD REFAB DECODE CONTROL INPUT REGISTER A DAC REGISTER A DAC A MAX55 FBA FBB 6-BIT SHIFT REGISTER INPUT REGISTER B INPUT REGISTER C DAC REGISTER B DAC REGISTER C DAC B DAC C OUTB FBC OUTC FBD SR CONTROL LOGIC OUTPUT INPUT REGISTER D DAC REGISTER D DAC D OUTD UPO REFCD SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 Low-Power, Quad, 2-Bit /MAX55 ABSOLUTE MAXIMUM RATINGS V DD to AGND...-.3V to +6V V DD to DGND...-.3V to +6V AGND to DGND...-.3V to +.3V REFAB, REFCD to AGND...-.3V to (V DD +.3V) OUT_, FB_ to AGND...-.3V to (V DD +.3V) Digital Inputs to DGND...-.3V to +6V, UPO to DGND...-.3V to (V DD +.3V) ELECTRICAL CHARACTERISTI Continuous Current into Any Pin...±2mA Continuous Power Dissipation (T A = +7 C) 2-Pin SSOP (derate 8.mW/ C above +7 C)...64mW Operating Temperature Range...-4 C to +5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( (V DD = +5V ±%, V REFAB = V REFCD = 2.5V), MAX55 (V DD = +3V to +3.6V, V REFAB = V REFCD =.25V), V AGND = V DGND =, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values at T A = +25 C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Analog Section) Resolution N 2 Bits Integral Nonlinearity (Note ) INL A/MAX55A ±.25 ±.75 B/MAX55B ±2. Differential Nonlinearity DNL Guaranteed monotonic ±. LSB Offset Error V OS ±3.5 mv Offset-Error Tempco 6 ppm/ o C Gain Error (Note ) GE -.3 ±2. MAX ±4. Gain-Error Tempco ppm/ o C Power-Supply Rejection Ratio PSRR MATCHING PERFORMANCE (T A = +25 o C) Gain Error GE 6 MAX ±2. MAX ±4. Offset Error V OS ±. ±3.5 mv Integral Nonlinearity INL (Note ) ±.35 ±. LSB REFERENCE INPUT Reference Input Range V REF V DD -.4 V Reference Input Resistance R REF Code-dependent, minimum at code 555H LSB LSB µv/v LSB 8 kω Refer ence C ur r ent i n S hutd ow n. ±. µa DIGITAL INPUTS A/B 2.4 Input High Voltage V IH MAX55A/MAX55B 2. V Input Low Voltage V IL.8 V Input Leakage Current I IN V IN = or V DD ±. ±. µa Input Capacitance C IN 8 pf 2

3 Low-Power, Quad, 2-Bit ELECTRICAL CHARACTERISTI (continued) ( (V DD = +5V ±%, V REFAB = V REFCD = 2.5V), MAX55 (V DD = +3V to +3.6V, V REFAB = V REFCD =.25V), V AGND = V DGND =, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values at T A = +25 C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS Output High Voltage V OH I SOURCE = 2mA V DD -.5 V Output Low Voltage V OL I SINK = 2mA.3.4 V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR.6 V/µs Output Settling Time To ±.5 LSB, V STEP = 2.5V A/B To ±.5 LSB, V STEP =.25V MAX55A/MAX55B Output Voltage Swing Rail-to-rail (Note 2) to V DD V Current into FB_. µa OUT_ Leakage Current in Shutdown R L = ±. ±. µa Startup Time Exiting A/B 5 Shutdown Mode MAX55A/MAX55B 2 Digital Feedthrough =V DD, f IN = khz 5 nv s Digital Crosstalk 5 nv s POWER SUPPLIES A/B Supply Voltage V DD MAX55A/MAX55B µs µs V /MAX55 Supply Current I DD (Note 3).85. ma Supply Current in Shutdown (Note 3) 2 µa TIMING CHARACTERISTI (Figure 6) Clock Period t CP ns Pulse-Width High t CH 4 ns Pulse-Width Low t CL 4 ns Fall to Rise Setup Time t S 4 ns Rise to Rise Hold Time t H ns Setup Time t DS 4 ns Hold Time t DH ns 3

4 Low-Power, Quad, 2-Bit /MAX55 ELECTRICAL CHARACTERISTI (continued) ( (V DD = +5V ±%, V REFAB = V REFCD = 2.5V), MAX55 (V DD = +3V to +3.6V, V REFAB = V REFCD =.25V), V AGND = V DGND =, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values at T A = +25 C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rise to Valid Propagation Delay Fall to Valid Propagation Delay t D t D2 C LOAD = 2pF C LOAD = 2pF 8 MAX MAX55 2 Rise to Fall Delay t 4 ns Rise to Rise Hold Time t 4 ns Pulse-Width High t W ns Note : Guaranteed from code to code 495 in unity-gain configuration. Note 2: Accuracy is better than. LSB for V OUT = 6mV to (V DD - 6mV), guaranteed by PSR test on endpoints. Note 3: R L =, digital inputs at DGND or V DD. ns ns (T A = +25 C, unless otherwise noted.) Typical Operating Characteristics V DD = 5V R L = 5kΩ INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE toc -.2 MAX55 V DD = 3V R L = 5kΩ INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE toc V DD = 5V SUPPLY CURRENT vs. TEMPERATURE toc3 INL (LSB) -.4 INL (LSB) -.4 IDD (µa) REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) CODE = FFF hex TEMPERATURE ( C) 4

5 Low-Power, Quad, 2-Bit (T A = +25 C, unless otherwise noted.) IDD (µa) IDD (µa) SUPPLY CURRENT vs. TEMPERATURE 83 MAX55 82 V DD = 3V CODE = FFF hex TEMPERATURE ( C) V DD = 5V SUPPLY CURRENT vs. SUPPLY VOLTAGE 78 CODE = FFF hex V DD (V) toc4 toc7 INL (LSB) IDD (µa) Typical Operating Characteristics (continued) FULL-SCALE ERROR vs. LOAD V DD = 5V -5.. LOAD (kω) MAX55 V DD = 3V SUPPLY CURRENT vs. SUPPLY VOLTAGE 784 CODE = FFF hex V DD (V) toc5 toc8 INL (LSB) FULL-SCALE ERROR vs. LOAD MAX55 V DD = 3V -5.. LOAD (kω) ANALOG CROSSTALK 5V toc9 µs/div V REF = 2.5V, R L = 5kΩ, C L = pf DACA CODE SWITCHING FROM C hex TO FCC hex DACB CODE SET TO 8 hex toc6 V/div /MAX55 OUTB AC-COUPLED mv/div ANALOG CROSSTALK 3V toc DYNAMIC RESPONSE 5V toc.5v/div V/div OUTB AC-COUPLED 5mV/div µs/div V REF =.5V, R L = 5kΩ, C L = pf DACA CODE SWITCHING FROM C hex TO FFF hex DACB CODE SET TO 8 hex µs/div V REF = 2.5V, R L = 5kΩ, C L = pf SWITCHING FROM CODE hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +2 5

6 Low-Power, Quad, 2-Bit /MAX55 (T A = +25 C, unless otherwise noted.) DYNAMIC RESPONSE 3V toc2 µs/div V REF =.5V, R L = 5kΩ, C L = pf SWITCHING FROM CODE hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +.5V/div Typical Operating Characteristics (continued) DIGITAL FEEDTHROUGH 3V ( = khz) toc3 4µs/div V REF =.5V, R L = 5kΩ, C L = pf V = V PDL = V CL = 3.3V, V = V DACA CODE SET TO 8 hex V/div AC-COUPLED mv/div DIGITAL FEEDTHROUGH 5V ( = khz) toc4 2µs/div V REF = 2.5V, R L = 5kΩ, C L = pf V = V PDL = V CL = 5V, V = V DACA CODE SET TO 8 hex 2V/div AC-COUPLED mv/div Pin Description PIN NAME FUNCTION AGND Analog Ground 2 FBA DAC A Output Amplifier Feedback 3 DAC A Output Voltage 4 OUTB DAC B Output Voltage 5 FBB DAC B Output Amplifier Feedback 6 REFAB DAC A/DAC B Reference Voltage Input 7 CL Active-Low Clear Input. CL clears all DACs and registers. CL resets all outputs (OUT_, UPO, and ) to. 8 Active-Low Chip-Select Input 9 Serial Data Input Serial Clock Input DGND Digital Ground 2 Serial Data Output 3 UPO User-Programmable Logic Output 4 PDL Active-Low Power-Down Lockout. Drive PDL low to lock out software shutdown. 5 REFCD DAC C/DAC D Reference Voltage Input 6 FBC DAC C Output Amplifier Feedback 7 OUTC DAC C Output Voltage 8 OUTD DAC D Output Voltage 9 FBD DAC D Output Amplifier Feedback 2 V DD Positive Power Supply 6

7 Low-Power, Quad, 2-Bit Detailed Description The /MAX55 integrate four 2-bit, voltageoutput digital-to-analog converters (DACs) that are addressed through a simple 3-wire serial interface. The devices include a 6-bit data-in/data-out shift register. Each internal DAC provides a doubled-buffered input composed of an input register and a DAC register (see the Functional Diagram). The negative input of each amplifier is externally accessible. The DACs are inverted rail-to-rail ladder networks that convert 2-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage inputs. DACs A and B share the REFAB input, while DACs C and D share the REFCD input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure shows a simplified circuit diagram of one of the four DACs. Reference Inputs The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for the two corresponding DACs. The reference input voltage range is V to (V DD -.4V). The output voltages (V OUT_ ) are represented by a digitally programmable voltage source as: V OUT_ = (V REF x NB/496) x Gain where NB is the numeric value of the binary input code ( to 495) of the DAC. V REF is the reference voltage. Gain is the externally set voltage gain. The impedance at each reference input is code-dependent, ranging from a low value of kω when both DACs connected to the reference accept an input code REF_ AGND SHOWN FOR ALL s ON DAC R R R 2R 2R 2R 2R 2R D D9 D D FB_ OUT_ of 555 hex, to a high value exceeding giga-ohms with an input code of hex. The load regulation of the reference source affects the performance of the devices as the input impedance at the reference inputs is code dependent. The REFAB and REFCD reference inputs provide a kω guaranteed minimum input impedance. When the same voltage source drives the two reference inputs, the effective minimum impedance is 5kΩ. A voltage reference with an excellent load regulation of.2mv/ma, such as the MAX633, is capable of driving both reference inputs simultaneously at 2.5V. Driving REFAB and REFCD separately improves reference accuracy. The REFAB and REFCD inputs enter a high-impedance state, with a typical input leakage current of.2µa, when the /MAX55 are in shutdown. The reference input capacitance is also code dependent and typically ranges from 2pF with an input code of all s to pf with an input code of all s. Output Amplifiers All DAC outputs are internally buffered by precision amplifiers with a typical slew rate of.6v/µs. Access to the inverting input of each output amplifier provides the greater flexibility in output gain setting/signal conditioning (see the Applications Information section). With a full-scale transition at the output, the typical settling time to within ±.5 LSB is 2µs when the output is loaded with 5kΩ in parallel with pf. A load of less than 2kΩ at the output degrades performance. See the Typical Operating Characteristics for the output dynamic responses and settling performances of the amplifiers. Power-Down Mode The /MAX55 feature a software-programmable shutdown that reduces supply current to a typical value of µa. Drive PDL high to enable the shutdown mode. Write XXXXXXXXXXXX as the input-control word to put the device in power-down mode (Table ). In power-down mode, the output amplifiers and the reference inputs enter a high-impedance state. The serial interface remains active. Data in the input registers is retained in power-down, allowing the devices to recall the output states prior to entering shutdown. Start up from power-down either by recalling the previous configuration or by updating the DACs with new data. Allow 5µs for the outputs to stabilize when powering up the devices or bringing the devices out of shutdown. /MAX55 Figure. Simplified DAC Circuit Diagram 7

8 Low-Power, Quad, 2-Bit /MAX55 Serial-Interface Configurations The /MAX55s 3-wire serial interface is compatible with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3). The serial input word consists of two address bits and two control bits followed by 2 data bits (MSB first), as shown in Figure 4. The 4-bit address/control code determines the / MAX55s response outlined in Table. The connection between and the serial-interface port is not necessary, but may be used for data echo. Data held in the shift register can be shifted out of and returned to the µp for data verification. The digital inputs of the /MAX55 are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers can be updated simultaneously from the input registers (Table ). Serial-Interface Description The /MAX55 require 6 bits of serial data. Table lists the serial-interface programming commands. For certain commands, the 2 data bits are don t-care bits. Data is sent MSB first and can be sent in two 8-bit packets or one 6-bit word ( must remain low until 6 bits are transferred). The serial data is composed of two DAC address bits (A, A) and two control bits (C, C), followed by the 2 data bits D D (Figure 4). The 4-bit address/control code determines: The register(s) to be updated The clock edge on which data is to be clocked out through the serial-data output () The state of the user-programmable logic output (UPO) If the device is to enter shutdown mode (assuming PDL is high) How the device is configured when exiting out of shutdown mode MAX55 * MISO* MOSI SCK +5V SS SPI/QSPI PORT I/O SK CPOL =, CPHA = SO *THE -MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE /MAX55, BUT CAN BE USED FOR READBACK PURPOSES. MAX55 * SI* MICROWIRE PORT Figure 3. Connections for SPI/QSPI *THE -SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE /MAX55, BUT CAN BE USED FOR READBACK PURPOSES. Figure 2. Connections for MICROWIRE I/O MSB...LSB ADDRESS BITS CONTROL BITS A A C C 4 ADDRESS/ CONTROL BITS Figure 4. Serial-Data Format 6 BITS OF SERIAL DATA DATA BITS MSB...LSB D...D 2 DATA BITS 8

9 Low-Power, Quad, 2-Bit Table. Serial-Interface Programming Commands 6-BIT SERIAL WORD A A C C D...D MSB LSB 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data FUNCTION Load input register A; DAC registers unchanged. Load input register B; DAC registers unchanged. Load input register C; DAC registers unchanged. Load input register D; DAC registers unchanged. Load input register A; all DAC registers updated. Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. XXXXXXXXXXXX Update all DAC registers from their respective input registers (startup). 2-bit DAC data Load all DAC registers from shift register (startup). XXXXXXXXXXXX Shutdown (provided PDL = ) XXXXXXXXXXXX UPO goes low (default) XXXXXXXXXXXX UPO goes high XXXXXXXXXXXX No operation (NOP) to DAC registers XXXXXXXXXXXX Mode, clocked out on s rising edge. All DAC registers updated. XXXXXXXXXXXX Mode, clocked out on s falling edge. All DAC registers updated (default). /MAX55 Figure 5 shows the serial-interface timing requirements. The input must be low to enable the DAC s serial interface. When is high, the interface control circuitry is disabled. must go low for at least t S before the rising serial clock () edge to properly clock in the first bit. When is low, data is clocked into the internal shift register through the serial data input () on the rising edge of. The maximum guaranteed clock frequency is MHz. Data is latched into the appropriate input/dac registers on the rising edge of. The programming command load-all-dacs-from-shiftregister allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The no operation (NOP) command leaves the register contents unaffected. This feature is used in a daisy-chain configuration (see the Daisy Chaining Devices section). The command to change the clock edge on which serial data is shifted out of also loads data from all input registers to their respective DAC registers. Serial-Data Output () The serial-data output,, is the internal shift register s output. The /MAX55 can be programmed so that data is clocked out of on the rising edge of (mode ) or the falling edge (mode ). In mode, output data at lags input data at by 6.5 clock cycles, maintaining compatibility with MICROWIRE, SPI/QSPI, and other serial interfaces. In mode, output data lags input data by 6 clock cycles. On power-up, defaults to mode timing. User-Programmable Logic Output (UPO) The user-programmable logic output, UPO, allows an external device to be controlled through the /MAX55 serial interface (Table ). 9

10 Low-Power, Quad, 2-Bit /MAX55 (MODE ) (MODE ) A A MSB FROM PREVIOUS WRITE MSB FROM PREVIOUS WRITE Figure 5. Serial-Interface Timing Diagram C C D D D9 D8 D7 D6 D5 D4 D3 D2 D DATA PACKET (N) A A C C D D D9 D8 D7 D6 D5 D4 D3 D2 D D A DATA PACKET (N-) A A C C D D D9 D8 D7 D6 D5 D4 D3 D2 D D A DATA PACKET (N-) D COMMAND EXECUTED DATA PACKET (N) DATA PACKET (N) t W t O t S t CL t CH t CP t H t t DS tdh t DO t DO2 Figure 6. Detailed Serial-Interface Timing Diagram Power-Down Lockout (PDL) Drive power-down lockout, PDL, low to disable software shutdown. When in shutdown, transitioning PDL from high to low wakes up the device with the output set to the state prior to shutdown. Use PDL to asynchronously wake up the device. Daisy Chaining Devices The /MAX55 can be daisy chained by connecting of one device to of another device (Figure 7). Each output of the /MAX55 includes an internal active pullup. The sink/source capability of determines the time required to discharge/charge a capacitive load. See the serial-data-out V OH and V OL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several /MAX55 devices. In this configuration, the data bus is common to all devices. Data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input () is required for each IC.

11 Low-Power, Quad, 2-Bit MAX55 Figure 7. Daisy Chaining /MAX55 MAX55 MAX55 TO OTHER SERIAL DEVICES /MAX TO OTHER SERIAL DEVICES MAX55 MAX55 MAX55 Figure 8. Multiple /MAX55 Devices Sharing a Common Line

12 Low-Power, Quad, 2-Bit /MAX55 Table 2. Unipolar Code Table DAC CONTENTS MSB LSB Applications Information Unipolar Output For a unipolar output, the output voltages and the reference inputs are of the same polarity. Figure 9 shows the /MAX55 unipolar output circuit, which is also the typical operating circuit. Table 2 lists the unipolar output codes. See Figure for rail-to-rail outputs. Figure shows the /MAX55 with the output amplifiers configured with a closed-loop gain of +2 to provide to 5V full-scale range with a 2.5V external reference voltage. ANALOG OUTPUT 495 +V REF ( ) V REF ( ) VREF +V REF ( ) = V REF ( ) 496 Bipolar Output Figure shows the /MAX55 configured for bipolar operation. V OUT = V REF [(2NB/496) - ] where NB is the numeric value of the DAC s binary input code. Table 3 shows digital codes (offset binary) and corresponding output voltages for the circuit of Figure. MAX55 REFAB REFERENCE INPUTS +5V DAC A DAC B DAC C DAC D REFCD AGND V DD DGND FBA FBB FBC FBD OUTB OUTC OUTD +V REF ( ) 496 V Table 3. Bipolar Code Table Figure 9. Unipolar Output Circuit MAX55 REFERENCE INPUTS +5V REFAB REFCD V DD FBA kω DAC CONTENTS MSB LSB ANALOG OUTPUT 247 +V REF ( ) 248 +V REF ( ) 248 V -V REF ( ) 248 -V 247 REF ( ) V REF ( ) = -V REF 248 Note: LSB = (V REF ) ( 496 ) kω DAC A FBB kω kω DAC B OUTB FBC kω kω DAC C OUTC FBD kω kω DAC D OUTD AGND DGND V REFAB = V REFCD = 2.5V Figure. Unipolar Rail-to-Rail Output Circuit 2

13 Low-Power, Quad, 2-Bit Digitally Programmable Current Source The circuit of Figure 2 places an npn transistor (2N394 or similar) within the op-amp feedback loop to implement a digitally programmable, unidirectional current source. This circuit drives 4mA to 2mA current loops, which are commonly used in industrial-control applications. The output current is calculated with the following equation: I OUT = (V REF /R) x (NB/496) where NB is the numeric value of the DAC s binary input code and R is the sense resistor shown in Figure 2. Power-Supply Considerations On power-up, all input and DAC registers are cleared (set to zero code) and D OUT is in mode (serial data is shifted out of on the clock s falling edge). For rated /MAX55 performance, limit V REFAB / V REFCD to.4v below V DD. Bypass V DD with a 4.7µF capacitor in parallel with a.µf capacitor to AGND. Use short lead lengths and place the bypass capacitors as close as possible to the supply inputs. Grounding and Layout Considerations Digital or AC transient signals between AGND and DGND create noise at the analog outputs. Connect AGND and DGND together at the DAC, and then connect this point to the highest-quality ground available. Good PCB ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Do not use wire-wrapped boards. PROCESS: BiCMOS Chip Information /MAX55 R R2 REF_ REF_ FB_ +5V DAC_ MAX55 V L I OUT DAC OUT_ -5V V OUT OUT_ FB_ 2N394 MAX55 R = R2 = kω ±.% R Figure. Bipolar Output Circuit Figure 2. Digitally Progammable Current Source 3

14 Low-Power, Quad, 2-Bit /MAX55 TOP VIEW AGND FBA OUTB FBB REFAB CL Pin Configuration MAX55 2 V DD 9 FBD 8 OUTD 7 OUTC 6 FBC 5 REFCD 4 PDL 3 UPO 2 DGND Package Information For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 2 SSOP A SSOP 4

15 Low-Power, Quad, 2-Bit REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED /8 Initial release 4/9 Removed future product asterisk from MAX55 in Ordering Information table and updated Electrical Characteristics table 4 /MAX55 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.