Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Transcription

1 9-23; Rev 3; 3/ Calibrated, Quad, 2-Bit General Description The combine four 2-bit, voltage-output digital-to-analog converters (DACs) and four precision output amplifiers in a space-saving 6-pin package. Offset, gain, and linearity are factory calibrated to provide the s ± LSB total unadjusted error. The operates with ±5V supplies, while the uses -5V and +.8V to +3.2V supplies. Each DAC has a double-buffered input, organized as an input register followed by a DAC register. A 6-bit serial word is used to load data into each input/dac register. The serial interface is compatible with either SPI/QSPI or MICROWIRE, and allows the input and DAC registers to be updated independently or simultaneously with a single software command. The DAC registers can be simultaneously updated with a hardware LDAC pin. All logic inputs are TTL/CMOS compatible. Applications Industrial Process Controls Automatic Test Equipment Digital Offset and Gain Adjustment Motion Control Devices Remote Industrial Controls Microprocessor-Controlled Systems Functional Diagram DGND V DD SDO LDAC AGND VSS TP REFAB Features Four 2-Bit DACs with Output Buffers Simultaneous or Independent Control of Four DACs via a 3-Wire Serial Interface Power-On Reset SPI/QSPI and MICROWIRE Compatible ± LSB Total Unadjusted Error () Full 2-Bit Performance without Adjustments ±5V Supply Operation () Double-Buffered Digital Inputs Buffered Voltage Output 6-Pin DIP/SO Packages Ordering Information PART TEMP RANGE PIN- PACKAGE INL (LSB) ACPE+ C to +7 C 6 PDIP ±.5 BCPE+ C to +7 C 6 PDIP ± ACWE+ C to +7 C 6 Wide SO ±.5 BCWE+ C to +7 C 6 Wide SO ± AEPE+ -4 C to +85 C 6 PDIP ±.5 BEPE+ -4 C to +85 C 6 PDIP ± AEWE+ -4 C to +85 C 6 Wide SO ±.5 BEWE+ -4 C to +85 C 6 Wide SO ± +Denotes a lead(pb)-free/rohs-compliant package. Ordering Information continued at end of data sheet. Pin Configuration 6-BIT SHIFT REGISTER SR CONTROL DECODE CONTROL INPUT REG A INPUT REG B INPUT REG C INPUT REG D DAC REG A DAC REG B DAC REG C DAC REG D DAC A DAC B DAC C DAC D OUTA OUTB OUTC OUTD TOP VIEW OUTB OUTA V SS AGND REFAB DGND LDAC SDI OUTC OUTD V DD TP REFCD SDO SDI REFCD DIP/SO SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 Calibrated, Quad, 2-Bit ABSOLUTE MAXIMUM RATINGS V DD to AGND or DGND...-.3V to +3.2V...-.3V to +7V V SS to AGND or DGND...-7V to +.3V SDI,,, LDAC, TP, SDO to AGND or DGND...-.3V to (VDD +.3V) REFAB, REFCD to AGND or DGND...-.3V to (VDD +.3V) OUT_ to AGND or DGND...VDD to VSS Maximum Current into Any Pin...5mA Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate.53mw/ C above +7 C)...842mW Wide SO (derate 9.52mW/ C above +7 C)...762mW Operating Temperature Ranges MAX53_AC_E/BC_E... C to +7 C MAX53_AE_E/BE_E...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C Soldering Temperature (reflow) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI (V DD = +2V, V SS = -5V, REFAB/REFCD = 8V, AGND = DGND = V, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE ANALOG SECTION Resolution N 2 Bits T A = +25 C A ±. B ±2. AC ±2. Total Unadjusted Error (Note ) TUE LSB BC ±3. T A = T MIN to T MAX AE ±2.5 BE ±3.5 Integral Nonlinearity INL A ±.5 ±.5 B ± LSB Differential Nonlinearity DNL Guaranteed monotonic ± LSB T A = +25 C A ±2.5 B ±5. AC ±5. Offset Error mv BC ±7.5 T A = T MIN to T MAX AE ±6. BE ±8.5 R L = -. ±. Gain Error _C/E -.6 ±.5 LSB R L = 5kΩ _M ±2. V DD Power-Supply Rejection Ratio PSRR T A = +25 C,.8V < V DD < 3.2V ±.2 ±.25 LSB/V V SS Power-Supply Rejection Ratio PSRR T A = +25 C, -5.5V < V DD < -4.5V ±.3 ±.3 LSB/V 2

3 Calibrated, Quad, 2-Bit ELECTRICAL CHARACTERISTI (continued) (V DD = +2V, V SS = -5V, REFAB/REFCD = 8V, AGND = DGND = V, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MATCHING PERFORMANCE (T A = +25 C) Total Unadjusted Error TUE A ±. B ±2. Gain Error ±. ±. LSB Offset Error A ±.2 ±2.5 B ±.2 ±5. Integral Nonlinearity INL ±.2 ±. LSB REFERENCE INPUT Reference Input Range REF V D D - 4 V Reference Input Resistance R REF Code dependent, minimum at code kω MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth V REF = 2V P-P 7 khz Reference Feedthrough Input code = V REF = V P-P at 4Hz - all s V REF = V P-P at 4kHz -82 LSB mv db Total Harmonic Distortion Plus Noise DIGITAL INPUTS (SDI,,, LDAC) THD+N V REF = 2.V P-P at 5kHz.24 % Input High Voltage V IH 2.4 V Input Low Voltage V IL.8 V Input Leakage Current V IN = V or V DD. µa Input Capacitance (Note 2) pf DIGITAL OUTPUT (SDO) Output Low Voltage V OL SDO sinking 5mA.3.4 V Output Leakage Current SDO = V to V DD ± µa DYNAMIC PERFORMANCE (R L = 5kΩ, C L = pf) Voltage Output Slew Rate 5 V/µs Output Settling Time To ±.5 LSB of full scale 3 µs Digital Feedthrough 5 nv-s Digital Crosstalk (Note 3) V REF = 5V 8 nv-s POWER SUPPLIES Positive Supply Range V DD V Negative Supply Range V SS V Positive Supply Current (Note 4) Negative Supply Current (Note 4) T A = +25 C 8 8 I DD T A = T MIN to T MAX 25 T A = +25 C -6-6 I SS T A = T MIN to T MAX -23 ma ma 3

4 Calibrated, Quad, 2-Bit ELECTRICAL CHARACTERISTI (continued) (V DD = +2V, V SS = -5V, REFAB/REFCD = 8V, AGND = DGND = V, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTI (Note 5) Internal Power-On Reset Pulse Width (Note 2) t POR 2 µs Clock Period t CP ns Pulse Width High t CH 3 ns Pulse Width Low t CL 3 ns Fall to Rise Setup Time t S 2 ns Rise to Rise Hold Time t H ns SDI Setup Time t DS 4 26 ns SDI Hold Time t DH ns Rise to SDO Valid Propagation Delay (Note 6) Fall to SDO Valid Propagation Delay (Note 7) Fall to SDO Enable (Note 8) t DO t DO2 kω pullup on SDO to V DD, CLOAD = 5pF kω pullup on SDO to V DD, CLOAD = 5pF SDO high 78 5 SDO low 5 8 SDO high 8 SDO low t DV ns ns ns Rise to SDO Disable (Note 9) t TR 4 6 ns Rise to Fall Delay t Continuous, edge ignored 2 ns Rise to Rise Hold Time t edge ignored 2 ns LDAC Pulse Width Low t LDAC 3 ns Pulse Width High t W 4 ns Note : TUE is specified with no resistive load. Note 2: Guaranteed by design. Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I DD decreases slightly. Note 5: All input signals are specified with t R = tf 5ns. Logic input swing is to 5V. Note 6: Serial data clocked out of SDO on s falling edge. (SDO is an open-drain output for the. The s SDO pin has an internal active pullup.) Note 7: Serial data clocked out of SDO on s rising edge. Note 8: SDO changes from High-Z state to 9% of final value. Note 9: SDO rises % toward High-Z state. 4

5 Calibrated, Quad, 2-Bit ELECTRICAL CHARACTERISTI (V DD = +5V, V SS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = V, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE ANALOG SECTION Resolution N 2 Bits Integral Nonlinearity INL A ±.5 ±.5 B ± Differential Nonlinearity DNL Guaranteed monotonic ± LSB Offset Error Gain Error T A = +25 C T A = T MIN to T MAX A ±3. B ±6. AC ±6. BC ±9. AE ±7. BE ±. R L = -.3 ±.5 RL = 5kΩ -.8 ±3. V D D P ow er - S up p l y Rej ecti on Rati o PSRR T A = +25 C, 4.5V V DD 5.5V ±. ±.5 LSB/V V S S P ow er - S up p l y Rej ecti on Rati o PSRR T A = +25 C, -5.5V V SS -4.5V ±.2 ±.7 LSB/V MATCHING PERFORMANCE (T A = +25 C) Gain Error ±. ±.25 LSB Offset Error A ±.3 ±3. B ±.3 ±6. Integral Nonlinearity INL ±.35 ±. LSB REFERENCE INPUT Reference Input Range REF V D D V Reference Input Resistance RREF Code dependent, minimum at code 555 hex 5 kω MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth V REF = 2V P-P 7 khz Reference Feedthrough Total Harmonic Distortion Plus Noise DIGITAL INPUTS (SDI,,, LDAC) Input code = all s V REF = V P-P at 4Hz V REF = V P-P at 4kHz THD+N V REF = 85mV P-P at khz.24 % Input High Voltage V IH 2.4 V Input Low Voltage V IL.8 V Input Leakage Current V IN = V or V DD. µa Input Capacitance (Note 2) pf LSB mv LSB mv db 5

6 Calibrated, Quad, 2-Bit ELECTRICAL CHARACTERISTI (continued) (V DD = +5V, V SS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = V, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (SDO) Output High Voltage V OH SDO sourcing 2mA Output Low Voltage V OL SDO sinking 2mA.3.4 V DYNAMIC PERFORMANCE (RL = 5kΩ, CL = pf) Voltage Output Slew Rate 5 V/µs Output Settling Time To ±.5 LSB of full scale 5 µs Digital Feedthrough 5 nv-s Digital Crosstalk (Note 3) 5 nv-s POWER SUPPLIES Positive Supply Range V DD V Negative Supply Range V SS V T A = +25 C Positive Supply Current (Note 4) I DD T A = T MIN to T MAX 6 V DD -.5 V DD -.25 V ma T A = +25 C Negative Supply Current (Note 4) I SS T A = T MIN to T MAX -4 ma TIMING CHARACTERISTI (Note 5) Internal Power-On Reset Pulse Width (Note 2) t POR 5 µs Clock Period t CP ns Pulse Width High t CH _C/E 35 ns Pulse Width Low t CL _C/E 35 ns Fall to Rise Setup Time t S _C/E 4 ns Rise to Rise Hold Time t H ns SDI Setup Time t DS _C/E 4 24 ns SDI Hold Time t DH ns Rise to SDO Valid Propagation Delay (Note 6) t DO C LOAD = 5pF, _C/E 6 2 ns Fall To SDO Valid Propagation Delay (Note 7) t DO2 C LOAD = 5pF, _C/E 23 2 ns 6

7 Calibrated, Quad, 2-Bit ELECTRICAL CHARACTERISTI (continued) (V DD = +5V, V SS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = V, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fall to SDO Enable t DV C LOAD = 5pF, _C/E 75 4 ns Rise to DSO Disable (Note ) t TR C LOAD = 5pF, _C/E 7 3 ns Rise to Fall Delay t O Continuous, edge ignored 35 ns Rise to Rise Hold Time t edge ignored, _C/E 35 ns LDAC Pulse Width High t LDAC _C/E 5 ns Pulse Width High t W _C/E ns Note 2: Guaranteed by design. Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I DD decreases slightly. Note 5: All input signals are specified with t R = tf 5ns. Logic input swing is to 5V. Note 6: Serial data clocked out of SDO on s falling edge. (SDO is an open-drain output for the. The s SDO pin has an internal active pullup.) Note 7: Serial data clocked out of SDO on s rising edge. Note : When disabled, SDO is internally pulled high. 7

8 Calibrated, Quad, 2-Bit Typical Operating Characteristics (T A = +25 C, unless otherwise noted.) INL ERROR (LSB) THD + NOISE (%) INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE V SS = -5V V DD = +2V V DD = +5V REFERENCE VOLTAGE (V) TOTAL HARMONIC DISTORTION PLUS NOISE vs. REFERENCE FREQUENCY.2 DAC CODE = ALL s.75 REFAB = 5V P-P R L = kω, C L = pf R L = NO LOAD, C L = pf 2 FREQUENCY (khz) /7- RELATIVE OUTPUT (db) FULL-SCALE ERROR (LSB) REFERENCE FEEDTHROUGH AT 4Hz /7-3b REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE REFAB SWEPT 2V P-P V OUTA MONITORED -5 k k k M FREQUENCY (Hz) FULL-SCALE ERROR vs. LOAD /7-2 M -5. LOAD (kω) /7-4 THD + NOISE (%) SUPPLY CURRENT (ma) TOTAL HARMONIC DISTORTION PLUS NOISE vs. REFERENCE FREQUENCY DAC CODE = ALL s REFAB = V P-P R L = kω, C L = pf R L = NO LOAD, C L = pf 2 FREQUENCY (khz) SUPPLY CURRENT vs. TEMPERATURE V DD = +5V V SS = -5V REFERENCE FEEDTHROUGH AT 4kHz I DD I SS TEMPERATURE ( C) /7-3 /7-5 REFAB, 5V/div V REFAB, 5V/div V µv/div 2µV/div INPUT CODE = ALL s 5µs/div INPUT CODE = ALL s 5µs/div 8

9 Calibrated, Quad, 2-Bit Typical Operating Characteristics (continued) (T A = +25 C, unless otherwise noted.) DYNAMIC RESPONSE (ALL BITS ON, OFF, ON), 5V/div 2V/div NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF), 5V/div 5V/div 5mV/div 5µs/div V DD = +5V, V SS = -5V, REFAB = 5V, C L = pf, R L = kω µs/div V DD = +5V, V SS = -5V, REFAB = V, C L = pf, R L = kω POSITIVE FULL-SCALE SETTLING TIME (ALL BITS OFF TO ALL BITS ON) DIGITAL FEEDTHROUGH, 5V/div 5V/div, 5V/div -V OFFSET 5mV/div AC-COUPLED, mv/div µs/div V DD = +5V, V SS = -5V, REFAB = V, C L = pf, R L = kω V DD = +5V, V SS = -5V, REFAB = V, = HIGH, DIN TOGGLING AT 2 THE CLOCK RATE, OUTA = 5V 9

10 Calibrated, Quad, 2-Bit Typical Operating Characteristics (continued) (T A = +25 C, unless otherwise noted.) INL ERROR (LSB) INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE V DD = +5V V SS = -5V V REF (V) /7-6 RELATIVE OUTPUT (db) REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE REFAB SWEPT 2V P-P V OUTA MONITORED -5 k k k M FREQUENCY (Hz) /7-7 M THD + NOISE (%) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY.2 REFAB = 2.5V P-P R L = kω, C L = pf R L = NO LOAD, C L = pf 2 FREQUENCY (khz) /7-4 THD + NOISE (%) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY.2.75 REFAB = V P-P R L = kω, C L = pf.25 R L = NO LOAD, C L = pf 2 FREQUENCY (khz) REFERENCE FEEDTHROUGH AT 4Hz /7-9 FULL-SCALE ERROR (LSB) FULL-SCALE ERROR vs. LOAD -4. LOAD (kω) /7- SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE V DD = +5V V SS = -5V TEMPERATURE ( C) REFERENCE FEEDTHROUGH AT 4kHz I DD I SS /7- REFAB, V/div V REFAB, V/div V AC-COUPLED, µv/div AC-COUPLED, µv/div INPUT CODE = ALL s 5µs/div INPUT CODE = ALL s 5µs/div

11 Calibrated, Quad, 2-Bit Typical Operating Characteristics (continued) (T A = +25 C, unless otherwise noted.) DYNAMIC RESPONSE (ALL BITS ON, OFF, ON), 5V/div V/div NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF), 5V/div 5mV/div 5µs/div V DD = +5V, V SS = -5V, REFAB = 2.5V, C L = pf, R L = kω µs/div V DD = +5V, V SS = -5V, REFAB = 2.5V, C L = pf, R L = kω POSITIVE FULL-SCALE SETTLING TIME (ALL BITS OFF TO ALL BITS ON) DIGITAL FEEDTHROUGH, 5V/div, 5V/div 5mV/div AC-COUPLED, 2mV/div µs/div V DD = +5V, V SS = -5V, REFAB = 2.5V, C L = pf, R L = kω ns/div V DD = +5V, V SS = -5V, REFAB = 2.5V, = HIGH, DIN TOGGLING AT 2 THE CLOCK RATE, OUTA =.25V

12 Calibrated, Quad, 2-Bit Pin Description PIN NAME FUNCTION OUTB DAC B Output Voltage 2 OUTA DAC A Output Voltage 3 V SS Negative Power Supply 4 AGND Analog Ground 5 REFAB Reference Voltage Input for DAC A and DAC B 6 DGND Digital Ground 7 LDAC 8 SDI Serial Data Input. Data is shifted into an internal 6-bit shift register on 's rising edge. 9 SDO Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input registers to their respective DAC registers. Chip-Select Input (active low). A low level on enables the input shift register and SDO. On s rising edge, data is latched into the appropriate register(s). Shift Register Clock Input Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when is low. For the, SDO is an open-drain output. For the, SDO has an active pullup to V DD. 2 REFCD Reference Voltage Input for DAC C and DAC D 3 TP Test Pin. Connect to V DD for proper operation. 4 V DD Positive Power Supply 5 OUTD DAC D Output Voltage 6 OUTC DAC C Output Voltage Detailed Description The contain four 2-bit voltage-output DACs that are easily addressed using a simple 3-wire serial interface. They include a 6-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see the Functional Diagram on the front page). The DACs are inverted R-2R ladder networks that convert 2-bit digital inputs into equivalent analog output voltages in proportion to the applied reference-voltage inputs. DAC A and DAC B share the REFAB reference input, while DAC C and DAC D share the REFCD reference input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure shows a simplified circuit diagram of one of the four DACs. Reference Inputs The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for its two corresponding DACs. The REFAB/REFCD voltage range is V to (V DD - 4V) for the and V to (VDD - 2.2V) for the. The output voltages VOUT_ are represented by REF AGND SHOWN FOR ALL s ON DAC R R R 2R 2R 2R 2R 2R D D9 D D Figure. Simplified DAC Circuit Diagram V OUT a digitally programmable voltage source as: V OUT_ = N B (V REF) /496 where N B is the numeric value of the DAC s binary input code ( to 495) and VREF is the reference voltage. 2

13 Calibrated, Quad, 2-Bit The input impedance at each reference input is code dependent, ranging from a low value of typically 6kΩ (with an input code of ) to a high value of 6kΩ (with an input code of ). Since the input impedance at the reference pins is code dependent, load regulation of the reference source is important. The REFAB and REFCD reference inputs have a 5kΩ guaranteed minimum input impedance. When the two reference inputs are driven from the same source, the effective minimum impedance becomes 2.5kΩ. The reference input capacitance is also code dependent and typically ranges from 25pF to 3pF. Output Buffer Amplifiers All voltage outputs are internally buffered by precision unity-gain followers with a typical slew rate of 5V/µs for the and 3V/µs for the. With a full-scale transition at the output ( to 8V or 8V to ), the typical settling time to ±.5 LSB is 3µs when loaded with 5kΩ in parallel with pf (loads less than 5kΩ degrade performance). With a full-scale transition at the output ( to 2.5V or 2.5V to ), the typical settling time to ±.5 LSB is 5µs when loaded with 5kΩ in parallel with pf (loads less than 5kΩ degrade performance). Output dynamic responses and settling performances of the output amplifier are shown in the Typical Operating Characteristics. Serial-Interface Configurations The s 3-wire or 4-wire serial interface is compatible with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3). In Figures 2 and 3, LDAC can be tied either high or low for a 3-wire interface, or used as the fourth input with a 4-wire interface. The connection between SDO and the serial-interface port is not necessary, but may be used for data echo. (Data held in the shift register of the can be shifted out of SDO and returned to the microprocessor for data verification; data in the input/dac registers cannot be read.) With a 3-wire interface (,, SDI) and LDAC tied high, the DACs are double-buffered. In this mode, depending on the command issued through the serial interface, the input register(s) may be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers may be simultaneously updated from the input registers. With a 3- wire interface (,, SDI) and LDAC tied low (Figure 5V 5V RP kω RP kω SK SDO* MISO* SS SDI SO SDI MOSI SDO* SI* MICROWIRE PORT SPI/QSPI PORT I/O I/O LDAC** I/O LDAC** I/O *THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE, BUT MAY BE USED FOR READBACK PURPOSES. **THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE. THE HAS AN INTERNAL ACTIVE PULLUP TO VDD, SO R P IS NOT NECESSARY. Figure 2. Connections for MICROWIRE Figure 3. Connections for SPI/QSPI CPOL =, CPHA = *THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE, BUT MAY BE USED FOR READBACK PURPOSES. **THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE. THE HAS AN INTERNAL ACTIVE PULLUP TO VDD, SO R P IS NOT NECESSARY. 3

14 Calibrated, Quad, 2-Bit SDI SDO Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or V DD ) D5 D4 D3... MSB Q5... MSB FROM PREVIOUS WRITE D2 D D LSB... Q COMMAND EXECUTED LSB FROM PREVIOUS WRITE INPUT REGISTER(S) UPDATED SDI D5 D4 D3... MSB... D2 D D LSB SDO Q5... MSB FROM PREVIOUS WRITE... Q LSB FROM PREVIOUS WRITE LDAC DACs UPDATED Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC t W t O t S t CL t CH t CP t H t I t DS tdh SDI SDO t DV t DO t DO2 t TR LDAC* *USE OF LDAC IS OPTIONAL t LDAC Figure 6. Detailed Serial-Interface Timing Diagram 4

15 Calibrated, Quad, 2-Bit 4), the DAC registers remain transparent. Any time an input register is updated, the change appears at the DAC output with the rising edge of. The 4-wire interface (,, SDI, LDAC) is similar to the 3-wire interface with LDAC tied high, except LDAC is a hardware input that simultaneously and asynchronously loads all DAC registers from their respective input registers when driven low (Figure 5). Serial-Interface Description The require 6 bits of serial data. Data is sent MSB first and can be sent in two 8-bit packets or one 6-bit word ( must remain low until 6 bits are transferred). The serial data is composed of two DAC address bits (A, A), two control bits (C, C), and the 2 data bits D D (Figure 7). The 4-bit address/control code determines the following: ) the register(s) to be updated and/or the status of the input and DAC registers (i.e., whether they are in transparent or latch mode), and 2) the edge on which data is clocked out of SDO. Figure 6 shows the serial-interface timing requirements. The chip-select pin () must be low to enable the DAC s serial interface. When is high, the interface control circuitry is disabled and the serial data output pin (SDO) is driven high () or is a high-impedance open drain (). must go low at least t S before the rising serial clock () edge to properly clock in the first bit. When is low, data is clocked into the internal shift register via the serial data input pin (SDI) on s rising edge. The maximum guaranteed clock frequency is MHz. Data is latched into the appropriate input/dac registers on s rising edge. MSB...LSB Address Bits Control Bits 6 Bits of Serial Data Data Bits MSB...LSB A A C C D...D 4 Address/ Control Bits 2 Data Bits Figure 7. Serial-Data Format (MSB Sent First) Interface timing is optimized when serial data is clocked out of the microcontroller/microprocessor on one clock edge and clocked into the on the other edge. Table lists the serial-interface programming commands. For certain commands, the 2 data bits are don t cares. The programming command Load-All-DACs-From-Shift- Register allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The NOP (no operation) command allows the register contents to be unaffected and is useful when the are configured in a daisy-chain (see the Daisy-Chaining Devices section). The command to change the clock edge on which serial data is shifted out of the SDO pin also loads data from all input registers to their respective DAC registers. Serial-Data Output The serial-data output, SDO, is the internal shift register s output. The can be programmed so that data is clocked out of SDO on s rising (Mode ) or falling (Mode ) edge. In Mode, output data at SDO lags input data at SDI by 6.5 clock cycles, maintaining compatibility with MICROWIRE, SPI/QSPI, and other serial interfaces. In Mode, output data lags input data by 6 clock cycles. On power-up, SDO defaults to Mode timing. For the, SDO is an open-drain output that should be pulled up to +5V. The data sheet timing specifications for SDO use a kω pullup resistor. For the, SDO is a complementary output and does not require an external pullup. Test Pin The test pin (TP) is used for pre-production analysis of the IC. Connect TP to V DD for proper operation. Failure to do so affects DAC operation. Daisy-Chaining Devices Any number of s can be daisy-chained by connecting the SDO pin of one device (with a pullup resistor, if appropriate) to the SDI pin of the following device in the chain (Figure 8). Since the s SDO pin has an internal active pullup, the SDO sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the serial data out VOH and V OL specifications in the Electrical Characteristics. 5

16 Calibrated, Quad, 2-Bit Table. Serial-Interface Programming Commands A X X A X 6-BIT SERIAL WORD C C D D 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data 2-bit DAC data XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX LDAC X X X Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. Load all DACs from shift register. No operation (NOP) FUNCTION Load DAC A input register; DAC output unchanged. Load DAC B input register; DAC output unchanged. Load DAC C input register; DAC output unchanged. Load DAC D input register; DAC output unchanged. Load input register A; all DAC registers updated. Update all DACs from their respective input registers. Mode (default condition at power-up), DOUT clocked out on s rising edge. All DACs updated from their respective input registers. XXXXXXXXXXXX X Mode, DOUT clocked out on s falling edge. All DACs updated from their respective input registers. X 2-bit DAC data Load DAC A input register; DAC A is immediately updated. X 2-bit DAC data Load DAC B input register; DAC B is immediately updated. X 2-bit DAC data Load DAC C input register; DAC C is immediately updated. X 2-bit DAC data Load DAC D input register; DAC D is immediately updated. X = Don t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high, the DAC registers are latched. When daisy-chaining s, the delay from low to high (t S ) must be the greater of: t DV + t DS or t TR + t RC + t DS - t W where t RC is the time constant of the external pullup resistor (R p ) and the load capacitance (C) at SDO. For t RC < 2ns, t S is simply t DV + t DS. Calculate t RC from the following equation: V PULLUP trc = Rp (C) ln VPULLUP - 2.4V [ ( ) ] where V PULLUP is the voltage to which the pullup resistor is connected. Additionally, when daisy-chaining devices, the maximum clock frequency is limited to: f(max) = 2 (t DO + t RC - 38ns + t DS ) For example, with trc = 23ns (5V ±% supply with Rp = kω and C = 3pF), the maximum clock frequency is 8.7MHz. Figure 9 shows an alternate method of connecting several s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. More I/O lines are required in this configuration because a dedicated chip-select input () is required for each IC. 6

17 Calibrated, Quad, 2-Bit DIN SDI SDO +5V +5V +5V R P * kω SDI SDO R P * kω SDI SDO R P * kω TO OTHER SERIAL DEVICES * THE HAS AN ACTIVE INTERNAL PULLUP, SO R P IS NOT NECESSARY. Figure 8. Daisy-Chaining s with a 3-Wire Serial Interface DIN LDAC 2 3 TO OTHER SERIAL DEVICES LDAC SDI LDAC SDI LDAC SDI Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low., 2, 3 are driven separately, thus controlling which data are written to devices, 2, 3 7

18 Calibrated, Quad, 2-Bit Applications Information Interfacing to the M68HC* PORT D of the 68HC supports SPI. The four registers used for SPI operation are the Serial Peripheral Control Register, the Serial Peripheral Status Register, the Serial Peripheral Data I/O Register, and PORT D s Data Direction Register. These registers have a default starting location of $. On reset, the PORT D register (memory location $8) is cleared and bits 5- are configured as general-purpose inputs. Setting bit 6 (SPE) of the Serial Peripheral Control Register (SPCR) configures PORT D for SPI as follows: BIT NAME SS MOSI MISO TXD RXD Bits 6 and 7 are not used. Writes to these bits are ignored. The PORT D Data Direction Register (DDRD) determines whether the port bits are inputs or outputs. Its configuration is shown below: BIT NAME DDD5 DDD4 DDD3 DDD2 DDD DDD Setting DDD_ = configures the port bit as an input, while setting DDD_ = configures the port bit as an output. Writes to bits 6 and 7 have no effect. In SPI mode with MSTR =, when a PORT D bit is expected to be an input (SS, MISO, RXD), the corresponding DDRD bit (DDD_) is ignored. If the bit is expected to be an output (, MOSI, TXD), the corresponding DDRD bit must be set for the bit to be an output. Table 2. Serial Peripheral Control-Register Definitions NAME SPIE SPE DWOM MSTR CPOL CPHA SPR/ DEFINITION Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral Status Register s SPIF bit or MODF bit is set. Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a generalpurpose I/O port. When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary. Master/Slave select option Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the clock idles low. Determines the clock phase. SPI Clock-Rate Select SPR SPR µp clock divided by 2 µp clock divided by 4 µp clock divided by 6 µp clock divided by 32 Table 3. Serial Peripheral Status-Register Definitions NAME SPIF WCOL MODF DEFINITION SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR. The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by reading the SPSR and then accessing the SPDR. The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the master controller has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR. *M68HC is a Motorola microcontroller. General information about the device was obtained from M68HC technical manuals. 8

19 Calibrated, Quad, 2-Bit Table 4. M68HC Programming Code 9

20 Calibrated, Quad, 2-Bit SS is an input intended for use in a multimaster environment. However, SS or unused PORT D bit RXD, TXD, or possibly MISO (if DAC readback is not used) should be configured as a general-purpose output and used as by setting the appropriate Data Direction Register bit. The SPCR configuration (memory location $28) is shown below: BIT NAME SPIE SPE DWOM MSTR CPOL CPHA SPR SPR SETTING AFTER RESET U* U* SETTING FOR TYPICAL SPI COMMUNICATION ** ** *U = Unknown **Depends on µp clock frequency. Always configure the 68HC as the master controller and the as the slave device. When MSTR = in the SPCR, a write to the Serial Peripheral Data I/O Register (SPDR), located at memory location $2A, initiates the transmission/reception of data. The data transfer is monitored and the appropriate flags are set in the Serial Peripheral Status Register (SPSR). The SPSR configuration is shown below: BIT NAME SPIF WCOL MODF RESET CONDITIONS An example of 68HC programming code for a two-byte SPI transfer to the is given in Table 4. SS is used for, the high byte of / digital data is stored in memory location $, and the low byte is stored in memory location $. Interfacing to Other Controllers When using MICROWIRE, refer to the section on Interfacing to the M68HC for guidance, since MICROWIRE can be considered similar to SPI when CPOL = and CPHA =. When interfacing to Intel s 8C5/8C3 microcontroller family, use bit-pushing to configure a desired port as the interface port. Bitpushing involves arbitrarily assigning I/O port bits as interface control lines, and then writing to the port each time a signal transition is required. Unipolar Output For a unipolar output, the output voltages and the reference inputs are the same polarity. Figure shows the unipolar output circuit, which is also the typical operating circuit. Table 5 lists the unipolar output codes. Bipolar Output The outputs can be configured for bipolar operation using Figure s circuit. One op amp and two resistors are required per DAC. With R = R2: V OUT = VREF [(2NB/496) - ] where NB is the numeric value of the DAC s binary input code. Table 6 shows digital codes and corresponding output voltages for Figure s circuit. Table 5. Unipolar Code Table DAC CONTENTS MSB LSB ANALOG OUTPUT 495 +V REF ( ) V REF ( ) VREF +V REF ( ) = V REF ( ) 496 +V REF ( ) 496 V Table 6. Bipolar Code Table DAC CONTENTS MSB LSB ANALOG OUTPUT +V 247 REF ( ) 248 +V REF ( ) 248 V -V REF ( ) V REF ( ) V REF ( ) = -V REF 248 NOTE: LSB = (V REF ) ( 496 ) 2

21 Calibrated, Quad, 2-Bit REFERENCE INPUTS 5 2 REFAB REFCD DAC A DAC B DAC C +2V (+5V) 4 3 V DD TP 2 6 OUTA OUTB OUTC V REF DAC OUTPUT R R2 +2V (+5V) V OUT 5V DAC D 5 OUTD R = R2 = kω.% V SS AGND DGND V NOTE: ( ) ARE FOR. NOTES: ( ) ARE FOR. V REF IS THE SELECTED REFERENCE INPUT FOR THE. Figure. Unipolar Output Circuit Figure. Bipolar Output Circuit +2V (+5V) +2V (+5V) AC 5kΩ REFERENCE INPUT +4V (+75mV) -4V (-75mV) kω REFAB TP V DD + V IN REFAB TP V DD DAC A 2 OUTA DAC B OUTB 4 AGND V SS AGND DGND V BIAS - V SS 3 DGND 6-5V -5V NOTES: ( ) ARE FOR. DIGITAL INPUTS NOT SHOWN. Figure 2. AC Reference Input Circuit NOTES: ( ) ARE FOR. DIGITAL INPUTS NOT SHOWN. Figure 3. AGND Bias Circuit 2

22 Calibrated, Quad, 2-Bit N V SS AGND Figure 4. When V SS and V DD cannot be sequenced, tie a Schottky diode between V SS and AGND. Using an AC Reference In applications where the reference has AC signal components, the have multiplying capability within the reference input range specifications. Figure 2 shows a technique for applying a sine-wave signal to the reference input where the AC signal is offset before being applied to REFAB/REFCD. The reference voltage must never be more negative than DGND. The s total harmonic distortion plus noise (THD+N) is typically less than.2%, given a 5V P-P signal swing and input frequencies up to 35kHz, or given a 2V P-P swing and input frequencies up to 5kHz. The typical -3dB frequency is 7kHz as shown in the Typical Operating Characteristics graphs. For the, with an input signal amplitude of.85mv P-P, THD+N is typically less than.24% with a 5kΩ load in parallel with pf and input frequencies up to khz, or with a 2kΩ load in parallel with pf and input frequencies up to 95kHz. Offsetting AGND AGND can be biased from DGND to the reference voltage to provide an arbitrary nonzero output voltage for a zero input code (Figure 3). The output voltage VOUTA is: V OUTA = V BIAS + N B (V IN ) where V BIAS is the positive offset voltage (with respect to DGND) applied to AGND, and N B is the numeric value of the DAC s binary input code. Since AGND is common to all four DACs, all outputs will be offset by V BIAS in the same manner. As the voltage at AGND increases, the DAC s resolution decreases because its full-scale voltage swing is effectively reduced. AGND should not be biased more negative than DGND. Power-Supply Considerations On power-up, V SS should come up first, V DD next, then REFAB or REFCD. If supply sequencing is not possible, tie an external Schottky diode between V SS and AGND as shown in Figure 4. On power-up, all input and DAC registers are cleared (set to zero code) and SDO is in Mode (serial data is shifted out of SDO on the clock s rising edge). For rated performance, VDD should be 4V higher than REFAB/REFCD and should be between.8v and 3.2V. When using the, VDD should be at least 2.2V higher than REFAB/REFCD and should be between 4.75V and 5.5V. Bypass both VDD and VSS with a 4.7µF capacitor in parallel with a.µf capacitor to AGND. Use short lead lengths and place the bypass capacitors as close to the supply pins as possible. Grounding and Layout Considerations Digital or AC transient signals between AGND and DGND can create noise at the analog outputs. Tie AGND and DGND together at the DAC, then tie this point to the highest quality ground available. Good PCB ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Wire-wrapped boards are not recommended. 22

23 Calibrated, Quad, 2-Bit Ordering Information (continued) PART TEMP RANGE PIN- PACKAGE +Denotes a lead(pb)-free/rohs-compliant package. INL (LSB) ACPE+ C to +7 C 6 PDIP ±.5 BCPE+ C to +7 C 6 PDIP ± ACWE+ C to +7 C 6 Wide SO ±.5 BCWE+ C to +7 C 6 Wide SO ± AEPE+ -4 C to +85 C 6 PDIP ±.5 BEPE+ -4 C to +85 C 6 PDIP ± AEWE+ -4 C to +85 C 6 Wide SO ±.5 BEWE+ -4 C to +85 C 6 Wide SO ± Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 6 PDIP P SO W

24 Calibrated, Quad, 2-Bit REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED /94 Initial release 3 3/ Removed dice and ceramic SB packages and changed voltage supply specifications 7, 3, 2, 22, 23 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.