Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510

Transcription

1 9-55; Rev 3; / Quad, Serial 8-Bit DACs General Description The MAX59/MAX5 are quad, serial-input, 8-bit voltage-output digital-to-analog converters (DACs). They operate with a single supply or dual ±5V supplies. Internal, precision buffers swing rail-to-rail. The reference input range includes both supply rails. The MAX59 has four separate reference inputs, allowing each DAC's full-scale range to be set independently. -pin DIP, SSOP, and SO packages are available. The MAX5 is identical to the MAX59 except it has two reference inputs, each shared by two DACs. The MAX5 is housed in space-saving -pin DIP and SO packages. The serial interface is double-buffered: A -bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. A -bit serial word is used to load data into each register. Both input and DAC registers can be updated independently or simultaneously with single software commands. Two additional asynchronous control pins provide simultaneous updating (LDAC) or clearing (CLR) of input and DAC registers. The interface is compatible with MICROWIRE TM and SPI/QSPI TM. All digital inputs and outputs are TTL/CMOS compatible. A buffered data output provides for readback or daisy-chaining of serial devices. Functional Diagrams Features Single or Dual ±5V Supply Operation Output Buffer Amplifiers Swing Rail-to-Rail Reference Input Range Includes Both Supply Rails Calibrated Offset, Gain, and Linearity (LSB TUE) MHz Serial Interface, Compatible with SPI, QSPI (CPOL = CPHA = ) and MICROWIRE Double-Buffered Registers for Synchronous Updating Serial Data Output for Daisy-Chaining Power-On Reset Clears Serial Interface and Sets All Registers to Zero Ordering Information PART TEMP RANGE PIN-PACKAGE TUE (LSB) MAX59ACPP+ C to +7 C PDIP ± MAX59BCPP+ C to +7 C PDIP ±.5 MAX59ACWP+ C to +7 C Wide SO ± MAX59BCWP+ C to +7 C Wide SO ±.5 MAX59ACAP+ C to +7 C SSOP ± Ordering Information continued on last page. **Contact factory for availability and processing to MIL-STD Denotes a lead(pb)-free/rohs-compliant package. Pin Configurations MAX59/MAX5 CLR DOUT LDAC AGND DGND V SS REFB REFA DECODE CONTROL INPUT REG A MAX59 DAC REG A DAC A TOP VIEW OUTB 9 -BIT SHIFT REGISTER INPUT REG B INPUT REG C DAC REG B DAC REG C DAC B DAC C OUTB V SS REFB REFA AGND N.C. DGND MAX REFC REFD N.C. SR CONTROL INPUT REG D DAC REG D DAC D LDAC 9 DOUT DIP/SO/SSOP CLR REFC REFD Functional Diagrams continued at end of data sheet. Pin Configurations continued at end of data sheet. MICROWIRE is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 MAX59/MAX5 ABSOLUTE MAXIMUM RATINGS to DGND...-.3V, +V to AGND...-.3V, +V V SS to DGND...-V, +.3V V SS to AGND...-V, +.3V to V SS...-.3V, +V Digital Input Voltage to DGND...-.3V, ( +.3V) REF_...(V SS -.3V), ( +.3V) OUT_..., V SS Maximum Current into Any Pin...5mA Continuous Power Dissipation (T A = +7 C) -Pin Plastic DIP (derate.53mw/ C above +7 C)...84mW -Pin Wide SO (derate 9.5mW/ C above +7 C)...7mW -Pin CERDIP (derate.mw/ C above +7 C)...8mW -Pin Plastic DIP (derate.mw/ C above +7 C)...889mW -Pin Wide SO (derate.mw/ C above +7 C)...8mW -Pin SSOP (derate.mw/ C above +7 C)...8mW -Pin CERDIP (derate.mw/ C above +7 C)...889mW Operating Temperature Ranges: MAX5 _C... C to +7 C MAX5 _E...-4 C to +85 C MAX5 _MJ_ C to +5 C Storage Temperature Range...-5 C to +5 C Lead Temperature (soldering, s)...+3 C Soldering Temperature (reflow) Lead (Pb)-free packages...+ C Packages containing lead (Pb)...+ C Note: The outputs may be shorted to, V SS, or AGND if the package power dissipation is not exceeded. Typical short-circuit current to AGND is 5mA. Do not bias AGND more than +V above DGND, or more than.5v below DGND. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI ( = ±%, V SS = V to -5.5V, V REF = 4V, AGND = DGND = V, R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution 8 Bits VREF = +4V, MAX5 A ± Total Unadjusted Error TUE V SS = V or -5V ±% MAX5 B ±.5 VREF = -4V, MAX5 A ± LSB V SS = -5V ±% MAX5 B ±.5 Differential Nonlinearity DNL Guaranteed monotonic ± LSB Zero-Code Error Code = hex, V SS = V Code = hex, V SS = -5V ±% Code = FF hex MAX5 C MAX5 E MAX5 M MAX5 C MAX5 E Zero-Code-Error Supply Rejection Code = hex, = 5V ±%, V SS = V or -5V ±% mv Zero-Code Temperature Coefficient Code = hex ± µv/ C Full-Scale Error Code = FF hex ±4 mv Full-Scale-Error Supply Rejection Full-Scale-Error Temperature Coefficient ZCE Code = FF hex, = ±%, V SS = V or -5V ±% MAX5 M MAX5 C MAX5 E MAX5 M 4 ±4 ± ± 4 8 mv mv ± µv/ C

3 ELECTRICAL CHARACTERISTI (continued) ( = ±%, V SS = V to -5.5V, V REF = 4V, AGND = DGND = V, R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE INPUTS Input Voltage Range V SS V Input Resistance (Note ) Code = 55 hex MAX59 4 MAX5 8 kω Input Capacitance (Note ) Code = hex MAX59 5 MAX5 Channel-to-Channel Isolation (Note 3) - db AC Feedthrough (Note 4) -7 db DAC OUTPUTS Full-Scale Output Voltage V SS V Resistive Load DIGITAL INPUTS VREF = 4V, load regulation /4LSB VREF = -4V, V SS = -5V ±%, load regulation /4LSB VREF = MAX5 C/E, load regulation LSB VREF = MAX5 M, load regulation LSB Input High Voltage V IH.4 V Input Low Voltage V IL.8 V Input Current I IN V IN = V or. µa Input Capacitance C IN (Note 5) pf DIGITAL OUTPUTS Output High Voltage V OH I SOURCE =.ma -.5 V Output Low Voltage V OL I SINK =.ma.4 V DYNAMIC PERFORMANCE Voltage-Output Slew Rate Positive and negative MAX5 C. MAX5 E.7 MAX5 M Output Settling Time (Note ) To /LSB, kω II pf load µs Digital Feedthrough Code = hex, all digital inputs from V to 5 nv-s Digital-to-Analog Glitch Impulse Code 8 7 nv-s Signal-to-Noise + Distortion Ratio SINAD Multiplying Bandwidth VREF =.5V p-p, 3dB bandwidth Wideband Amplifier Noise.5 VREF = 4V p-p at khz, = 5V, code = FF hex 87 VREF = 4V p-p at khz, V SS = -5V ±% 74 3 pf kω V/µs db MHz µv RMS MAX59/MAX5 3

4 MAX59/MAX5 ELECTRICAL CHARACTERISTI (continued) ( = ±%, V SS = V to -5.5V, V REF = 4V, AGND = DGND = V, R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Positive Supply Voltage For specified performance V Negative Supply Voltage V SS For specified performance -5.5 V Positive Supply Current Outputs unloaded, all MAX5 C/E 5 I DD digital inputs = V or MAX5 M 5 ma V SS = -5V ±%, outputs MAX5 C/E 5 Negative Supply Current I SS unloaded, all digital ma inputs = V or MAX5 M 5 Note : Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note : Input capacitance is code dependent. The highest input capacitance occurs at code = hex. Note 3: VREF = 4V p-p, khz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to hex. Note 4: VREF = 4V p-p, khz. DAC code = hex. Note 5: Guaranteed by design. Note : Output settling time is measured by taking the code from hex to FF hex, and from FF hex to hex. TIMING CHARACTERISTI ( = ±%, V SS = V to -5V, V REF = 4V, AGND = DGND = V, C L = 5pF, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LDAC Pulse Width Low Rise to LDAC Fall Setup Time CLR Pulse Width Low t LDW t CLL t CLW MAX5 C/E 4 MAX5 M 5 5 (Notes 7, 8) ns MAX5 C/E 4 MAX5 M 5 5 SERIAL INTERFACE TIMING Fall to Setup Time t S MAX5 C/E 4 MAX5 M 5 ns Fall to Rise Hold Time t H ns Rise to Rise Hold Time t H (Note 9) 4 ns Fall to Fall Hold Time t H (Note 7) ns to Rise Setup Time MAX5 C/E 4 t DS MAX5 M 5 ns to Rise Hold Time t DH ns Clock Frequency f CLK MAX5 C/E.5 MAX5 M MHz Pulse Width High Pulse Width Low to DOUT Valid t CH t CL t DO MAX5 C/E MAX5 M 5 MAX5 C/E 4 MAX5 M 5 MAX5 C/E MAX5 M Note 7: Guaranteed by design. Note 8: If LDAC is activated prior to 's rising edge, it must stay low for t LDW or longer after goes high. Note 9: Minimum delay from th clock cycle to rise. 4 4 ns ns ns ns ns

5 Typical Operating Characteristics (T A = +5 C, unless otherwise noted.) IOUT (ma) 8 4 OUTPUT SINK CURRENT vs. (V OUT - V SS ) = VREF = V SS = GND = V ALL DIGITAL INPUTS = HEX V OUT - V SS (V) MAX59-FG IOUT (ma) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE = VREF = V SS = GND DIGITAL INPUT = FF HEX V OUT (V) MAX59-FG SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE I SS = +5.5V V SS = -5.5V VREF = ALL DIGITAL INPUTS = TEMPERATURE ( C) I DD MAX59-FG MAX59/MAX5 IDD (ma) V SS = -5V SUPPLY CURRENT vs. REFERENCE VOLTAGE = ALL LOGIC INPUTS = VREF VOLTAGE (V) V SS = V MAX59-FG3 THD + NOISE (db) THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE = V SS = -5V INPUT CODE = FF HEX FREQ = khz 4 8 REFERENCE AMPLITUDE (Vp-p) FREQ = khz MAX59-FG4 %.%.% THD + NOISE (%) THD + NOISE (db) THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY = V SS = -5V INPUT CODE = FF HEX FREQ = SWEPT VREF = Vp-p VREF = 8Vp-p VREF = 4Vp-p k k k REFERENCE FREQUENCY (Hz) MAX59-FG5 % %.%.% THD + NOISE (%) REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE MAX59-FG MAX59-FG7 MAX59-FG8 RELATIVE OUTPUT (db) = V SS = AGND VREF =.5VDC +.5Vp-p SINE WAVE RELATIVE OUTPUT (db) = V SS = AGND VREF =.5VDC +.5Vp-p SINE WAVE RELATIVE OUTPUT (db) = V SS = -5V VREF =.5VDC + 4Vp-p SINE WAVE k k k FREQUENCY (Hz) M M k k k FREQUENCY (Hz) M M k k k FREQUENCY (Hz) M M 5

6 Quad, Serial 8-DACs MAX59/MAX5 ZERO-CODE ERROR (mv) Typical Operating Characteristics (continued) (T A = +5 C, unless otherwise noted.) ZERO-CODE ERROR vs. NEGATIVE SUPPLY VOLTAGE V SS (V) = VREF = +4V -5 - MAX59-FG9 WORST-CASE LSB DIGITAL STEP CHANGE V A =, V/div B =, mv TIMEBASE = ns/div mv ns A B REFERENCE FEEDTHROUGH AT 4kHz A = REFA, V p-p B =, μv/div, UNLOADED TIMEBASE = μs/div =, V SS = -5V CODE = ALL s A B REFERENCE FEEDTHROUGH AT khz REFERENCE FEEDTHROUGH AT 4kHz REFERENCE FEEDTHROUGH AT 4Hz 5V 5μV A A A B B B μs A = REFA, V p-p B =, 5μV/div, UNLOADED TIMEBASE = 5μs/div A = REFA, V p-p B =, 5μV/div, UNLOADED TIMEBASE = μs/div A = REFA, V p-p B =, 5μV/div, UNLOADED TIMEBASE = ms/div

7 Typical Operating Characteristics (continued) (T A = +5 C, unless otherwise noted.) CLOCK FEEDTHROUGH A B 5V POSITIVE SETTLING TIME (V SS = AGND OR -5V) mv μs A B MAX59/MAX5 A =, 333kHz B = OUT_, mv/div TIMEBASE = μs/div A = DIGITAL INPUT, 5V/div B = OUT_, V/div TIMEBASE = μs/div = REF_ = +4V ALL BITS OFF TO ALL BITS ON R L = kω, C L = pf NEGATIVE SETTLING TIME (V SS = AGND) NEGATIVE SETTLING TIME (V SS = -5V) 5V mv 5V mv A A B B μs μs A = DIGITAL INPUT, 5V/div B = OUT_, V/div TIMEBASE = μs/div = REF_ = +4V ALL BITS ON TO ALL BITS OFF R L = kω, C L = pf A = DIGITAL INPUT, 5V/div B = OUT_, V/div TIMEBASE = μs/div = REF_ = +4V ALL BITS ON TO ALL BITS OFF R L = kω, C L = pf 7

8 MAX59/MAX5 Pin Description PIN MAX59 MAX5 NAME FUNCTION OUTB DAC B Voltage Output DAC A Voltage Output 3 3 V SS Negative Power Supply, V to -5V ±%. Connect to AGND for single-supply operation. 4 REFB Reference Voltage Input for DAC B 4 REFAB Reference Voltage Input for DACs A and B 5 REFA Reference Voltage Input for DAC A 5 AGND Analog Ground 7, 4 N.C. Not Internally Connected 8 DGND Digital Ground 9 7 LDAC 8 DOUT 9 CLR 3 5 Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents of each input latch to its respective DAC latch. Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be clocked out on rising or falling edge of. Clear DAC input (active low). Driving CLR low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. Serial Data Input. TTL/CMOS-compatible input. Data is clocked into on the rising edge of. must be low for data to be clocked in. Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the rising (default) or the falling edge. Chip-Select Input (active low). Data is shifted in and out when is low. Programming commands are executed when rises. REFD Reference Voltage Input for DAC D 3 REFCD Reference Voltage Input for DACs C and D 7 REFC Reference Voltage Input for DAC C 8 4 Positive Power Supply, ±% 9 5 DAC D Output Voltage DAC C Output Voltage 8

9 Detailed Description Serial Interface At power-on, the serial interface and all DACs are cleared and set to code zero. The serial data output (DOUT) is set to transition on 's rising edge. The MAX59/MAX5 communicate with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure ). Data is sent MSB first and can be transmitted in one 4-bit and one 8-bit (byte) packet or in one -bit word. If a -bit control word is used, the first four bits are ignored. A 4-wire interface adds a line for LDAC and allows asynchronous updating. The serial clock () synchronizes the data transfer. Data is transmitted and received simultaneously. Figure shows a detailed serial interface timing. Please note that the clock should be low if it is stopped between updates. DOUT does not go into a highimpedance state if the clock or is high. Serial data is clocked into the data registers in MSBfirst format, with the address and configuration information preceding the actual DAC data. Data is clocked in on 's rising edge while is low. Data at DOUT is clocked out clock cycles later, either at 's rising edge (default or mode ) or falling edge (mode ). Chip select () must be low to enable the DAC. If is high, the interface is disabled and DOUT remains unchanged. must go low at least 4ns before the first rising edge of the clock pulse to properly clock in the first bit. With low, data is clocked into the MAX59/MAX5's internal shift register on the rising edge of the external serial clock. can be driven at rates up to.5mhz. MAX59/MAX5 INSTRUCTION EXECUTED A A C C D7 D D5 D4 D3 D D D A A A C C D7 D D5 D4 D3 D D D MSB LSB A MSB LSB DOUT MODE (DEFAULT) DACA DACD A A C C D7 D D5 D4 D3 D D D A A A C C D7 D D5 D4 D3 D D D A DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT DOUT MODE A A C C D7 D D5 D4 D3 D D D A A A C C D7 D D5 D4 D3 D D D A Figure. MAX59/MAX5 3-Wire Interface Timing 9

10 MAX59/MAX5 t H t S tch t DS t DH t DO t CL t H t H t CLL DOUT LDAC NOTE: TIMING SPECIFICATION t CLL IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY. t LDW Figure. Detailed Serial Interface Timing (Mode Shown) Table. Serial-Interface Programming Commands A A -Bit Serial Word C C D D 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data LDAC Function Load DAC A input register, DAC output unchanged. Load DAC B input register, DAC output unchanged. Load DAC C input register, DAC output unchanged. Load DAC D input register, DAC output unchanged. 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data Load input and DAC register A. Load input and DAC register B. Load input and DAC register C. Load input and DAC register D. X X 8-Bit DAC Data X X X X X X X X X X Update all DACs from shift register. No Operation (NOP), shifts data in shift register. X X X X X X X X X X LDAC Command, all DACs updated from respective input registers. X X X X X X X X X Mode, DOUT clocked out on rising edge of (default). All DACs updated from respective input registers. X X X X X X X X X Mode, DOUT clocked out on falling edge of. All DACs updated from input registers.

11 Serial Input Data Format and Control Codes The -bit serial input format shown in Figure 3 comprises two DAC address bits (A, A), two control bits (C, C) and eight bits of data (D...D7). The 4-bit address/control code configures the DAC as shown in Table. DOUT This is the first bit shifted in MSB A A C C D7 D D D Control and Address bits Figure 3. Serial Input Format A Address Load Input Register, DAC Registers Unchanged (Single Update Operation) (LDAC = H) When performing a single update operation, A and A select the respective input register. At the rising edge of, the selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This preloads individual data in the input register without changing the DAC outputs. A A A Address (LDAC = H) C C C C D7 D7 D 8-bit DAC data LSB Load Input and DAC Registers D This command directly loads the selected DAC register at 's rising edge. A and A set the DAC address. Current shift-register data is placed in the selected input and DAC registers. For example, to load all four DAC registers simultaneously with individual settings (DAC A = V, DAC B = V, DAC C = 3V and DAC D = 4V), five commands are required. First, perform four single input register update operations. Next, perform an LDAC command as a fifth command. All DACs will be updated from their respective input registers at the rising edge of. D5 D5 D4 8-Bit Data D4 D3 D3 8-Bit Data D D D D D D A x (LDAC = x) Update All DACs from Shift Registers All four DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. This command can be used to substitute CLR if code hex is programmed, which clears all DACs. A x (LDAC = x) No Operation (NOP) The NOP command (no operation) allows data to be shifted through the MAX59/MAX5 shift register without affecting the input or DAC registers. This is useful in daisy chaining (also see the Daisy-Chaining Devices section). For this command, the data bits are "Don't Cares." As an example, three MAX59/MAX5s are daisy-chained (A, B and C), and DAC A and DAC C need to be updated. The 3-bit-wide command would consist of one -bit word for device C, followed by an NOP instruction for device B and a third -bit word with data for device A. At 's rising edge, only device B is not updated. A (LDAC = x) LDAC Command (Software) All DAC registers are updated with the contents of their respective input registers at 's rising edge. With the exception of using to execute, this performs the same function as the asynchronous LDAC. A A A A Set DOUT Phase Rising (Mode, Default) A x x x x x x x x (LDAC = x) C C C C C C C C D7 D7 D7 D D D 8-Bit DAC Data Mode resets the serial output DOUT to transition at 's rising edge. This is the MAX59/MAX5 s default setting after the supply voltage has been applied. The command also loads all DAC registers with the contents of their respective input registers, and is identical to the LDAC command. D5 D5 D5 D4 D4 D4 D3 D3 D3 D D D D D D D D x x x x x x x x D7 D x x x x x x x x x D5 D4 D3 D D D D MAX59/MAX5

12 MAX59/MAX5 Set DOUT Phase Falling (Mode ) A A C C D7 D D5 D4 D3 D D D (LDAC = x) x x x x x x x x This command resets DOUT to transition at 's falling edge. Once this command is issued, the phase of DOUT is latched and will not change except on power-up or if the specific command is issued that sets the phase to rising edge. The same command also updates all DAC registers with the contents of their respective input registers, identical to the LDAC command. LDAC Operation (Hardware) LDAC is typically used in 4-wire interfaces (Figure 7). LDAC allows asynchronous hardware control of the DAC outputs and is level-sensitive. With LDAC low, the DAC registers are transparent and any time an input register is updated, the DAC output immediately follows. Clear DACs with CLR Strobing the CLR pin low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. Similar to the LDAC pin, CLR can be invoked at any time, typically when the device is not selected ( = H). When the DAC data is all zeros, this function is equivalent to the "Update all DACs from Shift Registers" command. Digital Inputs and Outputs Digital inputs and outputs are compatible with both TTL and 5V CMOS logic. The power-supply current (I DD ) depends on the input logic levels. Using CMOS logic to drive,,, CLR and LDAC turns off the internal level translators and minimizes supply currents. Serial Data Output DOUT is the output of the internal shift register. DOUT can be programmed to clock out data on 's falling edge (mode ) or rising edge (mode ). In mode, output data lags the input data by.5 clock cycles, maintaining compatibility with Microwire, SPI, and QSPI. In mode, output data lags the input by clock cycles. On power-up, DOUT defaults to mode timing. DOUT never three-states; it always actively drives either high or low and remains unchanged when is high. Interfacing to the Microprocessor The MAX59/MAX5 are Microwire, SPI, and QSPI compatible. For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = ). The SPI/QSPI CPOL = CPHA = configuration can also be used if the DOUT output is ignored. MAX59 MAX5 DOUT The MAX59/MAX5 can interface with Intel's 8C5X/8C3X family in mode if the clock polarity is inverted. More universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. Digital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. Also see the Clock Feedthrough photo in the Typical Operating Characteristics section. The clock idle state is low. Daisy-Chaining Devices Any number of MAX59/MAX5s can be daisy-chained by connecting the DOUT pin of one device to the pin of the following device in the chain. The NOP instruction (Table ) allows data to be passed from to DOUT without changing the input or DAC registers of the passing device. A threewire interface updates daisy-chained or individual MAX59/MAX5s simultaneously by bringing high. SK SO SI I/ MICROWIRE PORT THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX59/MAX5, BUT MAY BE USED FOR READ-BACK PURPOSES. Figure 4. Connections for MICROWIRE MAX59 MAX5 DOUT MISO MOSI SCK I/ SPI PORT CPOL =, CPHA = THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX59/MAX5, BUT MAY BE USED FOR READ-BACK PURPOSES. Figure 5. Connections for SPI

13 MAX59 MAX5 MAX59 MAX5 DOUT DOUT DOUT MAX59 MAX5 MAX59 MAX5 TO OTHER SERIAL DEVICES MAX59/MAX5 Figure. Daisy-chained or individual MAX59/MAX5s are simultaneously updated by bringing high. Only three wires are required. LDAC 3 TO OTHER SERIAL DEVICES LDAC MAX59 MAX5 LDAC MAX59 MAX5 LDAC MAX59 MAX5 Figure 7. Multiple MAX59/MAX5 DACs sharing one line. Simultaneously update by strobing LDAC, or specifically update by enabling individual. 3

14 MAX59/MAX5 REF_ AGND R R R R R SHOWN FOR ALL ON DAC R R R D D5 D D7 Figure 8. DAC Simplified Circuit Diagram OUT_ If multiple devices share a common line, Figure 7's configuration provides simultaneous update by strobing LDAC low.,, 3... are driven separately, thus controlling which data are written to devices,, 3... Analog Section DAC Operation The MAX59/MAX5 contain four matched voltageoutput DACs. The DACs are inverted R-R ladder networks that convert 8-bit digital words into equivalent analog output voltages in proportion to the applied reference voltages. Each DAC in the MAX59 has a separate reference input, while the two reference inputs in the MAX5 each share a pair of DACs. The two reference inputs permit different full-scale output voltage ranges for each pair of DACs. A simplified diagram of one of the four DACs is shown in Figure 8. Reference Input The MAX59/MAX5 can be used for multiplying applications. The reference accepts both DC and AC signals. The voltage at each REF input sets the fullscale output voltage for its respective DAC(s). If the reference voltage is positive, both the MAX59 and MAX5 can be operated from a single supply. If dual supplies are used, the reference input can vary from VSS to, but is always referred to AGND. The input impedance at REF is code dependent, with the lowest value (kω for the MAX59 and 8kΩ for the MAX5) occurring when the input code is 55 hex or. The maximum value, practically infinity, occurs when the input code is hex. Since the REF input impedance is code dependent, the DAC's reference sources must have a low output impedance (no more than 3Ω for the MAX59 and Ω for the MAX5) to maintain output linearity. The REF input capacitance is also code dependent: 5pF typical for the MAX59 and 3pF typical for the MAX5. The output voltage for any DAC can be represented by a digitally programmable voltage source as: VOUT = (NB x VREF) / 5 where NB is the numerical value of the DAC's binary input code. Output Buffer Amplifiers All MAX59/MAX5 voltage outputs are internally buffered by precision unity-gain followers that slew at up to V/µs. The outputs can swing from VSS to VDD. With a V to +4V (or +4V to V) output transition, the amplifier outputs will settle to /LSB in typically µs when loaded with kω in parallel with pf. The buffer amplifiers are stable with any combination of resistive loads kω and capacitive loads 3pF. Applications Information Power Supply and Reference Operating Ranges The MAX59/MAX5 are fully specified to operate with VDD = 5V ±% and VSS = V to -5.5V. 8-bit performance is guaranteed for both single- and dual-supply operation. The zero-code output error is less than 4mV when operating from a single supply. The DACs work well with reference voltages from VSS to. The reference voltage is referred to AGND. The preferred power-up sequence is to apply V SS and then VDD, but bringing up both supplies at the same time is also acceptable. In either case, the voltage applied to REF should not exceed VDD during powerup or at any other time. If proper power sequencing is not possible, connect an external Schottky diode between VSS and AGND to ensure compliance with the Absolute Maximum Ratings. Do not apply signals to the digital inputs before the device is fully powered up. Power-Supply Bypassing and Ground Management In single-supply operation (AGND = DGND = VSS = V), AGND, DGND and VSS should be connected together in a "star" ground at the chip. This ground should then return to the highest quality ground available. Bypass VDD with a.µf capacitor, located as close to and DGND as possible. In dual-supply operation, bypass VSS to AGND with.µf. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figures 9 and show suggested circuit board layouts to minimize crosstalk. 4

15 REFC REFD SYSTEM GND OUTB V SS REFB REFA AGND REFCD SYSTEM GND OUTB V SS REFAB AGND MAX59/MAX5 Figure 9. Suggested MAX59 PC Board Layout for Minimizing Crosstalk (Bottom View) Unipolar-Output, -Quadrant Multiplication In unipolar operation, the output voltages and the reference input(s) are the same polarity. Figures and show the MAX59/MAX5 unipolar configurations. Both devices can be operated from a single supply if the reference inputs are positive. If dual supplies are used, the reference input can vary from VSS to. Table shows the unipolar code. Table. Unipolar Code Table DAC CONTENTS MSB LSB ANALOG OUTPUT +V 55 REF ( ) 5 +V 9 REF ( ) 5 8 V REF +V REF ( ) = V REF ( ) 5 +V REF ( ) 5 V Figure. Suggested MAX5 PC Board Layout for Minimizing Crosstalk (Bottom View) Bipolar-Output, -Quadrant Multiplication Bipolar-output, -quadrant multiplication is achieved by offsetting AGND positively or negatively. Table 3 shows the bipolar code. AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a input code, as shown in Figure 3. The output voltage at is: V = V BIAS + (NB/5)(V IN ), Table 3. Bipolar Code Table DAC CONTENTS MSB LSB ANALOG OUTPUT +V 7 REF ( ) 8 +V REF ( ) 8 V -V REF ( ) 8 7 -V REF ( ) 8 8 -V REF ( ) = -V REF 8 Note: LSB = (V REF ) ( -8 ) = +V REF ( ) 5 5

16 MAX59/MAX5 SERIAL INTERFACE NOT SHOWN REFERENCE INPUTS (V SS TO ) REFA REFB REFC REFD DAC A DAC B DAC C OUTB V IN V BIAS 5 8 REFA DAC A AGND MAX59 V SS DGND 3 8-5V (OR GND) DAC D REFAB MAX59 V SS AGND DGND 3 8-5V (OR GND) Figure. MAX59 Unipolar Output Circuit V IN V BIAS 5 AGND DAC A V SS MAX5 DGND 3 REFERENCE INPUTS (V SS TO ) 4 4 REFAB DAC A -5V (OR GND) SERIAL INTERFACE NOT SHOWN Figure 3. MAX59/MAX5 AGND Bias Circuits (Positive Offset) SERIAL INTERFACE NOT SHOWN MAX5 DAC B DAC C DAC D V SS REFCD AGND DGND 3-5V (OR GND) 3 5 Figure. MAX5 Unipolar Output Circuit 5 OUTB where NB represents the digital input word. Since AGND is common to all four DACs, all outputs will be offset by V BIAS in the same manner. Do not bias AGND more than +V above DGND, or more than.5v below DGND. Figures 4 and 5 illustrate the generation of negative offsets with bipolar outputs. In these circuits, AGND is biased negatively (up to -.5V with respect to DGND) to provide an arbitrary negative output voltage for a input code. The output voltage at is: = -(R/R)(.5V) + (NB/5)(.5V)(R/R+) where NB represents the digital input word. Since AGND is common to all four DACs, all outputs will be offset by V BIAS in the same manner. Table 3, with V REF =.5V, shows the digital code vs. output voltage for Figure 4 and 5's circuits with R = R. The ICL7 op amp is chosen because its common-mode range extends to both supply rails.

17 MAX873.μF +.5V SERIAL INTERFACE NOT SHOWN R 33k.% R 33k.% REFERENCE INPUTS MAX59 DAC A DAC B.μF OUTB MAX59/MAX5 7.μF DAC C ICL7A 3 8.μF DAC D 9-5V.μF V SS AGND DGND 3 8-5V Figure 4. MAX59 AGND Bias Circuit (Negative Offset) 4-Quadrant Multiplication Each DAC output may be configured for 4-quadrant multiplication using Figure and 7's circuit. One op amp and two resistors are required per channel. With R = R: V OUT = V REF [(NB/5)-] where NB represents the digital word in DAC register A. The recommended value for resistors R and R is 33kΩ (±.%). Table 3 shows the digital code vs. output voltage for Figure and 7's circuit. 7

18 MAX59/MAX5 MAX873 4.μF +.5V SERIAL INTERFACE NOT SHOWN R 33k.% ICL7A 3 7-5V R 33k.% 8.μF.μF.μF REFERENCE INPUTS MAX5-5V DAC A DAC B DAC C DAC D V SS AGND DGND 5 5.μF OUTB Figure 5. MAX5 AGND Bias Circuit (Negative Offset) REFERENCE INPUTS (V SS TO ) μF R R.μF DAC A MAX59 ICL7A* V OUT SERIAL INTERFACE NOT SHOWN DAC B OUTB -5V.μF.μF DAC C R R DAC D V SS AGND DGND 3 8.μF AGND OR -5V 9 ICL7A* V OUT.μF -5V *CONNECT ICL7A PIN 8 TO AGND Figure. MAX59 Bipolar Output Circuit 8

19 SERIAL INTERFACE NOT SHOWN REFERENCE INPUTS DAC A DAC B DAC C MAX5.μF OUTB R ICL7A* R -5V.μF R.μF.μF V OUT MAX59/MAX5 DAC D 5 ICL7A* R V OUT.μF V SS AGND DGND 3 5-5V.μF AGND OR -5V *CONNECT ICL7A PIN 8 TO AGND Figure 7. MAX5 Bipolar Output Circuit Functional Diagrams (continued) Pin Configurations (continued) CLR DOUT LDAC AGND DGND V SS REFAB DECODE CONTROL INPUT REG A MAX5 DAC REG A DAC A TOP VIEW OUTB 5 -BIT SHIFT REGISTER INPUT REG B DAC REG B DAC B OUTB V SS 3 REFAB 4 AGND 5 MAX5 4 3 REFCD INPUT REG C DAC REG C DAC C DGND LDAC 7 DOUT 8 9 CLR SR CONTROL INPUT REG D DAC REG D DAC D DIP/Wide SO REFCD 9

20 MAX59/MAX5 _Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE TUE (LSB) MAX59BCAP+ C to +7 C SSOP ±.5 MAX59AEPP+ -4 C to +85 C PDIP ± MAX59BEPP+ -4 C to +85 C PDIP ±.5 MAX59AEWP+ -4 C to +85 C Wide SO ± MAX59BEWP+ -4 C to +85 C Wide SO ±.5 MAX59AEAP+ -4 C to +85 C SSOP ± MAX59BEAP+ -4 C to +85 C SSOP ±.5 MAX59AMJP -55 C to +5 C CERDIP** ± MAX59BMJP -55 C to +5 C CERDIP** ±.5 MAX5ACPE+ C to +7 C PDIP ± MAX5BCPE+ C to +7 C PDIP ±.5 MAX5ACWE+ C to +7 C Wide SO ± MAX5BCWE+ C to +7 C Wide SO ±.5 MAX5AEPE+ -4 C to +85 C PDIP ± MAX5BEPE+ -4 C to +85 C PDIP ±.5 MAX5AEWE+ -4 C to +85 C Wide SO ± MAX5BEWE+ -4 C to +85 C Wide SO ±.5 MAX5AMJE -55 C to +5 C CERDIP** ± MAX5BMJE -55 C to +5 C CERDIP** ±.5 **Contact factory for availability and processing to MIL-STD Denotes a lead(pb)-free/rohs-compliant package. Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. PDIP P+3-43 Wide SO W SSOP AA CERDIP J- -45 PDIP P+ -43 Wide SO W CERDIP J-3-45

21 REVISION NUMBER REVISION DATE 3 / DESCRIPTION Updated Ordering Information, added soldering temperature to Absolute Maximum Ratings, updated Figure 7 and Functional Diagrams Revision History PAGES CHANGED,, 9, MAX59/MAX5 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

22 MAX59/MAX5 _Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE TUE (LSB) MAX59BCAP+ C to +7 C SSOP ±.5 MAX59AEPP+ -4 C to +85 C PDIP ± MAX59BEPP+ -4 C to +85 C PDIP ±.5 MAX59AEWP+ -4 C to +85 C Wide SO ± MAX59BEWP+ -4 C to +85 C Wide SO ±.5 MAX59AEAP+ -4 C to +85 C SSOP ± MAX59BEAP+ -4 C to +85 C SSOP ±.5 MAX59AMJP -55 C to +5 C CERDIP** ± MAX59BMJP -55 C to +5 C CERDIP** ±.5 MAX5ACPE+ C to +7 C PDIP ± MAX5BCPE+ C to +7 C PDIP ±.5 MAX5ACWE+ C to +7 C Wide SO ± MAX5BCWE+ C to +7 C Wide SO ±.5 MAX5AEPE+ -4 C to +85 C PDIP ± MAX5BEPE+ -4 C to +85 C PDIP ±.5 MAX5AEWE+ -4 C to +85 C Wide SO ± MAX5BEWE+ -4 C to +85 C Wide SO ±.5 MAX5AMJE -55 C to +5 C CERDIP** ± MAX5BMJE -55 C to +5 C CERDIP** ±.5 **Contact factory for availability and processing to MIL-STD Denotes a lead(pb)-free/rohs-compliant package. Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. PDIP P+3-43 Wide SO W SSOP AA CERDIP J- -45 PDIP P+ -43 Wide SO W CERDIP J-3-45