MAX517BCPA SCL SDA. Maxim Integrated Products 1

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1 9-393; Rev ; 9/2 2-Wire Serial 8-Bit DACs with General Description The MAX57/MAX58/MAX59 are 8-bit voltage output digital-to-analog converters (DACs) with a simple 2-wire serial interface that allows communication between multiple devices. They operate from a single 5V supply and their internal precision buffers allow the DAC outputs to swing rail-to-rail. The MAX57 is a single DAC and the MAX58/MAX59 are dual DACs. The MAX58 uses the supply voltage as the reference f both DACs. The MAX57 has a reference input f its single DAC and each of the MAX59 s two DACs has its own reference input. The MAX57/MAX58/MAX59 feature a serial interface and internal software protocol, allowing communication at data rates up to 4kbps. The interface, combined with the double-buffered input configuration, allows the DAC registers of the dual devices to be updated individually simultaneously. In addition, the devices can be put into a low-power shutdown mode that reduces supply current to 4µA. Power-on reset ensures the DAC outputs are at V when power is initially applied. The MAX57/MAX58 are available in space-saving 8- pin DIP and SO packages. The MAX59 comes in 6- pin DIP and SO packages. Applications Minimum Component Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment Programmable Attenuats Features Single +5V Supply Simple 2-Wire Serial Interface I 2 C Compatible Output Buffer Amplifiers Swing Rail-to-Rail Space-Saving 8-pin DIP/SO Packages (MAX57/MAX58) Reference Input Range Includes Both Supply Rails (MAX57/MAX59) Power-On Reset Clears All Latches 4µA Power-Down Mode Ordering Infmation PART TEMP RANGE PIN-PAGE TUE (LSB) MAX57ACPA MAX57BCPA MAX57ACSA C to +7 C C to +7 C C to +7 C 8 Plastic DIP 8 Plastic DIP 8 SO.5 MAX57BCSA C to +7 C 8 SO.5 MAX57BC/D C to +7 C Dice*.5 Ordering Infmation continued at end of data sheet. *Dice are specified at T A = +25 C, DC parameters only. **Contact facty f availability and processing to MIL-STD-883. Functional Diagram INPUT LATCH OUTPUT LATCH V DD 7 REF DAC OUT MAX57/MAX58/MAX59 Pin Configurations TOP VIEW INPUT LATCH OUTPUT LATCH REF DAC 8 OUT OUT GND MAX57 MAX58 DIP/SO OUT (REF) V DD AD AD ( ) ARE FOR MAX57 Pin Configurations continued at end of data sheet BIT SHIFT REGISTER DECODE 6 5 AD AD ADDRESS COMPARATOR / DETECTOR MAX58 2 GND Maxim Integrated Products F pricing, delivery, and dering infmation, please contact Maxim/Dallas Direct! at , visit Maxim s website at

2 MAX57/MAX58/MAX59 ABSOLUTE MAXIMUM RATINGS V DD to GND...-.3V to +6V OUT_...-.3V to (V DD +.3V) REF_ (MAX57, MAX59)...-.3V to (V DD +.3V) AD_...-.3V to (V DD +.3V), to GND...-.3V to +6V Maximum Current into Any Pin...5mA Continuous Power Dissipation (T A = +7 C) 8-Pin Plastic DIP (derate 9.9mW/ C above +7 C)...727mW 8-Pin SO (derate 5.88mW/ C above +7 C)...47mW 8-Pin CERDIP (derate 8.mW/ C above +7 C)...64mW 6-Pin Plastic DIP (derate.53mw/ C above +7 C)..842mW 6-Pin Narrow SO (derate 8.7mW/ C above +7 C)...696mW 6-Pin CERDIP (derate.mw/ C above +7 C)...8mW Operating Temperature Ranges MAX5_C... C to +7 C MAX5_E...-4 C to +85 C MAX5_MJB C to +25 C Stage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions f extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = 5V ±%, V REF_ = 4V (MAX57, MAX59), R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are T A = +25 C.) PARAMETER SYMBOL S MIN TYP MAX UNITS STATIC ACCURACY Resolution 8 Bits Total Unadjusted Err (Note ) TUE MAX5 _A ± MAX5 _B ±.5 LSB Differential Nonlinearity (Note ) DNL Guaranteed monotonic ± LSB MAX5 _C 8 Zero-Code Err ZCE Code = hex MAX5 _E 2 mv MAX5 _BM 2 MAX5 _C ± Zero-Code-Err Supply Rejection Code = hex MAX5 _E ± mv MAX5 _BM ± Zero-Code-Err Temperature Coefficient Code = hex ± µv/ C Full-Scale Err Full-Scale-Err Supply Rejection Full-Scale-Err Temperature Coefficient Code = FF hex, MAX58 unloaded MAX57, MAX59 Code = FF hex V DD = +5V ±% Code = FF hex MAX5 _C MAX5 _E MAX5 _BM MAX5 _C MAX5 _E MAX5 _BM ±8 ±2 ±2 mv ± ± mv ± ± µv/ C 2

3 ELECTRICAL CHARACTERISTICS (continued) (V DD = 5V ±%, V REF_ = 4V (MAX57, MAX59), R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are T A = +25 C.) PARAMETER SYMBOL S MIN TYP MAX UNITS REFERENCE INPUTS (MAX57, MAX59) Input Voltage Range V DD V Input Resistance R IN Code = 55 hex (Note 2) 6 24 kω Input Current Power-down mode ± µa Input Capacitance Code = FF hex (Note 3) 3 pf Channel-to-Channel Isolation (MAX59) (Note 4) AC Feedthrough (Note 5) -7 db DAC OUTPUTS Full-Scale Output Voltage V DD V OUT_ = 4V, ma to 2.5mA.25 Output Load Regulation MAX5 _C/E, REF_ = V DD (MAX57, MAX59), code = FF hex, µa to 5µA MAX5 _M, REF_ = V DD (MAX57, MAX59), code = FF hex, µa to 5µA Output Leakage Current OUT_ = V to V DD, power-down mode ± µa DIGITAL INPUTS, Input High Voltage V IH.7V DD V Input Low Voltage V IL.3V DD V Input Leakage Current I IN V V IN V DD ± µa Input Hysteresis V HYST.5V DD V Input Capacitance C IN (Note 6) pf DIGITAL INPUTS AD, AD, AD2, AD3 Input High Voltage V IH 2.4 V Input Low Voltage V IL.8 V Input Leakage Current I IN V IN = V to V DD ± µa DIGITAL OUTPUT (Note 7) Output Low Voltage V OL I SINK = 3mA.4 I SINK = 6mA.6 V Three-State Leakage Current I L V IN = V to V DD ± µa Three-State Output Capacitance C OUT (Note 6) pf DYNAMIC PERFORMANCE MAX5 _C 2. Voltage Output Slew Rate Positive and negative MAX5 _E.4 V/µs MAX5 _M. Output Settling Time To /2 LSB, kω and pf load (Note 8) 6 µs Digital Feedthrough Code = hex, all digital inputs from V to V DD db LSB nv-s MAX57/MAX58/MAX59 3

4 MAX57/MAX58/MAX59 ELECTRICAL CHARACTERISTICS (continued) (V DD = 5V ±%, V REF_ = 4V (MAX57, MAX59), R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are T A = +25 C.) PARAMETER SYMBOL S MIN TYP MAX UNITS Digital-Analog Glitch Impulse Code 28 to 27 2 nv-s Signal to Noise + Disttion Ratio (MAX57, MAX59) Multiplying Bandwidth (MAX57, MAX59) TIMING CHARACTERISTICS (V DD = 5V ±%, T A = T MIN to T MAX, unless otherwise noted. Typical values are T A = +25 C.) PARAMETER SYMBOL S MIN TYP MAX UNITS Serial Clock Frequency f 4 khz Bus Free Time Between a and a Condition t BUF.3 µs Hold Time, (Repeated) Start Condition t HD, STA.6 µs Low Period of the Clock t LOW.3 µs High Period of the Clock t HIGH.6 µs Setup Time f a Repeated Condition t SU, STA.6 µs Data Hold Time t HD, DAT (Note 9).9 µs Data Setup Time t SU, DAT ns Rise Time of Both and Signals, Receiving t R (Note ) 2 +.Cb 3 ns Fall Time of Both and Signals, Receiving t F (Note ) 2 +.Cb 3 ns Fall Time of Transmitting t F I SINK 6mA (Notes 7, ) 2 +.Cb 25 ns Setup Time f Condition t SU, STO.6 µs Capacitive Load f Each Bus Line Cb 4 pf Pulse Width of Spike Suppressed t SP (Notes 6, ) 5 Note : Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: V SINAD REF_ = 4Vp-p at khz, V DD = 5V, 87 Code = FF hex V REF_ = 4Vp-p, 3dB bandwidth F the MAX58 (full-scale = V DD ) the last three codes are excluded from the TUE and DNL specifications, due to the limited output swing when loaded with kω to GND. Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Input capacitance is code dependent. The highest input capacitance occurs at code FF hex. VREF_ = 4V P-P, khz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to hex. VREF_ = 4Vp-p, khz, DAC code = hex. Guaranteed by design. I 2 C compatible mode. R PULLUP =.7kΩ. Output settling time is measured by taking the code from hex to FF hex, and from FF hex to hex. A master device must provide a hold time of at least 3ns f the signal (referred to V IL of the signal) in der to bridge the undefined region of s falling edge. Note : Cb = total capacitance of one bus line in pf. t R and t F measured between.3v DD and.7v DD. Note : Input filters on the and inputs suppress noise spikes less than 5ns. 4 ns db MHz Wideband Amplifier Noise 6 µv RMS POWER REQUIREMENTS Supply Voltage V DD V MAX57C.5 3. Nmal mode, output(s) MAX57E/M unloaded, all digital inputs Supply Current I DD at V V DD MAX58C, MAX59C ma MAX58E/M, MAX59E/M Power-down mode 4 2 µa

5 Typical Operating Characteristics (T A = +25 C, unless otherwise noted.) FULL-SCALE ERROR (LSB) SUPPLY CURRENT (ma) FULL-SCALE ERROR vs. SOURCE CURRENT (V REF = V DD ) V DD = V REF = 5V DAC CODE = FF HEX LOAD TO AGND OUTPUT SOURCE CURRENT (ma) MAX58 SUPPLY CURRENT vs. TEMPERATURE DAC CODE = B HEX V DD = 5.5V AD, AD = V DD DAC CODE = FF HEX DAC CODE = HEX MAX57- MAX57-4 ZERO-CODE ERROR (LSB) SUPPLY CURRENT (ma) ZERO-CODE ERROR vs. SINK CURRENT V DD = V REF = 5V DAC CODE = HEX LOAD to V DD OUTPUT SINK CURRENT (ma) MAX58 SUPPLY CURRENT vs. DAC CODE V DD = 5.5V BOTH DACS SET MAX57-2 MAX57-5 SUPPLY CURRENT (ma) SHUTDOWN SUPPLY CURRENT (µa) MAX57/MAX59 SUPPLY CURRENT vs. TEMPERATURE V DD = 5.5V REF_ INPUTS =.6V ALL DIGITAL INPUTS to V DD MAX59, DAC CODE = FF HEX MAX57, DAC CODE = FF HEX.5 MAX57, MAX59 DAC CODE = HEX TEMPERATURE ( C) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE V DD = 5.5V ALL DIGITAL INPUTS to V DD MAX57-3 MAX57-7 MAX57/MAX58/MAX TEMPERATURE ( C) DAC CODE (DECIMAL) TEMPERATURE ( C) SUPPLY CURRENT (ma) MAX57/MAX59 SUPPLY CURRENT vs. REFERENCE VOLTAGE MAX59 MAX57 V DD = 5V DAC CODE(S) FF HEX MAX57-8 RELATIVE OUTPUT (db) MAX57/MAX59 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE V P-P SINE 2V P-P SINE V P-P SINE.5V P-P SINE MAX57-9 POSITIVE FULL-SCALE STEP RESPONSE OUT V/div REFERENCE VOLTAGE (V) -6 k V DD = 5V V REF = SINE WAVE CENTERED AT 2.5V k k M M FREQUENCY (Hz) µs/div OUT LOADED WITH kω II pf REF = 4V (MAX57/MAX59) DAC CODE = HEX to FF HEX 5

6 MAX57/MAX58/MAX59 Typical Operating Characteristics (continued) (T A = +25 C, unless otherwise noted.) NEGATIVE FULL-SCALE STEP RESPONSE µs/div OUT LOADED WITH kω II pf REF = 4V (MAX57/MAX59) DAC CODE = FF HEX to HEX CLOCK FEEDTHROUGH OUT V/div A WORST-CASE LSB STEP CHANGE 5ns/div REF = 5V (MAX57/MAX59) DAC CODE = 8 HEX to 7F HEX MAX57/MAX59 REFERENCE FEEDTHROUGH AT khz OUT 2mV/div AC COUPLED A B B A =, 4kHz, 5V/div B = OUT, 5mV/div DAC CODE = 7F HEX REF = 5V (MAX57/MAX59) MAX57/MAX59 REFERENCE FEEDTHROUGH AT khz A = REF, V/div (4V P-P ) B = OUT, 5µV/div, UNLOADED FILTER PASSBAND = Hz to khz DAC CODE = HEX MAX57/MAX59 REFERENCE FEEDTHROUGH AT khz A A B B A = REF, V/div (4V P-P ) B = OUT, 5µV/div, UNLOADED FILTER PASSBAND = khz to khz DAC CODE = HEX A = REF, V/div (4V P-P ) B = OUT, 5µV/div, UNLOADED FILTER PASSBAND = khz to MHz DAC CODE = HEX 6

7 Pin Description PIN MAX57 MAX58 MAX59 NAME FUNCTION OUT DAC Voltage Output GND Ground 5 AD3 Address Input 3; sets IC s slave address Serial Clock Input Serial Data Input 9 AD2 Address Input 2; sets IC s slave address 5 5 AD Address Input ; sets IC s slave address 6 6 AD Address Input ; sets IC s slave address VDD Power Supply, +5V; used as reference f MAX58 3 REF Reference Voltage Input f DAC 8 5 REF Reference Voltage Input f DAC 8 6 OUT DAC Voltage Output 2, 3, 7, 4 N.C. No Connect not internally connected. INPUT LATCH INPUT LATCH 8-BIT SHIFT REGISTER DECODE AD (AD2) AD (AD3) ( ) ARE FOR MAX59 V DD OUTPUT LATCH OUTPUT LATCH ADDRESS COMPARATOR / DETECTOR REF DAC DAC (REF) MAX57/MAX59 Figure. MAX57/MAX59 Functional Diagram MAX59 ONLY GND OUT (OUT) Detailed Description Serial Interface The MAX57/MAX58/MAX59 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocess (µp) pt. Figure 2 shows the timing diagram f signals on the 2-wire bus. Figure 3 shows a typical application. The 2-wire bus can have several devices (in addition to the MAX57/ MAX58/MAX59) attached. The two bus lines ( and ) must be high when the bus is not in use. When in use, the pt bits are toggled to generate the appropriate signals f and. External pull-up resists are not required on these lines. The MAX57/MAX58/ MAX59 can be used in applications where pull-up resists are required (such as in I 2 C systems) to maintain compatibility with existing circuitry. The MAX57/MAX58/MAX59 are receive-only devices and must be controlled by a bus master device. They operate at rates up to 4kHz. A master device sends infmation to the devices by transmitting their address over the bus and then transmitting the desired infmation. Each transmission consists of a condition, the MAX57/MAX58/MAX59 s programmable slave-address, one me command-byte/output-byte pairs ( a command byte alone, if it is the last byte in the transmission), and finally, a condition (Figure 4). MAX57/MAX58/MAX59 7

8 MAX57/MAX58/MAX59 R C kω t HD, STA µc +5V AD AD AD2 AD3 AD AD AD AD t LOW DUAL DAC MAX59 OUT DUAL DAC MAX58 SINGLE DAC MAX57 t HIGH Figure 2. Two-Wire Serial Interface Timing Diagram REF REF OUT OUT OUT REF OUT +V +4V OFFSET ADJUSTMENT GAIN ADJUSTMENT BRIGHTNESS ADJUSTMENT CONTRAST ADJUSTMENT +2.5V THRESHOLD ADJUSTMENT Figure 3. MAX57/MAX58/MAX59 Application Circuit t R t BUF t SU, DAT t SU, STA t HD, STA t HD, t DAT SU, STO t F REPEATED The address byte and pairs of command and output bytes are transmitted between the and conditions. The state is allowed to change only while is low, with the exception of and conditions. s state is sampled, and therefe must remain stable while is high. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer the data bits to the MAX57/MAX58/MAX59. Set low during the 9th clock cycle as the MAX57/MAX58/MAX59 pull low during this time. R C (see Figure 3) limits the current that flows during this time if stays high f sht periods of time. The and Conditions When the bus is not in use, both and must be high. A bus master signals the beginning of a transmission with a condition by transitioning from high to low while is high (Figure 5). When the master has finished communicating with the slave, it issues a condition by transitioning from low to high while is high. The bus is then free f another transmission. The Slave Address The MAX57/MAX58/MAX59 each have a 7-bit long slave address (Figure 6). The first three bits (MSBs) of the slave address have been facty programmed and are always. In addition, the MAX57 and MAX58 have the next two bits facty programmed to s. The logic state of the address inputs (AD and AD on the MAX57/MAX58; AD, AD, AD2, and AD3 on the MAX59) determine the LSB bits of the 7-bit slave address. These input pins may be connected to VDD DGND, they may be actively driven by TTL CMOS logic levels. The MAX57/MAX58 have four possible slave addresses and therefe a maximum of four of 8

9 SLAVE SLAVE ADDRESS AD AD AD3 AD2 LSB MSB R2 R R RST PD Figure 7. Command Byte MSB LSB MSB LSB MSB LSB Figure 4. A Complete Serial Transmission Figure 5. All communications begin with a condition and end with a condition, both generated by a bus master. X X A/ R2, R, R: RESERVED BITS. SET TO. RST: RESET BIT, SET TO TO RESET ALL DAC REGISTERS. PD: POWER-DOWN BIT. SET TO TO PLACE THE DEVICE IN THE 4µA SHUTDOWN MODE. SET TO TO RETURN TO THE NORMAL OPERATIONAL STATE. A: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN THE NEXT BYTE. SET TO FOR MAX57. : NOWLEDGE BIT. THE MAX57/MAX58/MAX59 PULLS LOW DURING THE 9TH CLOCK PULSE. X: DON T CARE. LSB MAX57/MAX58/MAX59 SLAVE ADDRESS BITS AD, AD, AD2, AND AD3 CORRESPOND TO THE LOGIC STATE OF THE ADDRESS INPUT PINS. Figure 6. Address Byte these devices may share the bus. The MAX59 has 6 possible slave addresses. The eighth bit (LSB) in the slave address byte should be low when writing to the MAX57/MAX58/MAX59. The MAX57/MAX58/MAX59 monit the bus continuously, waiting f a condition followed by their slave address. When a device recognizes its slave address, it is ready to accept data. The Command Byte and Output Byte A command byte follows the slave address. Figure 7 shows the fmat f the command byte. A command byte is usually followed by an output byte unless it is the last byte in the transmission. If it is the last byte, all bits except PD (power-down) and RST (reset) are igned. If an output byte follows the command byte, A of the command byte indicates the digital address of the DAC whose input data latch receives the digital output data. Set this bit to when writing to the MAX57. The data is transferred to the DAC s output latch during the condition following the transmission. This allows both DACs of the MAX58/MAX59 to be updated simultaneously (Figure 8). Setting the PD bit high powers down the MAX57/ MAX58/MAX59 following a condition (Figure 9a). If a command byte with PD set high is followed by an output byte, the addressed DAC s input latch will be updated and the data will be transferred to the DAC s output latch following the condition (Figure 9b). 9

10 MAX57/MAX58/MAX59 AD3 AD2AD AD (ADDRESSING DAC) Figure 8a. Setting One DAC Output (MAX57/MAX58/MAX59) AD3 AD2AD AD (ADDRESSING DAC) (FULL SCALE) (FULL SCALE) DAC INPUT LATCH ( SET TO FULL SCALE) DAC OUTPUT CHANGES HERE: ( ) DAC GOES TO FULL SCALE. DAC INPUT LATCH ( SET TO FULL SCALE) (ADDRESSING DAC) (FULL SCALE) DAC INPUT LATCH ( SET TO FULL SCALE) DAC OUTPUTS CHANGE HERE: ( ) DAC AND DAC GO TO FULL SCALE. Figure 8b. Setting Both DAC Outputs (MAX58/MAX59) (a) (b) (PD) AD3 AD2AD AD X X X DEVICE ENTERS ( POWER-DOWN STATE) (PD) AD3 AD2 ADAD NOTE: X = DON'T CARE Figure 9. Entering the Power-Down State X X (ADDRESSING DAC) (FULL SCALE) DAC INPUT LATCH ( SET TO FULL SCALE. ) ( DEVICE ENTERS POWER-DOWN STATE. DAC OUTPUT LATCH SET TO FULL SCALE. )

11 Furtherme if the transmission s last command byte has PD high, the output latches are updated, but voltage outputs will not reflect the newly entered data because the DAC enters power-down mode when the condition is detected. When in power-down, the DAC outputs float. In this mode, the supply current is a maximum of 2µA. A command byte with the PD bit low returns the MAX57/MAX58/MAX59 to nmal operation following a condition, with the voltage outputs reflecting the output-latch contents (Figures a and b). Because each subsequent command byte overwrites the previous PD bit, only the last command byte of a transmission affects the power-down state. Setting the RST bit high clears the DAC input latches. The DAC outputs remain unchanged until a condition is detected (Figure a). If a reset is issued, the (a) (b) (PD) AD3 AD2 ADAD AD3 NOTE: X = DON'T CARE AD2AD AD following output byte is igned. Subsequent pairs of command/output bytes overwrite the input latches (Figure b). All changes made during a transmission affect the MAX57/MAX58/MAX59 s outputs only when the transmission ends and a has been recognized. The R, R, and R2 bits are reserved and must be set to zero. (PD) X X X X X (ADDRESSING DAC) I 2 C Compatibility The MAX57/MAX58/MAX59 are fully compatible with existing I 2 C systems. and are highimpedance inputs; has an open drain that pulls the data line low during the 9th clock pulse. Figure 2 shows a typical I 2 C application. DEVICE RETURNS TO ( NORMAL OPERATION) (SET TO ) DAC INPUT ( LATCH SET TO. ) DEVICE RETURNS TO NORMAL OPERATION. ( DAC SET TO. ) MAX57/MAX58/MAX59 Figure. Returning to Nmal Operation from Power-Down (a) (b) (RST) AD3 AD2 ADAD X X X ALL INPUT LATCHES ( SET TO. ) ( ALL OUTPUTS SET TO. ) (RST) AD3 AD2 ADAD NOTE: X = DON'T CARE Figure. Resetting DAC Outputs X X X "DUMMY" ALL INPUT LATCHES ( SET TO. ) X X X X X X X X DAC OUTPUTS SET TO UNLESS ( ) CHANGED BY ADDITIONAL COMMAND BYTE/ PAIRS. ADDITIONAL / PAIRS

12 MAX57/MAX58/MAX59 +5V µc AD AD AD AD E 2 PROM XICOR X24C4 DUAL DAC MAX58 OUT SINGLE DAC MAX57 OUT OUT Figure 2. MAX57/MAX58/MAX59 Used in a Typical I 2 C Application Circuit Additional Conditions It is possible to interrupt a transmission to a device with a new (repeated start) condition (perhaps addressing another device), which leaves the input latches with data that has not been transferred to the output latches (Figure 3). Only the currently addressed device will recognize a condition and transfer data to its output latches. If the device is left with data in its input latches, the data can be transferred to the output latches the next time the device is addressed, as long as it receives at least one command byte and a condition. Early Conditions The addressed device recognizes a condition at any point in a transmission. If the occurs during a command byte, all previous uninterrupted command and output byte pairs are accepted, the interrupted command byte is igned, and the transmission ends (Figure 4a). If the occurs during an output byte, all previous uninterrupted command and output byte pairs are accepted, the final command byte s PD and RST bits are accepted, the interrupted output byte is igned, and the transmission ends (Figure 4b). Analog Section DAC Operation The MAX58 and MAX59 contain two matched voltage-output DACs. The MAX57 contains a single DAC. The DACs are inverted R-2R ladder netwks that convert 8-bit digital wds into equivalent analog output voltages in proption to the applied reference voltages. The MAX58 has both DAC s reference inputs connected to VDD. Figure 5 shows a simplified diagram of one DAC. MAX57/MAX59 Reference Inputs The MAX57 and MAX59 can be used f multiplying applications. The reference accepts a V to VDD volt- (DEVICE ) (ADDRESSING DAC) ADDRESSING DAC (FULL SCALE) (FULL SCALE) DEVICE 's ( ) DAC INPUT LATCH SET TO FULL SCALE. REPEATED DEVICE 's DAC ( ) INPUT LATCH SET ( ONLY DEVICE 's DAC OUTPUT LATCH SET TO FULL TO FULL SCALE. SCALE. DEVICE 's OUTPUT LATCH UNCHANGED. ) (DEVICE ) Figure 3. Repeated Conditions 2

13 (a) (b) (RST) (PD) AD3 AD2 ADAD Table. Unipolar Code Table INTERRUPTED EARLY MAX57/MAX58/MAX59's ( ) STATE REMAINS UNCHANGED. (PD) AD3 AD2 ADAD RST X X Figure 4. Early Conditions DAC CONTENTS ANALOG OUTPUT V REF ( ) V REF ( ) 256 (POWER DOWN) 28 V REF + V REF ( ) = V REF ( ) V REF ( ) 256 V REF_* GND INTERRUPTED EARLY R R R 2R 2R 2R 2R 2R SHOWN FOR ALL s ON DAC *REF = V DD FOR THE MAX58 ( ) MAX57/MAX58/MAX59 POWER DOWN; INPUT LATCH UNCHANGED IF RST =, DAC OUTPUT(S) RESET IF RST =. D D5 D6 D7 Figure 5. DAC Simplified Circuit Diagram OUT_ MAX57/MAX58/MAX59 age, both DC and AC signals. The voltage at each REF input sets the full-scale output voltage f its respective DAC. The reference voltage must be positive. The DAC s input impedance is code dependent, with the lowest value occurring when the input code is 55 hex, and the maximum value occurring when the input code is hex. Since the REF input resistance (RIN) is code dependent, it must be driven by a circuit with low output impedance (no me than RIN 2) to maintain output linearity. The REF input capacitance is also code dependent, with the maximum value occurring at code FF hex (typically 3pF). The output voltage f any DAC can be represented by a digitally programmable voltage source as: VOUT = (N x V REF ) / 256, where N is the numerical value of the DAC s binary input code. Output Buffer Amplifiers The DAC voltage outputs are internally buffered precision unity-gain followers that slew up to V/µs. The outputs can swing from V to VDD. With a V to 4V ( 4V to V) output transition, the amplifier outputs typically settle to /2LSB in 6µs when loaded with kω in parallel with pf. The buffer amplifiers are stable with any combination of resistive loads 2kΩ and capacitive loads 3pF. The MAX57/MAX58/MAX59 are designed f unipolar-output, single-quadrant multiplication where the output voltages and the reference inputs are positive with respect to AGND. Table shows the unipolar code. 3

14 MAX57/MAX58/MAX59 OUT REF N.C. REF SYSTEM GND OUT N.C. N.C. GND Figure 6. PC Board Layout f Minimizing MAX59 Crosstalk (bottom view) Applications Infmation Power-Supply Bypassing and Ground Management Bypass V DD with a.µf capacit, located as close to VDD and GND as possible. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figure 6 shows the suggested PC board layout to minimize crosstalk. When using the MAX58 ( the MAX57/MAX59 with VDD as the reference), you may want to add a noise filter to the V DD supply (Figure 7) to the reference input(s) (Figure 8), especially in noisy environments. The reference input s bandwidth exceeds MHz f AC signals, so disturbances on the reference input can easily affect the DAC output(s). The maximum input current f a single reference input is V REF /6kΩ = I REF (max). In Figure 7, choose R F so that changes in the reference input current will have little effect on the reference voltage. F example, with R F = 6Ω, the maximum output err due to R F is given by: 6Ω x I REF (max) =.9mV.LSB In Figure 8, there is a voltage drop across R F that adds to the TUE. This voltage drop is due to the sum of the reference input current (V REF /6kΩ maximum), supply current (6mA maximum), and the amplifier output current (V REF /R LOAD ). Choose R F to limit this voltage drop to an acceptable value. F example, with a kω load, you can limit the err due to R F to.5lsb (9.8mV) by selecting R F so that: R F = V RF / I RF 9.8mV / (5V / 6kΩ + 6mA + 5V / kω) R F.4Ω Figure 7. Reference Filter When Using V DD as a Reference +5V +5V R F C F R F C F REF_ MAX57 MAX59 V DD MAX58.µF Figure 8. V DD Filter When Using V DD as a Reference V DD.µF 4

15 Pin Configurations (continued) TOP VIEW Ordering Infmation (continued) PART TEMP RANGE PIN-PAGE MAX57AEPA -4 C to +85 C 8 Plastic DIP MAX57BEPA -4 C to +85 C 8 Plastic DIP.5 MAX57BMJA -55 C to +25 C 8 CERDIP**.5 MAX58ACPA C to +7 C 8 Plastic DIP MAX58BCPA C to +7 C 8 Plastic DIP.5 MAX58ACSA C to +7 C 8 SO MAX58BCSA C to +7 C 8 SO.5 MAX58BC/D C to +7 C Dice*.5 MAX58AEPA -4 C to +85 C 8 Plastic DIP MAX58BEPA -4 C to +85 C 8 Plastic DIP.5 MAX58AESA MAX58BESA MAX58BMJA MAX59ACPE MAX59BCPE MAX59ACSE MAX59BCSE MAX59BC/D MAX59AEPE MAX59BEPE MAX59AESE MAX59BESE MAX59BMJE OUT N.C. N.C. GND AD3 N.C MAX59 DIP/SO -4 C to +85 C -4 C to +85 C -55 C to +25 C C to +7 C C to +7 C C to +7 C C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C -4 C to +85 C -4 C to +85 C -55 C to +25 C 6 OUT 5 REF 4 N.C. 3 REF 2 V DD AD AD 9 AD2 8 SO 8 SO 8 CERDIP** 6 Plastic DIP 6 Plastic DIP 6 Narrow SO 6 Narrow SO Dice* 6 Plastic DIP 6 Plastic DIP 6 Narrow SO 6 Narrow SO 6 CERDIP** TUE (LSB) MAX57AESA -4 C to +85 C 8 SO MAX57BESA -4 C to +85 C 8 SO.5 *Dice are specified at T A = +25 C, DC parameters only. **Contact facty f availability and processing to MIL-STD Chip Topography GND AD3 (MAX59) OUT OUT (MAX58/MAX59) AD2 (MAX59).78" (.98mm) TRANSISTOR COUNT: 797 SUBSTRATE CONNECTED TO VDD AD REF (MAX57/ MAX59) REF (MAX59) V DD AD.35" (3.429mm) MAX57/MAX58/MAX59 5

16 MAX57/MAX58/MAX59 Package Infmation (The package drawing(s) in this data sheet may not reflect the most current specifications. F the latest package outline infmation, go to PDIPN.EPS N INCHES DIM A A MIN.53.4 MAX.69. B.4.9 C.7. MILLIMETERS MIN MAX SOICN.EPS e.5 BSC.27 BSC E H E H L TOP VIEW VARIATIONS: DIM D D D INCHES MILLIMETERS MIN MAX MIN MAX N MS AA AB AC D A C e B A FRONT VIEW L SIDE VIEW -8 PROPRIETARY INFORMATION TITLE: PAGE OUTLINE,.5" SOIC APPROVAL DOCUMENT CONTROL NO. REV. 2-4 B Maxim cannot assume responsibility f use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA 9486 (48) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.