+5 Volt, Parallel Input Complete Dual 12-Bit DAC AD8582

Transcription

1 MIN Volts LINEARITY ERROR LSB a FEATURES Complete Dual -Bit DAC No External Components Single + Volt Operation mv/bit with.9 V Full Scale True Voltage Output, ± ma Drive Very Low Power: mw APPLICATIONS Digitally Controlled Calibration Portable Equipment Servo Controls Process Control Equipment PC Peripherals LDA CS A/B DATA LDB + Volt, Parallel Input Complete Dual -Bit DAC AD88 FUNCTIONAL BLOCK DIAGRAM AD88 DAC A REGISTER INPUT A REGISTER INPUT B REGISTER DAC B REGISTER -BIT DAC A REFERENCE -BIT DAC B V OUTA V REF V OUTB AGND DGND RST MSB GENERAL DESCRIPTION The AD88 is a complete, parallel input, dual -bit, voltage output DAC designed to operate from a single + volt supply. Built using a CBCMOS process, this monolithic DAC offers the user low cost, and ease-of-use in + volt only systems. Included on the chip, in addition to the DACs, are a rail-to-rail amplifier, latch and reference. The reference (V REF ) is trimmed to. volts output, and the on-chip amplifier gains up the DAC output to.9 volts full scale. The user needs only supply a + volt supply. The AD88 is coded natural binary. The op amp output swings from volt to +.9 volts for a one-millivolt-per-bit resolution, and is capable of driving ± ma. Operation down to. V is possible with output load currents less than ma...8 VFS LSB T A = + C The high speed parallel data interface connects to the fastest processors without wait states. The double-buffered input structure allows the user to load the input registers one at a time, then a single load strobe tied to both LDA + LDB inputs will update both DAC outputs simultaneously. LDA and LDB can also be activated independently to immediately update their respective DAC registers. An address input decodes DAC A or DAC B when the chip select CS input is strobed. An asynchronous reset input sets the output to zero scale. The MSB bit can be used to establish a preset to midscale when the reset input is strobed. The AD88 is available in the -pin plastic DIP and the surface mount SOIC-. Each part is fully specified for operation over C to +8 C, and the full + V ± % power supply range.... = +V T A = C, + C, +8 C.6. PROPER OPERATION WHEN SUPPLY VOLTAGE ABOVE CURVE OUTPUT LOAD CURRENT ma Figure. Minimum Supply Voltage vs. Load... = + C & +8 C = C 8 7 DIGITAL INPUT CODE Decimal 96 Figure. Linearity Error vs. Digital Code and Temperature REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood. MA 6-96, U.S.A. Tel: 67/9-7 Fax: 67/6-87

2 AD88 SPECIFICATIONS ELECTRICAL CHARACTERISTICS = +. V ± %, R L = No Load, C T A +8 C, unless otherwise noted) Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note Bits Relative Accuracy INL ±/ + LSB Differential Nonlinearity DNL Monotonic ±/ + LSB Zero-Scale Error V ZSE Data = H +. + mv Full-Scale Voltage V FS Data = FFF H, V Full-Scale Tempco TCV FS Notes and ±6 ppm/ C MATCHING PERFORMANCE Linearity Matching Error V FS A/B ± LSB REFERENCE OUTPUT Output Voltage V REF.8..6 V Output Source Current I REF Note ma Line Rejection LN REJ.8 %/V Load Regulation LD REG I REF = ma to ma. %/ma ANALOG OUTPUT Output Current I OUT Data = 8 H ± ma Load Regulation at Half Scale LD REG R L = Ω to, Data = 8 H LSB Capacitive Load C L No Oscillation pf DYNAMIC CHARACTERISTICS Crosstalk C T >6 db Voltage Output Settling Time t S To ± LSB of Final Value 6 µs Digital Feedthrough F T Signal Measured at DAC Output, While nv s Changing Data (LDA = LDB = ) LOGIC INPUTS Logic Input Low Voltage V IL.8 V Logic Input High Voltage V IH. V Input Leakage Current I IL µa Input Capacitance C IL Note pf TIMING SPECIFICATIONS, 6 Chip Select Pulse Width t CSW ns DAC Select Setup t AS ns DAC Select Hold t AH ns Data Setup t DS ns Data Hold t DH ns Load Setup t LS ns Load Hold t LH ns Load Pulse Width t LDW ns Reset Pulse Width t RSW ns SUPPLY CHARACTERISTICS Positive Supply Current I DD V IH =. V, V IL =.8 V 7 ma V IL = V, = + V ma Power Dissipation 7 P DISS V IH =. V, V IL =.8 V mw V IL = V, = + V mw Power Supply Sensitivity PSS = ±%.. %/% NOTES LSB = mv for V to +.9 V output range. Includes internal voltage reference error. These parameters are guaranteed by design and not subject to production testing. Very little sink current is available at the V REF pin. Use external buffer if setting up a virtual ground. Settling time is not guaranteed for the first six codes through. 6 All input control signals are specified with t R = t F = ns (% to 9% of + V) and timed from a voltage level of.6 V. 7 Power dissipation is a calculated value I DD V. Specifications subject to change without notice. REV.

3 AD88 ABSOLUTE MAXIMUM RATINGS* to DGND & AGND V, +7 V Logic Inputs to DGND V, +. V V OUT to AGND V, +. V V REF to AGND V, +. V AGND to DGND V, I OUT Short Circuit to GND ma Package Power Dissipation (T J max T A )/θ JA Thermal Resistance, θ JA -Pin Plastic DIP Package (N-) C/W -Lead SOIC Package (SOL-) C/W Maximum Junction Temperature (T J max) C Operating Temperature Range C to +8 C Storage Temperature Range C to + C Lead Temperature (Soldering, sec) C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CS A/B D D LDA, LDB RST V OUT t AS t DS t CSW t LS t AH t DH t LH t RSW t LDW t S t S ± LSB ERROR BAND Timing Diagram ORDERING INFORMATION* Temperature Package Package Model Range Description Option AD88AN C to +8 C -Pin Plastic DIP N- AD88AR C to +8 C -Lead SOIC SOL- AD88Chips + C Die *For die specifications contact your local Analog Devices sales office. The AD88 contains 7 transistors. Pin No. Name Description PIN DESCRIPTION, V OUTA Voltage outputs from the DACs. Fixed V OUTB output voltage range of V to.9 V with mv/lsb. An internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature and power supply variations. AGND Analog Ground. Ground reference for the internal bandgap reference voltage, the DAC, and the output buffer. DGND Digital ground for input logic., LDA, Load DAC register strobes. Transfers LDB input register data to the DAC registers. Active low inputs, Level sensitive latch. May be connected together to doublebuffer load DAC registers. MSB Digital Input: High presets DAC registers to half scale (8 H ), Low clears DAC registers to zero ( H ) upon RST assertion. 6 RST Active low digital input that clears the DAC register to zero, setting the DAC to minimum scale when MSB pin =, or half-scale when MSB pin =. 7 8 DB Twelve Binary Data Bit Inputs. DB is the MSB and DB is the LSB. 9 CS Chip Select. Active low input. A/B Select DAC A = or DAC B =. Positive Supply. Nominal value + V, ±%. V REF Nominal. V reference output voltage. This node must be buffered if required to drive external loads. N- -Pin Plastic DIP PIN CONFIGURATIONS V OUTA AGND V OUTB V REF DGND LDA LDB MSB RST DB 6 7 AD88 TOP VIEW (Not to Scale) 9 8 A/B CS DB DB 8 7 DB DB 9 6 DB9 DB DB8 DB DB7 DB DB6 SOL- -Pin SOIC AD88 TOP VIEW (Not to Scale) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD88 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV.

4 AD88 Table I. Control Logic Truth Table CS A/B LDA LDB RST MSB Input Register DAC Register L L H H H X Write to A Latched L H H H H X Write to B Latched L L L H H X Write to A A Transparent L H H L H X Write to B B Transparent H X L L H X Latched A & B Transparent H X ^ ^ H X Latched Latched X X X X L L Reset to Zero Scale Reset to Zero Scale X X X X L H Reset to Midscale Reset to Midscale H X X X ^ X Latch Reset Value Latch Reset Value ^Denotes positive edge triggered. OPERATION The AD88 is a complete, ready-to-use dual -bit digital-toanalog converter. Only one + V power supply is necessary for operation. It contains two voltage-switched, -bit, lasertrimmed digital-to-analog converters, a curvature-corrected bandgap reference, rail-to-rail output op amps, input registers, and DAC registers. The parallel data interface consists of twelve data bits, DB DB, an address select pin A/B, two load strobe pins (LDA, LDB) and an active low CS strobe. In addition an asynchronous RST pin will set all DAC register bits to zero causing the V OUT to become zero volts, or to midscale for trimming applications when the MSB pin is programmed to Logic. This function is useful for power on reset or system failure recovery to a known state. BANDGAP REFERENCE V REF.V BUFFER VOLTAGE SWITCHED -BIT R-R D/A CONVERTER SPDT N CH FET SWITCHES R R R R R R R R RAIL-TO-RAIL OUTPUT AMPLIFIER R AV =.9/. =.68V/V V OUT D/A CONVERTER SECTION The internal DAC is a -bit voltage-mode device with an output that swings from AGND potential to the. volt internal bandgap voltage. It uses a laser trimmed R-R ladder which is switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output (not available to the user) is internally connected to the rail-to-rail output op amp. AMPLIFIER SECTION The internal DAC s output is buffered by a low power consumption precision amplifier. This low power amplifier contains a differential PNP pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zeroscale DAC output voltages. The rail-to-rail amplifier is configured in a gain of.68 (=.9 V/. V) in order to set the.9 volt full-scale output ( mv/lsb). See Figure for an equivalent circuit schematic of the analog section. The op amp has a 6 µs typical settling time to.%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the Typical Performances section of this data sheet. Figure. Equivalent Schematic of Analog Portion OUTPUT SECTION The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull-down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the % supply tolerance value of.7 volts. P-CH N-CH V OUT AGND Figure. Equivalent Analog Output Circuit REV.

5 AD88 Figures and 6 in the typical performance characteristics section provide information on output swing performance near ground and full-scale as a function of load. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to pf capacitive load driving capability. REFERENCE SECTION The internal. V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is available at the V REF pin. Since V REF is not intended to drive external loads, it must be buffered. The equivalent emitter follower output circuit of the V REF pin is shown in Figure. Bypassing the V REF pin will improve noise performance; however, bypassing is not required for proper operation. Figure 8 shows broadband noise performance. POWER SUPPLY The very low power consumption of the AD88 is a direct result of a circuit design optimizing use of the CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors good analog accuracy is achieved. For power-consumption sensitive applications it is important to note that the internal power consumption of the AD88 is strongly dependent on the actual logic-input voltage levels present on the DB DB, CS, A/B, MSB, LDA, LDB and RST pins. Since these inputs are standard CMOS logic structures they contribute static power dissipation dependent on the actual driving logic V OH and V OL voltage levels. The graph in Figure 9 shows the effect on total AD88 supply current as a function of the actual value of input logic voltage. Consequently, for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A V INL = V on the DB pins provides the lowest standby dissipation of ma typical with a + V power supply. As with any analog system, it is recommended that the AD88 power supply be bypassed on the same PC card that contains the chip. Figure shows the power supply rejection versus frequency performance. This should be taken into account when using higher frequency switched-mode power supplies with ripple frequencies of khz and higher. One advantage of the rail-to-rail output amplifiers used in the AD88 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from +.7 V to +. V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD88 is possible down to +. volts. The minimum operating supply voltage versus load current plot, in Figure, provides information for operation below = +.7 V. TIMING AND CONTROL The input registers are level triggered and acquire data from the data bus during the time period when CS is low. The input register selected is determined by the A/B select pin, see Table I. for a complete description. When CS goes high, the data is latched into the register and held until CS returns low. The minimum time required for the data to be present on the bus before CS returns high is called the data setup time (t DS ) as seen in Timing Diagram. The data hold time (t DH ) is the amount of time that the data has to remain on the bus after CS goes high. The high speed timing offered by the AD88 provides for direct interface with no wait states in all but the fastest microprocessors. The data from the input registers is transferred to the DAC registers by the active low LDA and LDB pins. If these inputs are tied together, a single logic input can perform a double buffer update of the DAC registers, which in turn simultaneously changes the analog output voltages to a new value. If the LDA and LDB pins are wired low, they become transparent. In this mode the input register data will directly control the output voltages. Refer to the Control Logic Truth Table for a complete description. Unipolar Output Operation This is the basic mode of operation for the AD88. The AD88 has been designed to drive loads as low as 8Ω in parallel with pf. The code table for this operation is shown in Table II. Table II. Unipolar Code Table Hexadecimal Number in DAC Decimal Number Analog Output Register in DAC Register Voltage (V) FFF FF REV.

6 V OUT Volts OUTPUT OUTPUT VOLTAGE mv/div LD INPUT DATA OUTPUT NOISE VOLTAGE µv/div SUPPLY CURRENT ma POWER SUPPLY REJECTION db OUTPUT VOLTAGE Volts OUTPUT PULL-DOWN VOLTAGE mv OUTPUT CURRENT ma AD88 Typical Performance Characteristics = +V T A = + C R L TIED TO AGND = +V DATA = H 8 6 POSITIVE CURRENT LIMIT R L TIED TO +V DATA = H k k k LOAD RESISTANCE Ω.. T A = +8 C T A = + C T A = C OUTPUT SINK CURRENT µa 6 8 DATA = 8 H R L TIED TO +V NEGATIVE CURRENT LIMIT OUTPUT VOLTAGE Volts Figure. Output Swing vs. Load Figure 6. Pull-Down Voltage vs. Output Sink Current Capability Figure 7. I OUT vs. V OUT T A = + C NBW = 6kHz = +.7V = +V T A = + C 8 6 = +V ±mv AC T A = + C TIME = µs/div LOGIC VOLTAGE VALUE Volts k k k FREQUENCY Hz Figure 8. Broadband Noise Figure 9. Supply Current vs. Logic Input Voltage Figure. Power Supply Rejection vs. Frequency V LDB TO 7 = +V T A = + C µs % V µs = +V T A = + C.8 TIME ns/div TIME = µs/div TIME µs/div Figure. Midscale Transition Performance Figure. Large Signal Settling Time Figure. Output Voltage Rise Time Detail 6 REV.

7 SUPPLY CURRENT ma mv/div DATA ZERO-SCALE OUTPUT Volts OUTPUT NOISE DENSITY µv/ Hz NOMINAL FULL-SCALE VOLTAGE CHANGE mv OUTPUT VOLTAGE mv/div FREQUENCY DATA FULL-SCALE OUTPUT Volts AD88 µs = +V T A = + C TUE = ΣINL+ZS+FS SS = 97 UNITS = +.7V T A = + C = +.7V NO LOAD SS = 98 UNITS σ +σ.8.8 σ σ TIME µs/div TOTAL UNADJUSTED ERROR mv.7 7 Figure. Output Voltage Fall Time Detail Figure. Total Unadjusted Error Histogram Figure 6. Full-Scale Voltage vs. Temperature = +.7V NO LOAD SS = 98 UNITS = +V T A = + C = +V SS = UNITS σ +σ. σ σ 7. k k k FREQUENCY Hz HOURS OF OPERATION AT + C 6 Figure 7. Zero-Scale Voltage vs. Temperature Figure 8. Output Voltage Noise Density vs. Frequency Figure 9. Long-Term Drift Accelerated by Burn-In = +.V V DATA = +.V NO LOAD = +.V V 9 V µs T A = + C R L = = +V 9 V µs CS = HIGH V REF VOUT = +.7V V % % V mv 7 TIME µs/div TIME µs/div Figure. Supply Current vs. Temperature Figure. Reference Startup vs. Time Figure. Digital Feedthrough vs. Time REV. 7

8 REFERENCE ERROR mv REF LOAD REGULATION %/ma REF LINE REGULATION %/Volt AD = +.7V σ +σ σ σ 7 Figure. Reference Error vs. Temperature PIN. (.) MAX. (.). (.8) PIN. (.8). (.6) σ +σ 7 = +.7V I L = ma σ σ Figure. Reference Load Regulation vs. Temperature OUTLINE DIMENSIONS Dimensions shown in inches and (mm). N- -Pin Narrow Body Plastic DIP.7 (.). (8.6). (.) BSC SOL- -Lead Wide Body SOIC.6 (.6).98 (.).7 (.77). (.).99 (7.6).9 (7.).8 (7.). (6.).6 (.). (.8). (.8) MIN SEATING PLANE.9 (.6).97 (.). (.6).96 (.). (8.). (7.6) σ +σ σ σ = +.7 TO +.V 7 Figure. Reference Line Regulation vs. Temperature.9 (.9). (.9). (.8).8 (.).9 (.7).98 (.) x PRINTED IN U.S.A. C869 8 /9.8 (.). (.). (.7) BSC.9 (.9).8 (.) 8. (.).9 (.). (.7).7 (.) 8 REV.