10-Bit High Speed Multiplying D/A Converter (Universal Digital Logic Interface) DAC10*

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1 a FEATURES Fast Settling: 85 ns Low Full-Scale Drift: 0 ppm/ C Nonlinearity to 0.05% Max Over Temperature Range Complementary Current Outputs: 0 ma to ma Wide Range Multiplying Capability: MHz Bandwidth Wide Power Supply Range: +5, 7.5 Min to 8 V Max Direct Interface to TTL, CMOS, ECL, PMOS, NMOS Availability in Die Form GENERAL DESCRIPTION The series of 0-bit monolithic multiplying digital-toanalog converters provide high speed performance and full-scale accuracy. Advanced circuit design achieves 85 ns settling times with very low glitch energy and low power consumption. Direct interface to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic inputs. 0-Bit High Speed Multiplying D/A Converter (Universal Digital Logic Interface) * All series models guarantee full 0-bit monotonicity, and nonlinearities as tight as +0.05% over the entire operating temperature range are available. Device performance is essentially unchanged over the ±8 V power supply range, with 85 mw power consumption attainable at lower supplies. A highly stable, unique trim method is used, which selectively shorts Zener diodes, to provide / LSB full-scale accuracy without the need for laser trimming. Single-chip reliability, coupled with low cost and outstanding flexibility, make the device an ideal building block for A/D converters, Data Acquisition systems, CRT displays, programmable test equipment and other applications where low power consumption, input/output versatility and long-term stability are required. SIMPLIFIED SCHEMATIC MSB LSB V+ B B B 3 B B 5 B B 7 B 8 B 9 B BIAS NETWORK UT V REF (+) CURRENT SWITCHES REFERENCE AMPLIFIER UT V REF ( ) COMP V *Protected by Patent Nos.,055,770,,05,70 and,09,39. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 90, Norwood, MA 00-90, U.S.A. Tel: 78/ World Wide Web Site: Fax: 78/ Analog Devices, Inc., 998

2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS F G Parameter Symbol Conditions Min Typ Max Min Typ Max Units MONOTONICITY 0 0 Bits NONLINEARITY NL LSB DIFFERENTIAL NONLINEARITY DNL LSB SETTLING TIME t S All Bits Switched ON or OFF Settle to 0.05% of FS (See Note) ns OUTPUT CAPACITANCE C O 8 8 pf PROPAGATION DELAY t PLH All Bits Switched R L = 5 kω ns t PHL R L = 0 kω ns OUTPUT VOLTAGE Full-Scale Current Change V COMPLIANCE V OC < LSB V GAIN TEMPCO TCI FS (See Note) ±0 ±5 ±0 ±50 ppm/ C FULL-SCALE SYMMETRY I FSS I FR I FR µa ZERO-SCALE CURRENT I ZS µa FULL-SCALE CURRENT I FR (See Note) ma REFERENCE INPUT SLEW RATE DI/dt ma/µs REFERENCE BIAS CURRENT I B 3 3 µa POWER SUPPLY PPS/ FS +.5 V V+ 8 V % I FS /% V SENSITIVITY PPS/ FS 8 V V 0 V % I FS /% V POWER SUPPLY CURRENT I+ V S = ± 5 V; I REF = ma.3.3 ma I ma I+ V S = +5 V; 7.5 V; I REF = ma.8.8 ma I ma POWER DISSIPATION P D V S = ± 5 V; I REF = ma mw P D V S = +5 V; 7.5 V; I REF = ma mw LOGIC INPUT LEVELS V IL = V V IH = 0 V LOGIC INPUT CURRENTS I IL = 0; V IN = 0.8 V µa I IH V IN =.0 V µa ELECTRICAL CHARACTERISTICS F G Parameter Symbol Conditions Min Typ Max Min Typ Max Units MONOTONICITY 0 0 Bits NONLINEARITY NL LSB DIFFERENTIAL NONLINEARITY DNL LSB OUTPUT VOLTAGE COMPLIANCE V OC Full-Scale Current Change, < LSB 5 / /+5 +0 V FULL-SCALE CURRENT I FS V REF = V, R = R5 = kω ma FULL-SCALE SYMMETRY I FSS I FR I FR µa ZERO-SCALE CURRENT I ZS µa NOTE: Guaranteed by design. (@ V S = 5 V; I REF = ma; 0 C T A +70 C for F and G, unless otherwise noted. Output characteristics apply to both UT and UT.) (@ V S = 5 V; I REF = ma; T A = +5 C, unless otherwise noted. Output characteristics apply to both UT and UT.) REV. D

3 WAFER TEST LIMITS N Parameter Symbol Conditions Limit Units RESOLUTION 0 Bits min MONOTONICITY 0 Bits min NONLINEARITY NL ±0.5 LSB max OUTPUT VOLTAGE COMPLIANCE V OC True LSB +0 V max 5 V min OUTPUT CURRENT RANGE I FS ±3.99 ma ±8 µa max ZERO-SCALE CURRENT I ZS All Bits OFF 0.5 µa max LOGIC INPUT V IH I IN = 00 na V min LOGIC INPUT 0 V Ground 0.8 V max I IN = 00 µa POSITIVE SUPPLY CURRENT I+ V+ = 5 V ma max NEGATIVE SUPPLY CURRENT I V+ = 5 V 5 ma max NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard produce dice. TYPICAL ELECTRICAL CHARACTERISTICS (@ V S = 5 V, I REF = ma, T A = +5 C, unless otherwise noted. Output characteristics refer to both UT and UT ). (@ V S = 5 V, I REF = ma, unless otherwise noted. Output characteristics refer to both UT and UT ). F Parameter Symbol Conditions Typ Units SETTLING TIME t S To ± / LSB When Output Is Switched from 0 to FS 85 ns GAIN TEMPERATURE COEFFICIENT (TC) V REF Tempco Excluded ±0 ppm FS/ C OUTPUT CAPACITANCE 8 pf OUTPUT RESISTANCE 0 MΩ DICE CHARACTERISTICS DIE SIZE inch, 7,97 sq. mils (.3.0 mm, 5.07 sq. mm) REV. D 3

4 ABSOLUTE MAXIMUM RATINGS Operating Temperature FX, GX, GS, GP C to +70 C Junction Temperature (T J ) C to +50 C Storage Temperature C to +50 C Lead Temperature (Soldering, 0 sec) C V+ Supply to V Supply V Logic Inputs V to V plus 3 V V to V+ Analog Current Outputs V to 8 V Reference Inputs (V to V 7 ) V to V+ Reference Input Differential Voltage (V to V 7 ).... ± 8 V Reference Input Current (I ) ma Package Type JA JC Units 8-Lead Hermetic DIP (X) 8 5 C/W 8-Lead SOIC (S) 89 8 C/W 8-Lead Plastic DIP (P) 7 33 C/W NOTES Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. θ JA is specified for worst case mounting conditions, i.e., θ JA is specified for device in socket for Cerdip packages. ORDERING GUIDE INL Temperature Package Package Model (LSB) Range Description Options FX C to +70 C Cerdip Q-8 GX 0 C to +70 C Cerdip Q-8 GS 0 C to +70 C SOIC R-8 GP 0 C to +70 C Plastic DIP N-8 PIN CONNECTIONS 8-Lead Hermetic DIP 8-Lead Plastic DIP 8-Lead SOIC V (MSB) B 3 5 TOP VIEW (Not to Scale) 8 COMP 7 V REF ( ) V REF (+) 5 V+ B0 (LSB) B B3 B B B9 B8 B7 B REV. D

5 Typical Performance Characteristics 0mA.0mA.0mA I REF = ma UT UT ( ) () Figure. True and Complementary Output Operations OUTPUT CURRENT ma T A = T MIN TO T MAX ALL BITS ON V = 5V, V = 0V I REF = ma I REF = ma I REF = 0.mA OUTPUT VOLTAGE Volts Figure. Output Current vs. Output Voltage (Output Voltage Compliance) OUTPUT VOLTAGE Volts SHADED AREA INDICATES PERMISSABLUTPUT VOLTAGE RANGE FOR V = 5V I REF.0mA FOR OTHER V OR I REF SEUTPUT CURRENT vs. OUTPUT VOLTAGE CURVE TEMPERATURE C Figure 3. Output Voltage Compliance vs. Temperature POWER SUPPLY CURRENT ma ALL BITS "HIGH" OR "LOW" V+, POSITIVE POWER SUPPLY V DC Figure. Power Supply Current vs. V+ I I+ POWER SUPPLY CURRENT ma BITS MAY BE HIGH OR LOW I WITH I REF = ma I WITH I REF = ma I WITH I REF = 0.mA I WITH I REF = 0.mA V, NEGATIVE POWER SUPPLY V DC Figure 5. Power Supply Current vs. V POWER SUPPLY CURRENT ma V = 5V I REF =.0mA ALL BITS MAY BE "HIGH" OR "LOW" V+ = +5V I TEMPERATURE C Figure. Power Supply Current vs. Temperature I BASIC CONNECTIONS +V REF I FR = +V REF 03 R REF 0 + = I FR FOR ALL MSB LSB LOGIC STATES B B B 3 B B 5 B B 7 B 8 B 9 B 0 R REF V REF (R) I REF R F 3 8 C C V COMP 0.0 F V+ FOR FIXED REFERENCE, TTL OPERATION, TYPICAL VALUES ARE: V REF = V R REF = 5.000k R5 = R REF C C = 0.0 F = 0V (GROUND) Figure 7. Basic Positive Reference Operation V IN R REF R7 +V REF V IN I IN R IN R REF R REF R7 (OPTIONAL) I REF I REF 7 7 PEAK NEGATIVE SWING OF I IN HIGH INPUT IMPEDANCE +V REF MUST BE ABOVE PEAK POSITIVE SWING OF V IN Figure 8. Accommodating Bipolar References CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 000 V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! ESD SENSITIVE DEVICE REV. D 5

6 V REF I FS R REF R7 V REF R REF 7 NOTE: R REF SETS I FS ; R7 IS FOR BIAS CURRENT CANCELLATION V REF +0V 0k POT LOW T.C..5k 39k I REF (+) ma V 7 APPROXIMATELY 5k Figure 9. Basic Negative Reference Operation Figure 0. Recommended Full-Scale Adjustment Circuit MSB LSB B B B 3 B B 5 B B 7 B 8 B 9 B 0 ma ma B B B 3 B B 5 B B 7 B 8 B 9 B 0 FULL RANGE I REF =.000mA.5k.5k HALF-SCALE +LSB HALF-SCALE HALF-SCALE LSB HALF-SCALE +LSB ZERO SCALE +LSB Figure. Basic Unipolar Negative Operation MSB LSB +5V POSITIVE FULL RANGE B B B 3 B B 5 B B 7 B 8 B 9 B I REF (+) =.000mA B B B 3 B B 5 B B 7 B 8 B 9 B 0 E O.5k.5k POSITIVE FULL RANGE LSB ZERO-SCALE +LSB ZERO-SCALE ZERO-SCALE LSB NEGATIVE FULL-SCALE +LSB NEGATIVE FULL-SCALE Figure. Basic Bipolar Output Operation +5V 5k MSB LSB B B B 3 B B 5 B B 7 B 8 B 9 B 0.5k V IN V O REF0 GND k 5k C C +5V 5V POSITIVE FULL RANGE ZERO-SCALE NEGATIVE FULL-SCALE +LSB NEGATIVE FULL-SCALE B B B 3 B B 5 B B 7 B 8 B 9 B V+ V Figure 3. Offset Binary Operation REV. D

7 LOW-TO-HIGH SETTLING V L =.500V 0.00V HIGH-TO-LOW SETTLING V L = 0.500V 0.00V V L 0.500V 0.00V +5V 5 5 k 0. F 0 F IN57 0. F 0 F 0.0 F.7 F D.U.T. N F +5V F.5k 5V +5V.5k 0.0 F REF-0 5 0k N98 5V M /W, 5% CARBON k.7 F 5V 0.0 F F k NOTES:. CASF N98s MUST BE GROUNDED.. RESISTORS ARE /W MF, % UNLESS OTHERWISE SPECIFIED. 3. USE FET PROBE (7A SCOPE PLUGIN). 5V V O 99k /W, 5% CARBON / LSB SETTLING = 7.8mV 75mV Figure. Settling Time Measurement R L TTL V TH = +.V +5V 9.k V TH = +.V +5V CMOS V TH = +7.V E P0 O O 0 TO +I FR R L I FR = 03 0 I REF FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO (PIN ); CONNECT (PIN ) TO GROUND. ECL.k 0. F Figure 5. Positive Low Impedance Output Operation 3k "A" N390 3k N390 R L OP5 0 TO I FR R L I FR = 03 0 I REF 39k TO PIN.k FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT NOINVERTING INPUT OF OP AMP TO PIN ); CONNECT (PIN ) TO GROUND. 5.V Figure. Negative Low Impedance Output Operation Figure 7. Interfacing with Various Logic Families REV. D 7

8 APPLICATIONS 0V R IN +V REF R P R REF TYPICAL VALUES: R IN = k +V IN = V R EQ = + + R IN R P R REF OPTIONAL RESISTOR FOR OFFSET INPUTS R EQ = NO CAP Figure 8. Pulsed Reference Operation Reference Amplifier Setup The is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to ma. The full-scale output current is a linear function of the reference current and is given by: I FR = 03 0 I REF where I REF equals current flowing into Pin. In positive reference applications, an external positive reference voltage forces current through R into the V REF (+) terminal (Pin ) of the reference amplifier. Alternatively, a negative reference may be applied to V REF ( ) at Pin 7; reference current flows from ground through R into V(+) as in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at Pin 7. R7 (nominally equal to R) is used to cancel bias current errors; R7 may be eliminated with only a minor increase in error. Bipolar references may be accommodated by offsetting V REF or Pin 7. The negative common-mode range of the reference amplifier is given by: V CM = V plus (I REF kω) plus V. The positive common-mode range is V+ less.8 V. When a dc reference is used, a reference bypass capacitor is recommended. A 5 V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R should be split into two resistors with the junction bypassed to ground with a 0. µf capacitor. For most applications, the tight relationship between I REF and I FS will eliminate the need for trimming I REF. If required, fullscale trimming may be accomplished by adjusting the value of R, or by using a potentiometer for R. An improved method of full-scale trimming that eliminates potentiometer TC effect is shown in the Recommended Full-Scale Adjustment circuit. The reference amplifier must be compensated by using a capacitor from Pin 8 to V. For fixed reference operation, a 0.0 µf capacitor is recommended. For variable reference applications, see section entitled Reference Amplifier Compensation for Multiplying Applications. R L R L Multiplying Operation The provides excellent multiplying performance with an extremely linear relationship between I FS and I REF over a range of ma to µa. Monotonic operation is maintained over a typical range of I REF from 00 µa to ma. Reference Amplifier Compensation for Multiplying Applications AC reference applications will require the reference amplifier to be compensated using a capacitor from Pin 8 to V. The value of this capacitor depends on the impedance presented to Pin for R values of.0 kω,.5 kω and 5.0 kω, minimum values of C C are 5 pf, 37 pf and 75 pf. Larger values of R require proportionately increased values of C C for proper phase margin. For fastest response to a pulse, low values of R enabling small C C values should be used. If Pin is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated, which will decrease overall bandwidth and slew rate. For R = kω and C C = 5 pf, the reference amplifier slews at ma/µs enabling a transition from I REF = 0 to I REF = ma in 500 ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (I REF = 0) condition. Full-scale transition (0 ma to ma) occurs in 0 ns when the equivalent impedance at Pin is 00 Ω and C C = 0. This yields a reference slew rate of ma/ µs, which is relatively independent of R IN and V IN values. LOGIC INPUTS The design incorporates a unique logic input circuit that enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, µa logic input current and completely adjustable logic threshold voltage. For V = 5 V, the logic inputs may swing between 5 and +8 V. This enables direct interface with +5 V CMOS logic, even when the is powered from a +5 V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V plus (l REF kω) plus 3 V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control Pin (Pin, ). The appropriate graph shows the relationship between and V TH over the temperature range, with V TH nominally. V above. For TTL interface, simply ground Pin. When interfacing ECL, an I REF = ma is recommended. For interfacing other logic families, see Figure 7. For general setup of the logic control circuit, it should be noted that Pin will sink. ma typical; external circuitry should be designed to accommodate this current. Fastest settling times are obtained when Pin sees a low impedance. If Pin is connected to a kω divider, for example, it should be bypassed to ground by a 0.0 µf capacitor. 8 REV. D

9 ANALOG OUTPUT CURRENTS Both true and complemented output sink currents are provided where + = I FS. Current appears at the true output when a is applied to each logic input. As the binary count increases, the sink current at Pin increases proportionally, in the fashion of a positive logic D/A converter. When a 0 is applied to any input bit, that current is turned off at Pin and turned on at Pin. A decreasing logic count increases as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required, it must still be connected to ground or to a point capable of sourcing I FS. DO NOT LEAVE AN UNUSED OUTPUT PIN OPEN. Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive compliance is 3 V above V and is independent of the positive supply. Negative compliance is +0 V above V. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers. POWER SUPPLIES The operates over a wide range of power supply voltages from a total supply of 9 V to 3 V. When operating with V supplies of 0 V or less, I REF ma is recommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range and negative logic threshold range; consult the various figures for guidance. For example, operation at 9 V with I REF = ma is not recommended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible, however at least 8 V total must be applied to ensure turn-on of the internal bias network. Symmetrical supplies are not required, as the is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required; however, an artificial ground may be used to ensure that logic swings, etc., remain within acceptable limits. TEMPERATURE PERFORMANCE The nonlinearity and monotonicity specifications of the are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is tight, typically +0 ppm/ C, with zero-scale output current and drift essentially negligible compared to / LSB. The temperature coefficient of the reference resistor, R, should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the decrease approximately 0% at 55 C; an increase of about 5% is typical at +5 C. SETTLING TIME The is capable of extremely fast settling times; typically 85 ns at I REF = ma. Judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. The logic switch design enables propagation delays of only 35 ns for each of the 0 bits. Settling time to within / LSB of the LSB is therefore 35 ns, with each progressively larger bit taking successively longer. The MSB settles in 85 ns, thus determining the overall settling time of 30 ns. Settling to 8-bit accuracy requires about 0 ns to 78 ns. The output capacitance of the, including the package, is approximately 8 pf; therefore, the output RC time constant dominates settling time if R L > 500 Ω. Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for I REF values down to ma, with gradual increases for lower I REF values. The principal advantage of higher I REF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve ± µa; therefore, a kω load is needed to provide adequate drive for most oscilloscopes. The settling time fixture of schematic titled Settling Time Measurement uses a cascode design to permit driving a kω load with less than 5 pf of parasitic capacitance at the measurement node. At I REF values of less than ma, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 0 to provides an accurate indicator of settling time. This code change does not require the normal. time constants to settle to within ±0.% of the final value, and thus settling times may be observed at lower values of I REF. switching transients or glitches are very low and may be further reduced by small capacitive loads at the output with a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference and terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0. µf capacitors at the supply pins provide full transient protection. REV. D 9

10 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Cerdip (Q-8) (0.3) MIN (.9) MAX (5.08) MAX 0.00 (5.08) 0.5 (3.8) 0.03 (0.58) 0.0 (0.3) 0 9 PIN 0.90 (.38) MAX 0.00 (.5) BSC (.78) (0.7) 0.30 (7.87) 0.0 (5.59) 0.00 (.5) 0.05 (0.38) 0.50 (3.8) MIN SEATING PLANE (8.3) 0.90 (7.37) 0.05 (0.38) (0.0) C33 0 5/98 8-Lead Plastic DIP (N-8) 0.95 (3.9) 0.85 (.7) (.0) 0.5 (.93) 0.0 (0.558) 0.0 (0.35) (7.) 0.0 (.0) PIN 0.00 (.5) (0.38) (5.33) MAX (.5) BSC (.77) 0.05 (.5) (3.30) MIN SEATING PLANE 0.35 (8.5) (7.) 0.95 (.95) 0.5 (.93) 0.05 (0.38) (0.0) 8-Lead Wide Body SOL (R-8) 0.5 (.75) 0.9 (.35) (7.0) 0.9 (7.0) 0.93 (0.5) (0.00) 9 PIN 0.08 (0.30) (0.0) (.7) BSC 0.03 (.5) 0.09 (.35) 0.09 (0.9) (0.35) SEATING PLANE 0.05 (0.3) (0.3) (0.7) (0.5) x (.7) (0.0) PRINTED IN U.S.A. 0 REV. D

8-Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface) DAC08

8-Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface) DAC08 a FEATURES Fast Settling Output Current: ns Full-Scale Current Prematched to LSB Direct Interface to TTL, CMOS, ECL, HTL, PMOS Nonlinearity to.% Maximum over Temperature Range High Output Impedance and