+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/ C Internal Reference

Transcription

1 9-446; Rev 2; 5/6 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference General Description The / low-power, 2-bit, voltage-output, digital-to-analog converters (DACs) feature an internal precision bandgap reference and output amplifier. The operates on a single +5 supply with an internal +2.5 reference, and offers a configurable output amplifier. If necessary, the user can override the on-chip, <ppm/ C voltage reference with an external reference. The has the same features as the but operates from a single +3 supply and has an internal +.25 precision reference. The user-accessible inverting input and output of the amplifier allows specific gain configuratio, remote seing, and high output drive capability for a wide range of force/see applicatio. Both devices draw only 5µA of supply current, which reduces to 3µA in power-down mode. In addition, their power-up reset feature allows for a user-selectable initial output state of either or midscale and reduces output glitches during power-up. The serial interface is compatible with SPI, QSPI, and MICROWIRE, which makes the / suitable for cascading multiple devices. Each DAC has a double-buffered input organized as an input register followed by a DAC register. A 6-bit shift register loads data into the input register. The DAC register may be updated independently or simultaneously with the input register. Both devices are available in a 6-pin QSOP package and are specified for the extended-industrial (-4 C to +85 C) operating temperature range. For pin-compatible 4-bit upgrades, see the MAX57/MAX573 data sheet; for the pin-compatible 3-bit version, see the MAX532/ MAX533 data sheet. Industrial Process Control Applicatio Features Single-Supply Operation +5 () +3 () Built-In ppm/ C max Precision Bandgap Reference +2.5 () +.25 () SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial Interface Pin-Programmable Shutdown Mode and Power- Up Reset ( or Midscale Output oltage) Buffered Output Capable of Driving 5kΩ pf or 4 2mA Loads Space-Saving 6-Pin QSOP Package Pin-Compatible 3-Bit Upgrades Available (MAX532/MAX533) Pin-Compatible 4-Bit Upgrades Available (MAX57/MAX573) PART AEEE BEEE AEEE Ordering Information PIN- PACKAGE 6 QSOP 6 QSOP INL (LSB) ±.5 ± 6 QSOP ± PKG CODE E6-5 E6-5 E6-5 BEEE 6 QSOP ±2 E6-5 Note: All devices are specified over the -4 C to +85 C operating temperature range. Pin Configuration / Automatic Test Equipment TOP IEW Digital Offset and Gain Adjustment FB 6 DD Motion Control Microprocessor-Controlled Systems RSTAL PDL CLR REFADJ REF AGND PD 6 UPO 7 D 8 9 DGND SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. QSOP Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / ABSOLUTE MAXIMUM RATINGS DD to AGND, DGND to +6 AGND to DGND to +.3 Digital Inputs to DGND to +6 Digital Outputs (D, UPO) to DGND to ( DD +.3) FB, to AGND to ( DD +.3) REF, REFADJ to AGND to ( DD +.3) Maximum Current into Any Pin...5mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI (+5) Continuous Power Dissipation (T A = +7 C) QSOP (derate 8.mW/ C above +7 C)...667mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C ( DD = +5 ±%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R L = 5kΩ, C L = pf, output amplifier configured in unity-gain, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note ) Differential Nonlinearity Offset Error (Note 2) Gain Error Full-Scale Temperature Coefficient (Note 3) Power-Supply Rejection Ratio REFERENCE Output oltage Output oltage Temperature Coefficient Reference External Load Regulation Reference Short-Circuit Current REFADJ Current DIGITAL INPUT Input High oltage Input Low oltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL PUTS Output High oltage Output Low oltage SYMBOL N 2 INL A B - DNL - OS - GE TC FS A 3 B 3 PSRR 4.5 DD REF T A = +25 C A 3 TC REF ppm/ C B /I I µa (sourcing). µ/µa IH IL HYS I IN C IN OH OL REFADJ = DD IN = or DD I SOURCE = 2mA I SINK = 2mA CONDITIONS MIN TYP MAX DD UNITS Bits LSB LSB m m ppm/ C µ/ ma µa m µa pf 2

3 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference ELECTRICAL CHARACTERISTI (+5) (continued) ( DD = +5 ±%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R L = 5kΩ, C L = pf, output amplifier configured in unity-gain, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE oltage Output Slew Rate SR.6 /µs Output Settling Time To ±.5LSB, STEP = µs Output oltage Swing (Note 4) to DD Current into FB -.. µa Time Required to Exit Shutdown 2 ms Digital Feedthrough POWER REQUIREMENTS Power-Supply oltage (Note 5) Power-Supply Current (Note 5) Power-Supply Current in Shutdown DD I DD I SHDN = DD, f = khz, = 5p-p n-sec µa µa / ELECTRICAL CHARACTERISTI (+3) ( DD = +3 ±%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R L = 5kΩ, C L = pf, output amplifier connected in unity-gain, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 2 Bits Integral Nonlinearity (Note ) INL A - B -2 2 LSB Differential Nonlinearity DNL - LSB Offset Error (Note 2) OS - m Gain Error GE m Full-Scale Temperature A 3 TC FS Coefficient (Note 3) B 3 ppm/ C Power-Supply Rejection Ratio PSRR 2.7 DD µ/ REFERENCE Output oltage REF T A = +25 C Output oltage Temperature Coefficient Reference External Load Regulation Reference Short-Circuit Current REFADJ Current DIGITAL INPUT Input High oltage Input Low oltage Input Hysteresis TC REF /I IH IL HYS A B I µa (sourcing) REFADJ = DD ppm/ C µ/µa ma µa m 3

4 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / ELECTRICAL CHARACTERISTI (+3) (continued) ( DD = +3 ±%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R L = 5kΩ, C L = pf, output amplifier connected in unity-gain, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage Current I IN IN = or DD -. µa Input Capacitance C IN 8 pf DIGITAL PUTS Output High oltage OH I SOURCE = 2mA DD -.5 Output Low oltage OL I SINK = 2mA.3.4 DYNAMIC PERFORMANCE oltage Output Slew Rate SR.6 /µs Output Settling Time To ±.5LSB, STEP =.25 2 µs Output oltage Swing (Note 4) to DD Current into FB -.. µa Time Required to Exit Shutdown 2 ms Digital Feedthrough POWER REQUIREMENTS Power-Supply oltage (Note 5) Power-Supply Current (Note 5) Power-Supply Current in Shutdown DD I DD I SHDN = DD, f = khz, = 3p-p n-sec µa µa TIMING CHARACTERISTI (+5) ( DD = +5 ±%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R L = 5kΩ, C L = pf, output amplifier connected in unity-gain, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Period t CP Pulse Width High t CH 4 Pulse Width Low t CL 4 Fall to Rise Setup Time t S 4 Rise to Rise Hold Time SDI Setup Time SDI Hold Time Rise to D alid Propagation Delay Time t H t DS t DH t DO C LOAD = 2pF 4 8 Fall to D alid Propagation Delay Time t DO2 C LOAD = 2pF 8 Rise to Fall Delay Time t Rise to Rise Hold Time t 4 Pulse Width High t W 4

5 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference TIMING CHARACTERISTI (+3) ( DD = +3 ±%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R L = 5kΩ, C L = pf, output amplifier connected in unity-gain, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER Clock Period Pulse Width High Pulse Width Low Fall to Rise Setup Time Rise to Rise Hold Time SDI Setup Time SDI Hold Time Rise to D alid Propagation Delay Time Fall to D alid Propagation Delay Time Rise to Fall Delay Time Rise to Rise Hold Time Pulse Width High SYMBOL t CP t CH t CL t S t H t DS t DH t DO t DO2 t t t W C LOAD = 2pF C LOAD = 2pF CONDITIONS MIN TYP MAX UNITS / Note : Accuracy is guaranteed by the following table: DD () 5 3 Accuracy Guaranteed From Code: 6 33 To Code: Note 2: Offset is measured at the code closest to m. Note 3: The temperature coefficient is determined by the box method, in which the maximum over the temperature range is divided by T and the typical reference voltage. Note 4: Accuracy is better than.lsb for = m to ( DD - 8m). Guaranteed by PSR test on end points. Note 5: R LOAD = and digital inputs are at either DD or DGND. 5

6 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / Typical Operating Characteristics ( DD = +5, R L = 5kΩ, C L = pf, output amplifier in unity-gain configuration, T A = +25 C, unless otherwise noted.) INL (LSB) INTEGRAL NONLINEARITY vs., 2, 3, 4, 5, /23 toc DNL (LSB) DIFFERENTIAL NONLINEARITY vs. -.2, 2, 3, 4, 5, /23 toc2 REFERENCE OLTAGE () REFERENCE OLTAGE vs. TEMPERATURE TEMPERATURE ( C) /23 toc3 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. TEMPERATURE (CODE = AAA HEX) (CODE = HEX) /23 toc4 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. SUPPLY OLTAGE (CODE = AAA HEX) (CODE = HEX) /23 toc5 SHUTDOWN CURRENT (µa) SHUTDOWN CURRENT vs. TEMPERATURE /23 toc6 FULL-SCALE PUT () TEMPERATURE ( C) FULL-SCALE PUT OLTAGE vs. TEMPERATURE R L = 5kΩ C L = pf /23 toc7 FULL-SCALE PUT ERROR (LSB) SUPPLY OLTAGE () FULL-SCALE PUT ERROR vs. RESISTIE LOAD /23 toc TEMPERATURE ( C) DYNAMIC RESPONSE RISE TIME /23-9 5/div /div TEMPERATURE ( C) -2.. R L (kω) 2µs/div 6

7 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference Typical Operating Characteristics (continued) ( DD = +5, R L = 5kΩ, C L = pf, output amplifier in unity-gain configuration, T A = +25 C, unless otherwise noted.) DYNAMIC RESPONSE FALL TIME /23-2µ/div 5/div /div DIGITAL FEEDTHROUGH (, ) 2µs/div /23-2/div m/div AC COUPLED MAJOR CARRY TRANSITION 5µs/div /23-2 2/div m/div AC COUPLED / INL (LSB) INTEGRAL NONLINEARITY vs. /23 toc3 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. /23 toc4 REFERENCE OLTAGE () REFERENCE OLTAGE vs. TEMPERATURE /23 toc , 2, 3, 4, 5, -.25, 2, 3, 4, 5, TEMPERATURE ( C) SUPPLY CURRENT (µa) SUPPLY CURRENT vs. TEMPERATURE (CODE = AAA HEX) (CODE = HEX) /23 toc6 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. SUPPLY OLTAGE (CODE = AAA HEX) (CODE = HEX) /23 toc7 SHUTDOWN CURRENT (µa) SHUTDOWN CURRENT vs. TEMPERATURE /23 toc TEMPERATURE ( C) SUPPLY OLTAGE () TEMPERATURE ( C) 7

8 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / Typical Operating Characteristics (continued) ( DD = +5, R L = 5kΩ, C L = pf, output amplifier in unity-gain configuration, T A = +25 C, unless otherwise noted.) FULL-SCALE PUT () FULL-SCALE PUT OLTAGE vs. TEMPERATURE TEMPERATURE ( C) /23 toc9 FULL-SCALE PUT ERROR (LSB) FULL-SCALE PUT ERROR vs. RESISTIE LOAD -4.. R L (kω) /23 toc2 DYNAMIC-RESPONSE RISE TIME µs/div /23-2 2/div 4m/div DYNAMIC-RESPONSE FALL TIME /23-22 DIGITAL FEEDTHROUGH (, ) /23-23 MAJOR CARRY TRANSITION / /div 2/div 2/div 4m/div 5µ/div AC COUPLED m/div AC COUPLED µs/div 2µs/div 5µ/div 8

9 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference PIN NAME FB RSTAL PDL CLR Amplifier Inverting See Input (Analog Input) Analog Output oltage. High impedance if part is in shutdown. Reset alue Input (Digital Input). : Connect to DD to select midscale as the output reset value. : Connect to DGND to select as the output reset value. Power-Down Lockout (Digital Input). : Normal operation. : Disallows shutdown (device cannot be powered down). Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTAL) output state. Clearing the DAC will cause it to exit a software shutdown state. Active-Low Chip-Select Input (Digital Input) FUNCTION Serial Data Input. Data is clocked in on the rising edge of. Pin Description / 8 Serial Clock Input 9 DGND Digital Ground D Serial Data Output UPO User-Programmable Output (Digital Output) 2 PD Power-Down Input (Digital Input). Pulling PD high when PDL = DD places the IC into shutdown with a maximum shutdown current of 2µA. 3 AGND Analog Ground 4 REF Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5 () or +.25 () nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to DD and applying the external reference to REF. 5 REFADJ Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to DD when using an external reference. 6 DD Positive Power Supply. Bypass with a.µf capacitor in parallel with a 4.7µF capacitor to AGND. 9

10 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / PDL PD RSTAL CLR SR CONTROL 2 DD 6-BIT SHIFT REGISTER INPUT REGISTER AGND DGND DECODE CONTROL DAC REGISTER DAC LOGIC PUT D UPO FB BANDGAP REFERENCE.25 4k 2X (X) 2.5 (.25) REFERENCE BUFFER ( ) ARE FOR ONLY. REFADJ REF Figure. Simplified Functional Diagram Detailed Description The / 2-bit, force/see DACs are easily configured with a 3-wire serial interface. They include a 6-bit data-in/data-out shift register and have a double-buffered digital input coisting of an input register and a DAC register. In addition, these devices employ precision bandgap references, as well as an output amplifier with accessible feedback and output pi that can be used to set the gain externally (Figure ) or for forcing and seing applicatio. These DACs are designed with an inverted R-2R ladder network (Figure 2) that produces a weighted voltage proportional to the digital input code. Internal Reference Both devices use an on-board precision bandgap reference with a low temperature coefficient of only ppm/ C (max) to generate an output voltage of +2.5 () or +.25 (). The REF pin can source up to µa and may become utable with capacitive loads exceeding pf. REFADJ can be used for minor adjustments to the reference voltage. REF* AGND NOTE: SHOWN FOR ALL s ON DAC. R R R 2R 2R 2R 2R 2R D D9 D D FB *INTERNAL REFERENCE: +2.5 (), +.25 (); OR EXTERNAL REFERENCE Figure 2. Simplified Inverted R-2R DAC Structure

11 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference The circuit in Figure 3 achieves a nominal reference adjustment range of ±%. Connect a 33nF capacitor from REFADJ to AGND to establish low-noise DAC operation. Larger capacitor values may be used, but will result in increased start-up delay. The time cotant (τ) for the start-up delay is determined by the REFADJ input impedance of 4kΩ and CREFADJ: τ = 4kΩ CREFADJ External Reference An external reference may be applied to the REF pin. Disable the internal reference by pulling REFADJ to DD. This allows an external reference signal (AC- or DC-based) to be fed into the REF pin. For proper operation, do not exceed the input voltage range limits of to (DD -.4) for REF. Determine the output voltage using the following equation (REFADJ = DD): = REF [(NB / 496) G] where NB is the numeric value of the / input code ( to 495), REF is the external reference voltage, and G is the gain of the output amplifier, set by an external resistor-divider. The REF pin has a minimum input resistance of 4kΩ and is code-dependent. Output Amplifier The / s DAC output is internally buffered by a precision amplifier with a typical slew rate of.6/µs. Access to the output amplifier s inverting input (FB) provides the user greater flexibility with amplifier gain setting and signal conditioning (see Applicatio Information). The output amplifier typically settles to ±.5LSB from a full-scale traition within 2µs when it is connected in unity gain and loaded with 5kΩ pf. Loads less than kω may result in degraded performance. Power-Down Mode These devices feature software- and hardware-programmable (PD pin) shutdown modes that reduce the typical supply current to 3µA. To enter software shutdown mode, program the control sequence for the DAC as shown in Table. In shutdown mode, the amplifier output becomes highimpedance and the serial interface remai active. Data in the input registers is saved, allowing the / to recall the output state prior to entering shutdown when returning to normal operation. To exit shutdown mode, load both input and DAC registers simultaneously or update the DAC register from the input register. When returning from shutdown to normal operation, wait 2ms for the reference to settle. When using an external reference, the DAC requires only 2µs for the output to stabilize. / k 5k k 4k REFADJ k 4k REFADJ 33nF 33nF Figure 3a. Reference Adjust Circuit Figure 3b. Reference Adjust Circuit

12 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / Table. Serial-Interface Programming Commands C2 C 2-Bit DAC Data XXXXXXXXXXXX Power-Down Lockout Input (PDL) The power-down lockout pin (PDL) disables shutdown when low. When in shutdown mode, a high-to-low traition on PDL will wake up the DAC with its output still set to the state prior to power-down. PDL can also be used to wake up the device asynchronously. Load input register; DAC register unchanged. 2-Bit DAC Data Simultaneously load input and DAC registers; exit shutdown. X = Don t care 6-BIT SERIAL WORD C D... D XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXX No operation. Update DAC register from input register; exit shutdown. UPO goes low (default). XXXXXXXXXXXX UPO goes high. XXXXXXXXXX * S is a sub-bit and always zero. S* S* FUNCTION Shutdown DAC (provided PDL = ). Mode ; D clocked out on s rising edge. Mode ; D clocked out on s falling edge (default). DD SS Power-Down Input (PD) Pulling PD high places the / in shutdown. Pulling PD low will not return the / to normal operation. A high-to-low traition on PDL or appropriate commands (Table ) via the serial interface are required to exit power-down mode. Serial-Interface Configuration (SPI/QSPI/MICROWIRE/PIC6/PIC7) The / 3-wire serial interface is compatible with SPI, QSPI, PIC6/PIC7 (Figure 4) and MICROWIRE (Figure 5) interface standards. The 2- byte-long serial input word contai three control bits, 2 data bits in MSB-first format, and one sub-bit, which is always zero (Table 2). The / s digital inputs are double buffered, which allows the user to: Load the input register without updating the DAC register, Update the DAC register with data from the input register, Update the input and DAC registers concurrently. ( ) ARE FOR PIC6/PIC7 ONLY. MOSI SCK I/O SPI/QSPI PORT (PIC6/PIC7) CPOL =, CPHA = (CKE =, CKP =, SMP= SSPM3 - SSPM = ) Figure 4. SPI/QSPI Interface Connectio (PIC6/PIC7) SK SO I/O MICROWIRE PORT Figure 5. MICROWIRE Interface Connectio 2

13 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference The 6-bit input word may be sent in two -byte packets (SPI-, MICROWIRE-, and PIC6/PIC7-compatible), with low during this period. The control bits C2, C, and C (table ) determine: The clock edge on which D traitio, The state of the user-programmable logic output, The configuration of the device after shutdown. The general timing diagram in Figure 6 illustrates how data is acquired. must be low for the part to receive data. With low, data at is clocked into the register on the rising edge of. When traitio high, data is latched into the input and/or DAC registers, depending on the setting of the three control bits C2, C, and C. The maximum serial clock frequency guaranteed for proper operation is MHz for the Table 2. Serial Data Format MSB... LSB 6 BITS OF SERIAL DATA Control Bits MSB...Data Bits LSB Sub-Bit C2, C, C D......D S and 6.6MHz for the. Figure 7 depicts a more detailed timing diagram of the serial interface. PIC6 with SSP Module and PIC7 Interface The / are compatible with a PIC6/PIC7 microcontroller (µc), using the synchronous serial port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 4 and configure the PIC6/PIC7 as system master by initializing its synchronous serial port control register (SSP- CON) and synchronous serial port status register (SSPSTAT) to the bit patter shown in Tables 3 and 4. In SPI mode, the PIC6/PIC7 µcs allow eight bits of data to be synchronously tramitted and received simultaneously. Two coecutive 8-bit writings (Figure 6) are necessary to feed the DAC with three control bits, 2 data bits, and one sub-bit. data traitio on the serial clock s falling edge and is clocked into the DAC on s rising edge. The first eight bits of contain the three control bits (C2, C, C) and the first five data bits (D D7). The second 8-bit data stream contai the remaining bits (D6 D), and the sub-bit S. / COMMAND EXECUTED C2 C C D D D9 D8 D7 D6 D5 D4 D3 D2 D D S Figure 6. Serial-Interface Timing t W t t S t H t t CH t CL t CP t DS tdo t DO2 t DH D Figure 7. Detailed Serial-Interface Timing 3

14 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / Table 3. Detailed SSPCON Register Contents WCOL SSPO SSPEN CKP SSPM3 SSPM2 SSPM SSPM X = Don t care CONTROL BIT BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT BIT / SETTINGS X X SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detect Bit Synchronous Serial Port Enable Bit. : Disables serial port and configures these pi as I/O port pi. : Enables serial port and configures SCK, SDO and SCI as serialport pi. Clock Polarity Select Bit. CKP = for SPI master-mode selection. Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects f CLK = f OSC / 6 Table 4. Detailed SSPSTAT Register Contents CONTROL BIT SMP BIT7 CKE BIT6 D/A BIT5 P BIT4 S BIT3 R/W BIT2 UA BIT BF BIT X = Don t care / SETTINGS X X X X X X SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge Select Bit. Data will be tramitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit Serial Data Output The contents of the internal shift-register are output serially on D which allows for daisy-chaining of multiple devices (see Applicatio Information) as well as data readback. The / may be programmed to shift data out of D on the serial clock s rising edge (Mode ) or on the falling edge (Mode ). The latter is the default during power-up and provides a lag of 6 clock cycles, maintaining SPI, QSPI, MICROWIRE, and PIC6/PIC7 compatibility. In Mode, the output data lags by 5.5 clock cycles. During power-down, D retai its last digital state prior to shutdown. User-Programmable Output (UPO) The UPO feature allows an external device to be controlled through the serial-interface setup (Table ) thereby reducing the number of microcontroller I/O ports required. During power-down, this output will retain the last digital state before shutdown. With CLR pulled low, UPO will reset to the default state after wake-up. 4

15 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference Applicatio Information Definitio Integral Nonlinearity (INL) Integral nonlinearity (Figure 8a) is the deviation of the values on an actual trafer function from a straight line. This straight line can be either a best-straight-line fit (closest approximation to the actual trafer curve) or a line drawn between the endpoints of the trafer function, once offset and gain errors have been nullified. For a DAC, the deviatio are measured at every single step. Differential Nonlinearity (DNL) Differential nonlinearity (Figure 8b) is the difference between an actual step height and the ideal value of ANALOG PUT ALUE (LSB) AT STEP (/4 LSB ) AT STEP O (/2 LSB ) LSB. If the magnitude of the DNL is less than or equal to LSB, the DAC guarantees no missing codes and is monotonic. Offset Error The offset error (Figure 8c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compeated for by trimming. Gain Error Gain error (Figure 8d) is the difference between the ideal and the actual full-scale output voltage on the trafer curve, after nullifying the offset error. This error alters the slope of the trafer function and corresponds to the same percentage error in each step. ANALOG PUT ALUE (LSB) 3 2 ACTUAL OFFSET POINT ACTUAL DIAGRAM IDEAL OFFSET POINT OFFSET ERROR (+ /4 LSB) IDEAL DIAGRAM / Figure 8a. Integral Nonlinearity Figure 8c. Offset Error 6 7 IDEAL FULL-SCALE PUT ANALOG PUT ALUE (LSB) LSB LSB DIFFERENTIAL LINEARITY ERROR (-/4 LSB) DIFFERENTIAL LINEARITY ERROR (+/4 LSB) ANALOG PUT ALUE (LSB) GAIN ERROR (- /4 LSB) IDEAL DIAGRAM ACTUAL FULL-SCALE PUT Figure 8b. Differential Nonlinearity Figure 8d. Gain Error 5

16 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / Settling Time The settling time is the amount of time required from the start of a traition until the DAC output settles to its new output value within the converter s specified accuracy. Digital Feedthrough Digital feedthrough is noise generated on the DAC s output when any digital input traitio. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Unipolar Output Figure 9 shows the / setup for unipolar, rail-to-rail operation with a closed- loop gain of 2/. With its internal reference of +2.5, the provides a convenient unipolar output range of to , while the offers an output range of to with its on-board +.25 reference. Table 5 lists example codes for unipolar output voltages. REF DAC NOTE: GAIN = +2/ AGND +5/+3 DGND Figure 9. Unipolar Output Circuit Using Internal (+.25/+2.5) or External Reference. With external reference, pull REFADJ to DD. DD FB 5k 5k Bipolar Output The / can be configured for unitygain bipolar operation (FB = ) using the circuit shown in Figure. The output voltage is then given by the following equation: = REF [{G (NB / 496)} - ] where NB is the numeric value of the DAC s binary input code, REF is the voltage of the internal (or external) precision reference, and G is the overall gain. The application circuit in Figure uses a low-cost op amp (MAX462) external to the /. Together with the / this circuit offers an overall gain of +2/. Table 6 lists example codes for bipolar output voltages. Reset (RSTAL) and Clear (CLR) Functio The / DACs feature a clear pin (CLR), which resets the output to a certain value, depending upon how RSTAL is set. RSTAL = DGND selects an output of, and RSTAL = DD selects a midscale output when CLR is pulled low. The CLR pin has a minimum input resistance of 4kΩ in series with a diode to the supply voltage ( DD ). If the digital voltage is higher than the supply voltage for the part, a small input current may flow, but this current will be limited to ( CLR - DD -.5) / 4kΩ. Note: Clearing the DAC will also cause the part to exit a software shutdown (PD = ). REF DAC DGND +5/+3 5k 5k DD AGND MAX462 Figure. Unity-Gain Bipolar Output Circuit Using Internal (+.25/+2.5) or External Reference. With external reference, pull REFADJ to DD. Daisy-Chaining Devices Any number of /s may be daisychained by simply connecting the serial data output pin (D) of one device to the serial data input pin () of the following device in the chain (Figure ). Another configuration (Figure 2) allows several / DACs to share one common signal line. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. However, more I/O lines are required in this configuration, because each IC needs a dedicated line. FB + - 6

17 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference Table 5. Unipolar Code Table (Figure 9) MSB DAC CONTENTS LSB SUB-BIT S Table 6. Bipolar Code Table (Figure ) DAC CONTENTS MSB LSB SUB-BIT S REF (249 / 496) REF (248 / 496) 2 ANALOG PUT INTERNAL REFERENCE EXTERNAL REFERENCE / m µ REF (495 / 496) 2 REF (247 / 496) 2 REF ( / 496) 2 ANALOG PUT INTERNAL REFERENCE EXTERNAL REFERENCE / REF [ {2 (495 / 496)} - ] +.227m +6.35µ REF [ {2 (249 / 496)} - ] REF [ {2 (248 / 496)} - ] -.227m -6.35µ REF [ {2 (247 / 496)} - ] REF [ {2 ( / 496)} - ] REF / I II III D D D TO OTHER SERIAL DEICES Figure. Daisy-Chaining Multiple Devices with the Digital I/Os /D 7

18 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference / Using an External Reference with AC Components The / have multiplying capabilities within the reference input voltage range specificatio. Figure 3 shows a technique for applying a sinusoidal input to REF, where the AC signal is offset before being applied to the reference input. Power-Supply and Bypassing Coideratio On power-up, the input and DAC registers are cleared to either zero (RSTAL = DGND) or midscale (RSTAL = 2 3 DD). Bypass the power supply (DD) with a 4.7µF capacitor in parallel with a.µf capacitor to AGND. Minimize lead lengths to reduce lead inductance. Layout Coideratio Digital and AC signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. TO OTHER SERIAL DEICES I II III Figure 2. Multiple Devices Share One Common Digital Input () +5/ +3 AC REFERENCE INPUT 26k +5/+3 MAX495 Chip Information TRANSISTOR COUNT: 338 SUBSTRATE CONNECTED TO AGND 5mp-p k REF DD FB DAC AGND DGND Figure 3. External Reference with AC Components 8

19 +5/+3, 2-Bit, Serial, Force/See DACs with ppm/ C Internal Reference Package Information (The package drawing(s) in this data sheet may not reflect the most current specificatio. For the latest package outline information, go to QSOP.EPS / PACKAGE LINE, QSOP.5",.25" LEAD PITCH 2-55 F Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 9 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

20 Mouser Electronics Authorized Distributor Click to iew Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: AEEE+ AEEE+ AEEE+T BEEE+ BEEE+T AEEE+T BEEE+ BEEE+T