MAX1242/MAX V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8

Transcription

1 / General Description The / are low-power, 1-bit analogto-digital converters (ADCs) available in 8-pin packages. They operate with a single +2.7V to +5.25V supply and feature a 7.5µs successive-approximation ADC, a fast track/hold (1.5µs), an on-chip clock, and a high-speed, 3-wire serial interface. Power coumption is only 3mW (V DD = 3V) at the 73ksps maximum sampling speed. A 2µA shutdown mode reduces power at slower throughput rates. The has an internal 2.5V reference, while the requires an external reference. The accepts signals from V to V REF, and the reference input range includes the positive supply rail. An external clock accesses data from the 3-wire interface, which connects directly to standard microcontroller I/O ports. The interface is compatible with SPI, QSPI, and MICROWIRE. Excellent AC characteristics and very low power combined with ease of use and small package size make these converters ideal for remote-seor and dataacquisition applicatio, or for other circuits with demanding power coumption and space requirements. The / are available in 8-pin PDIP and SO packages. Portable Data Logging Test Equipment Isolated Data Acquisition TOP VIEW V DD AIN SHDN REF Applicatio Process Control Monitoring Temperature Measurement Pin Configuration PDIP/SO GND Features +2.7V to +5.25V Single-Supply Operation 1-Bit Resolution Internal 2.5V Reference () Small Footprint: 8-Pin DIP and SO Packages Low Power: 3.7mW (73ksps, ) 3mW (73ksps, ) 66µW (1ksps, ) 5µW (Power-Down Mode) Internal Track/Hold SPI/QSPI /MICROWIRE 3-Wire Serial Interface Pin-Compatible 12-Bit Upgrades: MAX124/MAX1241 Ordering Information AEPA+ - 4 C to + 85 C 8 PDIP ± 1 / 2 Ordering Information continued at end of data sheet. Note: Order the A in place of the C. Order the B in place of the D. +Denotes a lead(pb)-free/rohs-compliant package. Functional Diagram SHDN AIN REF PART CONTROL LOGIC T/H 2.5V REFERENCE ONLY TEMP RANGE V DD 1 5 GND INT CLOCK 1-BIT SAR PIN- PACKAGE OUTPUT SHIFT REGISTER 6 INL (LSB) ACPA+ C to +7 C 8 PDIP ± 1 / 2 BCPA+ C to +7 C 8 PDIP ±1 AA+ C to +7 C 8 SO ± 1 / 2 BA+ C to +7 C 8 SO ±1 QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at ; Rev 3; 1/12

2 / ABSOLUTE MAXIMUM RATINGS V DD to GND...-.3V to +6V AIN to GND...-.3V to (V DD +.3V) REF to GND...-.3V to (V DD +.3V) Digital Inputs to GND...-.3V to +6V to GND...-.3V to (V DD +.3V) Current...±25mA Continuous Power Dissipation (T A = +7 C) PDIP (derate 9.9mW/ C above +7 C)...727mW SO (derate 5.88mW/ C above +7 C)...471mW Operating Temperature Ranges /_C_A... C to +7 C /_E_ A...-4 C to +85 C Storage Temperature Range...-6 C to +15 C Lead Temperature (soldering, 1s)...+3 C Soldering Temperature (reflow) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI (V DD = +2.7V to +5.25V; 73ksps; f = 2.1MHz (5% duty cycle); 4.7µF capacitor at REF pin, external reference; V REF = 2.5V applied to REF pin; T A = T MIN to T MAX ; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note1) Resolution 1 Bits Relative Accuracy (Note 2) MAX124_A ±.5 MAX124_B ±1. LSB Differential Nonlinearity DNL No missing codes over temperature ±1 LSB Offset Error MAX124_A ±1 MAX124_B ±2 LSB Gain Error (Note 3) MAX124_A ±1 MAX124_B ±2 LSB Gain Temperature Coefficient ±.25 ppm/ C DYNAMIC SPECIFICATIONS (1kHz sine-wave input, V to 2.5Vp-p, P-P, 73ksps, ff =2.1MHz) = Signal-to-Noise Plus Distortion Ratio SINAD 66 db Total Harmonic Distortion THD Up to the 5th harmonic -7 db Spurious-Free Dynamic Range SFDR 7 db Small-Signal Bandwidth -3dB rolloff 2.25 MHz Full-Power Bandwidth 1. MHz CONVERSION RATE Conversion Time t CONV µs Track/Hold Acquisition Time t ACQ 1.5 µs Throughput Rate f = 2.1MHz 73 ksps Aperture Delay t AP Figure 9 3 Aperture Jitter <5 ps ANALOG INPUT Input Voltage Range V REF V Input Capacitance 16 pf 2 Maxim Integrated

3 / ELECTRICAL CHARACTERISTI (continued) (V DD = +2.7V to +5.25V; 73ksps; f = 2.1MHz (5% duty cycle); 4.7µF capacitor at REF pin, external reference; V REF = 2.5V applied to REF pin; T A = T MIN to T MAX ; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL REFERENCE ( only) REF Output Voltage T A = +25 C (Note 4) V REF Short-Circuit Current 3 ma REF Temperature Coefficient ±3 ppm/ C Load Regulation (Note 5) ma to.2ma output load.35 mv Capacitive Bypass at REF 4.7 µf EXTERNAL REFERENCE (V REF = 2.5V) Input Voltage Range Input Current Input Resistance REF Input Current in Shutdown DIGITAL INPUTS:,, SHDN, Input High Voltage V IH V DD 3.6V 2. V DD > 3.6V 3., Input Low Voltage V DD = 3.6V Operating mode () Operating mode () V DD = 5.25V Supply Current I DD Operating mode () V DD = 3.6V V DD = 5.25V Power-down V DD = 3.6V V DD = 5.25V Power-Supply Rejection (Note 7) PSR V DD = V DD (min) to V DD (max), full-scale input 1. V DD + 5mV Capacitive Bypass at REF.1 µf V IL.8, Input Hysteresis V HYST.2 V, Input Leakage I IN V IN = V or V DD ±.1 ±1 µa, Input Capacitance C IN (Note 6) 15 pf SHDN Input High Voltage V SH V DD -.4 SHDN Input Low Voltage V SL.4 V SHDN Input Current V SHDN = V or V DD ±4. µa SHDN Input Mid Voltage V SM 1.1 V DD V SHDN Voltage, Open V FLT SHDN = open V DD / 2 V SHDN Max Allowed Leakage, Mid Input V SHDN = V SHDN = open kω DIGITAL OUTPUT: Output Voltage Low V OL I SINK = 5mA.4 I SINK = 16mA.8 V Output Voltage High V OH I SOURCE =.5mA V DD -.5 V Three-State Leakage Current I L = V DD ±.1 ±1 µa Three-State Output Capacitance C OUT = V DD (Note 6) 15 pf POWER REQUIREMENTS ±1 V 1 15 µa ±.1 1 µa Supply Voltage V DD V ±.3 V V V na ma µa mv Maxim Integrated 3

4 / TIMING CHARACTERISTI (V DD = +2.7V to +5.25V, circuit of Figure 9, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Acquisition Time t ACQ = V DD (Note 8) 1.5 µs Fall to Output Data Valid t DO Figure 1, MAX124 C/E 2 2 Fall to Output Enable t DV Figure 1, 24 Rise to Output Disable t TR Figure 2, 24 Clock Frequency f 2.1 MHz Pulse Width High t CH 2 Pulse Width Low t CL 2 Low to Fall Setup Time t 5 Rise to Rise (Note 6) t STR Pulse Width t 24 Note 1: Tested at V DD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: Offset nulled. Note 4: Sample tested to.1% AQL. Note 5: External load should not change during conversion for specified accuracy. Note 6: Guaranteed by design. Not subject to production testing. Note 7: Measured as [V FS (V DD (min)) - V FS (V DD (max))]. Note 8: To guarantee acquisition time, t ACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. +2.7V 6kΩ 6kΩ DGND DGND a) High-Z to V OH and V OL to V OH b) High-Z to V OL and V OH to V OL Figure 1. Load Circuits for Enable Time +2.7V 6kΩ 6kΩ DGND DGND a) V OH to High-Z b) V OL to High-Z Figure 2. Load Circuits for Disable Time 4 Maxim Integrated

5 / Typical Operating Characteristics (V DD = +3.V, V REF = 2.5V, f = 2.1MHz, C LOAD = 2pF, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) C LOAD = 2pF SUPPLY CURRENT vs. SUPPLY VOLTAGE C LOAD = 2pF SUPPLY VOLTAGE (V) R L = CODE = 1111 /43-1 SHUTDOWN SUPPLY CURRENT (μa) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE / SUPPLY VOLTAGE (V) /43-2 INTERNAL REFERENCE VOLTAGE (V) INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) / SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE R LOAD = CODE = TEMPERATURE ( C) /43-4 INL (LSB) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) /43-7 INTERNAL REFERENCE VOLTAGE (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE V DD = 5V V DD = 3.6V V DD = 2.7V TEMPERATURE ( C) / INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE / V DD = 2.7V INTEGRAL NONLINEARITY vs. TEMPERATURE / INTEGRAL NONLINEARITY vs. CODE / INL (LSB).15 INL (LSB).15 INL (LSB) SUPPLY VOLTAGE (V) TEMPERATURE ( C) CODE Maxim Integrated 5

6 / Pin Description PIN NAME FUNCTION 1 V DD Positive Supply Voltage: +2.7V to +5.25V 2 AIN Sampling Analog Input, V to V REF range 3 SHDN Three-Level Shutdown Input. Pulling SHDN low shuts the / down to 15µA (max) supply current. Both and are fully operational with either SHDN high or open. For the, pulling SHDN high enables the internal reference, and letting SHDN open disables the internal reference and allows for the use of an external reference. Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for ; 4 REF bypass with a 4.7µF capacitor. External reference voltage input for, or for with the internal reference disabled. Bypass REF with a minimum of.1µf when using an external reference. 5 GND Analog and Digital Ground 6 Serial-Data Output. Data changes state at s falling edge. High impedance when is high. 7 Active-Low Chip Select. Initiates conversio on the falling edge. When is high, is high impedance. 8 Serial-Clock Input. clocks data out at rates up to 2.1MHz. Detailed Description Converter Operation The / use an input track/hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 1-bit output. Figure 3 shows the / in their simplest configuration. The / convert input signals in the V to V REF range in 9µs, including T/H acquisition time. The s internal reference is trimmed to 2.5V, while the requires an external reference. Both devices accept external reference voltages from 1.V to V DD. The serial interface requires only three digital lines (,, and ) and provides an easy interface to microprocessors (μps). The / have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current below 1µA (V DD 3.6V), while pulling SHDN high or leaving it open puts the devices into operational mode. A conversion is initiated by pulling low. The conversion result is available at in unipolar serial format. The serial-data stream coists of a high bit, signaling the end of conversion (EOC), followed by the data bits (MSB first). Analog Input Figure 4 illustrates the sampling architecture of the analog-to-digital converter s (ADC s) comparator. The fullscale input voltage is set by the voltage at REF. Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitor. In hold mode, the T/H switch ope and maintai a cotant input to the ADC s SAR section. During acquisition, the analog input AIN charges capacitor C HOLD. Bringing low ends the acquisition interval. At this itant, the T/H switches the input side of C HOLD to GND. The retained charge on C HOLD represents a sample of the input, unbalancing node ZERO at the comparator s input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to V within the limits of 1- bit resolution. This action is equivalent to traferring a charge from C HOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversion s end, the input side of C HOLD switches back to AIN, and C HOLD charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal s source impedance is high, the acquisition time lengthe, and more time must be allowed between conversio. The acquisition time, t ACQ, is the maximum time the device takes to acquire the signal and the minimum time needed for the signal to be acquired. Acquisition time is calculated by: t ACQ = 7(R S + R IN ) x 16pF 6 Maxim Integrated

7 / +2.7V to +5.25V 4.7μF ANALOG INPUT V TO V REF SHUTDOWN INPUT REFERENCE INPUT.1μF C* V DD AIN SHDN REF GND SERIAL INTERFACE AIN GND REF TRACK INPUT HOLD CAPACITIVE DAC C HOLD pF C SWITCH TRACK 9kΩ R IN ZERO HOLD COMPARATOR AT THE SAMPLING INSTANT, THE INPUT SWITCHES FROM AIN TO GND. *4.7μF,.1μF, Figure 3. Operational Diagram Figure 4. Equivalent Input Circuit where R IN = 9kΩ, R S = the input signal s source impedance, and t ACQ is never less than 1.5µs. Source impedances below 4kΩ do not significantly affect the ADC s AC performance. Higher source impedances can be used if a.1µf capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC s input signal bandwidth. Input Bandwidth The ADC s input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed traient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes, which clamp the analog input to V DD and GND, allow the input to swing from GND -.3V to V DD +.3V without damage. However, for accurate conversio near full scale, the input must not exceed V DD by more than 5mV, or be lower than GND by 5mV. If the analog input exceeds 5mV beyond the supplies, limit the input current to 2mA. Internal Reference () The has an on-chip voltage reference trimmed to 2.5V. The internal reference output is connected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to 4µA. Bypass REF with a 4.7µF capacitor. Larger capacitors increase wake-up time when exiting shutdown (see Using SHDN to Reduce Supply Current). The internal reference is enabled by pulling the SHDN pin high. Letting SHDN open disables the internal reference, which allows the use of an external reference, as described in the External Reference section. External Reference The / operate with an external reference at the REF pin. To use the with an external reference, disable the internal reference by letting SHDN open. Stay within the voltage range 1.V to V DD to achieve specified accuracy. The minimum input impedance is 18kΩ for DC currents. During conversion, the external reference must be able to deliver up to 25µA of DC load current and have an output impedance of 1Ω or less. The recommended minimum value for the bypass capacitor is.1µf. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor. Maxim Integrated 7

8 / Serial Interface Initialization after Power-Up and Starting a Conversion When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7µF reference bypass capacitor up to 2ms to provide adequate charge for specified accuracy. With an external reference, the internal reset time is 1µs after the power supplies have stabilized. No conversio should be performed during these times. To start a conversion, pull low. At s falling edge, the T/H enters its hold mode and a conversion is initiated. After an internally timed conversion period, the end of conversion is signaled by pulling high. Data can then be shifted out serially with the external clock. Using SHDN to Reduce Supply Current Power coumption can be reduced significantly by shutting down the / between conversio. Figure 6 shows a plot of average supply current vs. conversion rate. Because the uses an external reference voltage (assumed to be present continuously), it wakes up from shutdown more quickly, providing lower average supply currents. The wakeup time, t WAKE, is the time from SHDN deasserted to the time when a conversion may be initiated (Figure 5). For the, this time depends on the time in shutdown (Figure 7) because the external 4.7µF reference bypass capacitor loses charge slowly during shutdown. The s wake-up time is largely dependent on the external reference s power-up time. If the external reference is not shut down, the wake-up time is approximately 4µs. COMPLETE CONVERSION SEQUENCE SHDN t WAKE CONVERSION CONVERSION 1 POWERED UP POWERED DOWN POWERED UP Figure 5. Shutdown Sequence SUPPLY CURRENT (μa) 1, V DD = V REF R LOAD =, CODE = 1111 V DD = 3V V DD = 5V V DD = 3V -fig6 POWER-UP DELAY (ms) / k 1k 1k CONVERSIONS/SEC Figure 6. Average Supply Current vs. Conversion Rate TIME IN SHUTDOWN (sec) Figure 7. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown 8 Maxim Integrated

9 / B9 B8 B7 B6 B5 B4 B3 B2 B1 B S1 S EOC INTERFACE IDLE CONVERSION IN PROGRESS EOC CLOCK OUT SERIAL DATA SUB BITS TRAILING ZEROS TRACK/HOLD STATE TRACK HOLD TRACK HOLD.24μs 7.5μs (t CONV ) μs μs = 5.95μs μs (t ) CYCLE TIME TOTAL = 13.7μs Figure 8a. Interface Timing Sequence IDLE / B9 B8 B7 B6 B5 B4 B3 B2 B1 B EOC INTERFACE IDLE CONVERSION IN PROGRESS EOC CLOCK OUT SERIAL DATA IDLE TRACK/HOLD STATE TRACK HOLD TRACK HOLD.24μs 7.5μs (t CONV ) μs μs = 5μs CYCLE TIME TOTAL = 12.74μs (t ) Figure 8b. Interface Timing Sequence Minimum Cycle Time t t CH t DO t CL t TR t t DV t CONV B S1 S t AP t STR INTERNAL T/H (TRACK/ACQUIRE) (HOLD) (TRACK/ACQUIRE) Figure 9. Detailed Serial-Interface Timing Maxim Integrated 9

10 / External Clock The actual conversion does not require the external clock. This allows the conversion result to be read back at the µp s convenience at any clock rate up to 2.1MHz. The clock duty cycle is unrestricted if each clock phase is at least 2. Do not run the clock while a conversion is in progress. OUTPUT CODE FULL-SCALE TRANSITION Timing and Control Conversion-start and data-read operatio are controlled by the and digital inputs. The timing diagrams of Figures 8 and 9 outline serial-interface operation. A falling edge initiates a conversion sequence: the T/H stage holds the input voltage, the ADC begi to convert, and changes from high impedance to logic low. must be kept low during the conversion. An internal register stores the data when the conversion is in progress. EOC is signaled by going high. s rising edge can be used as a framing signal. shifts the data out of this register any time after the conversion is complete. traitio on s falling edge. The next falling clock edge produces the MSB of the conversion at, followed by the remaining bits. Since there are 1 data bits, two sub-bits, and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of, produce trailing zeros at and have no effect on converter operation. For minimum cycle time, use s rising edge as the EOC signal and then clock out the data with 1.5 clock cycles at full speed (Figure 8b). Pull high after reading the conversion s LSB. After the specified minimum time, t, pull low again to initiate the next conversion. Output Coding and Trafer Function The data output from the / is binary. Figure 1 depicts the nominal trafer function. Code traitio occur halfway between successive-integer LSB values. If VREF = 2.5V, then 1LSB = 2.44mV or 2.5V / 124. Applicatio Information Connection to Standard Interfaces The / serial interface is fully compatible with SPI, QSPI, and Microwire standard serial interfaces (Figure 11) FS INPUT VOLTAGE (LSB) FS - 3/2LSB Figure 1. Unipolar Trafer Function, Full Scale (FS) = V REF - 1LSB, Zero Scale (ZS) = GND a) SPI b) QSPI c) MICROWIRE I/O SCK MISO SS SCK MISO SS I/O SK SI +3V +3V FS = V REF - 1LSB 1LSB = V REF 124 Figure 11. Common Serial-Interface Connectio to the / 1 Maxim Integrated

11 / 1ST BYTE READ 2ND BYTE READ t CONV D9 D8 D7 D6 D5 D4 D3 D2 D1 D S1 S HIGH-Z MSB LSB EOC Figure 12. SPI/Microwire Serial-Interface Timing (CPOL = CPHA = ) t CONV D9 D8 D7 D6 D5 D4 D3 D2 D1 D S1 S MSB LSB HIGH-Z EOC Figure 13. QSPI Serial-Interface Timing (CPOL = CPHA = ) If a serial interface is available, set the CPU s serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 2.1MHz. 1) Use a general-purpose I/O line on the CPU to pull low. Keep low. 2) Wait the maximum conversion time specified before activating. Alternatively, look for a rising edge to determine the end of conversion. 3) Activate for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the conversion. output data traitio on s falling edge and is available in MSB-first format. Observe the -to- valid timing characteristic. Data can be clocked into the µp on s rising edge. 4) Pull high at or after the 11th falling clock edge. If remai low, the two sub-bits and trailing zeros are clocked out after the LSB. 5) With = high, wait the minimum specified time, t, before initiating a new conversion by pulling low. If a conversion is aborted by pulling high before the conversion s end, wait the minimum acquisition time, t ACQ, before starting a new conversion. Data can be output in two bytes or continuously, as shown in Figures 8a and 8b. The bytes contain the result of the conversion padded with one leading 1, two sub-bits, and trailing s if is still active with kept low. SPI and Microwire When using SPI or QSPI, set CPOL = and CPHA =. Conversion begi with a falling edge. goes low, indicating a conversion is in progress. Wait until goes high or until the maximum specified 7.5µs conversion time elapses. Two coecutive 1-byte reads are required to get the full 1+2 bits from the ADC. output data traitio on s falling edge and is clocked into the µp on s rising edge. The first byte contai a leading 1, and seven bits of conversion result. The second byte contai the remaining three bits, two sub-bits, and three trailing zeros. See Figure 11 for connectio and Figure 12 for timing. QSPI Set CPOL = CPHA =. Unlike SPI, which requires two 1-byte reads to acquire the 1 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The / require 11 clock cycles from the µp to clock out the 1 bits of data. Additional clock cycles clock out the two sub-bits followed by trailing zeros (Figure 13). The maximum clock frequency to eure compatibility with QSPI is 2.97MHz. Layout and Grounding For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should eure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Maxim Integrated 11

12 / Ordering Information (continued) TEMP PIN- INL PART RANGE PACKAGE (LSB) BEPA+ - 4 C to + 85 C 8 PDIP ±1 Chip Information SUBSTRATE CONNECTED TO GND PROCESS: BiCMOS AESA+ - 4 C to + 85 C 8 SO ± 1 / 2 BESA+ - 4 C to + 85 C 8 SO ±1 ACPA+ C to +7 C 8 PDIP ± 1 / 2 BCPA+ C to +7 C 8 PDIP ±1 AA+ C to +7 C 8 SO ± 1 / 2 BA+ C to +7 C 8 SO ±1 AEPA+ - 4 C to + 85 C 8 PDIP ± 1 / 2 BEPA+ - 4 C to + 85 C 8 PDIP ±1 AESA+ - 4 C to + 85 C 8 SO ± 1 / 2 Package Information For the latest package outline information and land patter (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertai to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 PDIP P SO S BESA+ - 4 C to + 85 C 8 SO ±1 Note: Order the A in place of the C. Order the B in place of the D. +Denotes a lead(pb)-free/rohs-compliant package. 12 Maxim Integrated

13 REVISION NUMBER REVISION DATE / DESCRIPTION Revision History PAGES CHANGED 11/96 Initial release 2 6/98 Extended temperature parts available 3 1/12 Removed military grades and added stylistic changes. 1 7, 12 Maxim Integrated cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licees are implied. Maxim Integrated reserves the right to change the circuitry and specificatio without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 16 Rio Robles, San Jose, CA USA Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.