PART MAX4584EUB MAX4585EUB TOP VIEW

Transcription

1 ; Rev ; 8/99 General Description The serial-interface, programmable switches are ideal for multimedia applicatio. Each device contai one normally open (NO) single-pole/ single-throw (SPST) switch and one single-pole/doublethrow (SPDT) switch. The feature 65Ω on-resistance, 4Ω on-resistance matching between channels, and 5Ω on-resistance flatness. Additionally, they have off-isolation of -83dB at 2kHz and -48dB at 1MHz, with crosstalk of -84dB at 2kHz and -6dB at 1MHz. The MA4584 uses a 2-wire I 2 C -compatible serial interface; the MA4585 uses a 3-wire SPI /QSPI / MICROWIRE -compatible interface. Both devices are available in a 1-pin µma package and are specified for the extended-industrial (-4 C to +85 C) temperature range. Serially Controlled Features +2.7 to +5.5 Single-Supply Operation SPST and SPDT Switches 65Ω (max) R ON with +5 Supply Audio Performance -83dB Off-Isolation at 2kHz -84dB Crosstalk at 2kHz ideo Performance -48dB Off-Isolation at 1MHz -6dB Crosstalk at 1MHz Serial Interface 2-Wire I 2 C Compatible (MA4584) 3-Wire SPI/QSPI/MICROWIRE Compatible (MA4585) Cellular Phones and Accessories Private Mobile Radios (PMRs) PC Multimedia Audio/ideo Routing Industrial Equipment Set-Top Boxes ideo Conferencing High-End Audio Equipment Applicatio PART MA4584EUB MA4585EUB Ordering Information TEMP. RANGE -4 C to +85 C -4 C to +85 C PIN-PACKAGE 1 µma 1 µma Pin Configuration/ Functional Diagram TOP IEW MA4584 MA4585 COM1 1 1 NO1A A (CS) 2 9 NO1B SDA (DIN) COM2 SCL (SCLK) 5 6 NO2 I 2 C is a trademark of Philips Corp. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ( ) ARE FOR MA4585 ONLY. µma Maxim Integrated Products 1 For free samples & the latest literature: or phone For small orders, phone

2 ABSOLUTE MAIMUM RATINGS to to +6 and NO to (Note 1) to ( +.3) A, CS, SDA, DIN, SCL, and SCLK to to +6 Continuous Current into Any Terminal...±2mA Peak Current into Any Terminal (pulsed at 1ms, 1% duty cycle)...±4ma ESD per Method >2k Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICSSingle +5 Supply Continuous Power Dissipation (T A = +7 C) µma (derate 4.1mW/ C above +7 C)...33mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1sec)...+3 C Note 1: Signals on NO or exceeding or ground are clamped by internal diodes. Limit forward-diode current to maximum current rating. ( = +5 ±5%,, unless otherwise noted. Typical values are at.) (Note 2) PARAMETER ANALOG SWITCHES Analog Signal Range (Note 3) SYMBOL NO, CONDITIONS MIN TYP MA UNITS On-Resistance R ON = 4.75, NO = 3, I = 4mA Ω On-Resistance Match Between Channels (Note 4) R ON = 4.75, NO = 3, I = 4mA Ω On-Resistance Flatness (Note 5) R FLAT = 4.75; NO = 1, 2, 3; I = 4mA Ω NO Off-Leakage Current (Note 6) I NO (OFF) = 5.25; NO = 1, 4.5; = 4.5, na Off-Leakage Current (Note 6) I (OFF) = 5.25; NO = 1, 4.5; = 4.5, na On-Leakage Current (Note 6) I (ON) = 5.25; NO = 1, 4.5, or floating; = 1, na AUDIO PERFORMANCE Off-Isolation (Note 7) ISO(A) A = 1 RMS, f IN = 2kHz, R L = 6Ω, Figure 8-83 db Channel-to-Channel Crosstalk AUDIO PERFORMANCE CT(A) A = 1 RMS, f IN = 2kHz, R S = 6Ω, Figure 8-84 db 2

3 ELECTRICAL CHARACTERISTICSSingle +5 Supply (continued) ( = +5 ±5%,, unless otherwise noted. Typical values are at.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS IDEO PERFORMANCE Off-Isolation (Note 7) A = 1 RMS, f IN = 1MHz, ISO() -48 db R L = 5Ω, Figure 8 Channel-to-Channel Crosstalk A = 1 RMS, f IN = 1MHz, CT() -6 db R S = 5Ω, Figure 8 -.1dB Bandwidth BW R S = 75Ω, R L = 1kΩ 5 MHz -3dB Bandwidth BW R S = 5Ω, R L = 5Ω 3 MHz NO Off-Capacitance C OFF f IN = 1MHz 5 pf DYNAMIC TIMING (Notes, 8, 11, and Figure 5) Turn-On Time t ON C L = 35pF, NO = 2.5, R L = 5kΩ Turn-Off Time NO = 2.5, C L = 35pF, R L = 3Ω Break-Before-Make Time t BBM NO = 2.5, Figure Charge Injection Q C L = 1.nF, S =, R S =, Figure 7 3 pc POWER SUPPLY Power-Supply oltage Range Supply Current I+ All logic inputs = or 5 1 µa 3

4 ELECTRICAL CHARACTERISTICSSingle +3 Supply ( = +3. ±1%,, unless otherwise noted. Typical values are at.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS ANALOG SWITCHES Analog Signal Range (Note 3) On-Resistance On-Resistance = 2.7, 3 5 Match Between Channels R ON NO = 1, (Note 4) I = 4mA 6 On-Resistance Flatness (Note 5) NO Off-Leakage Current (Notes 6, 9) NO, R ON R FLAT I NO (OFF) = 2.7, NO = 1, I = 4mA = 2.7; NO = 1, 1.5, 2; I = 4mA = 3.6; COM _ =.5, 3; NO = 3, Ω Ω Ω na Off-Leakage Current (Notes 6, 9) I COM _ (OFF) = 3.6; COM _ =.5, 3; NO = 3, na COM _ On-Leakage Current (Notes 6, 9) AUDIO PERFORMANCE Off-Isolation (Note 7) Channel-to-Channel Crosstalk IDEO PERFORMANCE Off-Isolation Channel-to-Channel Crosstalk -3dB Bandwidth NO Off-Capacitance Turn-On Time Turn-Off Time I COM _ (ON) ISO(A) CT(A) ISO() CT() C OFF NO = 1.5, R L = 5kΩ, C L = 35pF NO = 1.5, R L = 3Ω, C L = 35pF Break-Before-Make Time t BBM NO = 1.5, Figure 6 BW DYNAMIC TIMING (Notes 8, 11, and Figure 5) t ON = 3.6; =.5, 3; NO =.5, 3, or floating A =.5 RMS, f IN = 2kHz, R L = 6Ω, Figure 8 A =.5 RMS, f IN = 2kHz, R S = 6Ω, Figure 8 A =.5 RMS, f IN = 1MHz, R L = 5Ω, Figure 8 A =.5 RMS, f IN = 1MHz, R S = 5Ω, Figure 8 R S = 5Ω, R L = 5Ω f IN = 1MHz na db db db db MHz pf 4

5 I/O INTERFACE CHARACTERISTICS ( = +2.7 to +5.25,, unless otherwise noted. Typical values are at.) PARAMETER Input Hysteresis Input Capacitance SYMBOL DIGITAL INPUTS (SCLK, DIN, CS, SCL, SDA, A) Input Low oltage Input High oltage Input Leakage Current DIGITAL OUTPUT (SDA) Output Low oltage IL IH HYST I LEAK C IN OL = 5 CONDITIONS MIN TYP MA = 3.6 = 5 = 3 Digital inputs = or I SINK = 6mA UNITS µa pf 2-WIRE TIMING CHARACTERISTICS (Figures 1 and 2, = +2.7 to +5.25, f SCL = 1kHz,, unless otherwise noted. Typical values are at.) Data Hold Time PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditio Hold Time After Start Condition Stop Condition Setup Time Data Setup Time Clock Low Period Clock High Period SCL/SDA Rise Time (Note 1) SCL/SDA Fall Time (Note 1) SYMBOL f SCL t BUF t HD:STA t SU:STO t HD:DAT t SU:DAT t LOW t HIGH t R t F CONDITIONS = 2.7 to 5.25 = 4.75 to 5.25 The first clock is generated after this period. MIN TYP MA C B 2 +.1C B UNITS khz µs µs µs µs µs µs 5

6 3-WIRE TIMING CHARACTERISTICS (Figures 3 and 4, = to +5.25, f OP = 2.1MHz,, unless otherwise noted. Typical values are at.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS = 2.7 to Operating Frequency f OP = 4.75 to DIN to SCLK Setup t DS 1 DIN to SCLK Hold t DH CS Fall to SCLK Rise Setup t CSS 1 CS Rise to SCLK Hold t CSH SCLK Pulse Width Low t CL 2 SCLK Pulse Width High t CH 2 Rise Time (SCLK, DIN, CS) t R 2 µs Fall Time (SCLK, DIN, CS) t F 2 µs CS Pulse Width High t CSW 4 Note 2: Algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 3: Guaranteed by design. Not subject to production testing. Note 4: R ON = R ON(MA) - R ON(MIN). Note 5: Resistance flatness is defined as the difference between the maximum and minimum on-resistance values, as measured over the specified analog signal range. Note 6: Leakage parameters are 1% tested at maximum rated temperature and guaranteed by correlation at. Note 7: Off-isolation = 2 log ( COM _ / NO ), COM _ = output, NO = input to off switch. Note 8: All timing is measured from the clock s falling edge preceding the ACK signal for 2-wire and from the rising edge of CS for 3-wire. Turn-off time is defined at the output of the switch for a.5 change, tested with a 3Ω load to ground. Turn-on time is defined at the output of the switch for a.5 change and measured with a 5kΩ load resistor to. All timing is shown with respect to 2% and 7%, unless otherwise noted. Note 9: Leakage testing is guaranteed by testing with a supply. Note 1: C B = capacitance of one bus line in pf. Tested with C B = 4pF. Note 11: Typical values are for MA4584 devices. MHz ( = +5,, unless otherwise noted.) Typical Operating Characteristics RON (Ω) ON-RESISTANCE vs. COM AND SUPPLY OLTAGE = 2.7 = COM () = 4. = 5.5 = 5. MA4584/5-1 RON (Ω) ON-RESISTANCE vs. COM AND TEMPERATURE ( = 5) T A = +125 C T A = +85 C T A = -55 C COM () T A = -4 C MA4584/5-2 RON (Ω) ON-RESISTANCE vs. COM AND TEMPERATURE ( = 3.3) 75 7 T A = +85 C T A = +125 C T A = -4 C COM () T A = -55 C MA4584/5-3 6

7 Typical Operating Characteristics (continued) ( = +5,, unless otherwise noted.) SUPPLY CURRENT (µa) SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) MA4584/5-4 CHARGE INJECTION (pc) CHARGE INJECTION vs. COM COM () MA4584/5-5 TIME () TURN-ON/TURN-OFF TIMES vs. SUPPLY OLTAGE t ON SUPPLY OLTAGE () MA4584/5-6 TIME () TURN-ON/TURN-OFF TIMES vs. TEMPERATURE t ON TEMPERATURE ( C) MA4584/5-7 CURRENT (na) OFF-LEAKAGE CURRENT vs. TEMPERATURE I NO (OFF) AT NO = 4.5 COM = 1. I NO (OFF) AT NO = 1. COM = 4.5 I COM (OFF) AT COM = 1. NO = 4.5 I COM (OFF) AT COM = 4.5 NO = TEMPERATURE ( C) MA4584/5-8a CURRENT (na) ON-LEAKAGE CURRENT vs. TEMPERATURE I COM (ON) AT COM = 4.5 NO = FLOAT I COM (ON) AT COM = 1. NO = FLOAT TEMPERATURE ( C) MA4584/5-8b LOSS (db) AUDIO FREQUENCY RESPONSE 6Ω IN AND OUT OFF-ISOLATION CROSSTALK MA4584/5-9 LOSS (db) IDEO FREQUENCY RESPONSE INSERTION LOSS OFF-ISOLATION CROSSTALK 5Ω IN AND OUT MA4584/5-1 CLK 5/div t ON 2/div 2/div TURN-ON/TURN-OFF TIMES MA4584/ FREQUENCY (MHz) FREQUENCY (MHz) TIME (1/div) 7

8 PIN MA4584 MA4585 NAME 1 1 COM1 2 A 2 CS 3 SDA 3 DIN SCL 5 SCLK 6 6 NO2 7 7 COM NO1B 1 1 NO1A FUNCTION Analog Switch SPDT Common Terminal LSB+2 of the 2-Wire Serial-Interface Address Field Chip Select of the 3-Wire Serial Interface Data Input of the 2-Wire Serial Interface Data Input of the 3-Wire Serial Interface Supply oltage Clock Input of the 2-Wire Serial Interface Clock Input of the 3-Wire Serial Interface Normally Open SPST Terminal Analog Switch SPST Common Terminal Ground Normally Open Terminal Normally Open Terminal Pin Description SDA 2% 7% 7% 2% 7% 2% 7% 2% 7% 2% t LOW t BUF t SU, DAT t SU, STA t HD, STA t HD, DAT t SU, STO SCL t HD, STA 7% 2% 7% 7% 2% 2% t HIGH 7% 7% 7% t R t F START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. 2-Wire Serial-Interface Timing Diagram Detailed Description The are serial-interface, programmable switches. Each device contai one normally open (NO) single-pole/single-throw (SPST) switch and one single-pole/double-throw (SPDT) switch. The switches are independently controlled through the onchip serial interface. The MA4584 uses a 2-wire I 2 C- compatible serial communicatio protocol; the MA4585 uses a 3-wire SPI/QSPI/MICROWIRE-compatible serial communicatio protocol. These devices operate from a single +2.7 to +5.5 supply and are optimized for use with an audio frequency of 2kHz and video frequencies up to 1MHz. They feature 65Ω on-resistance, 4Ω on-resistance matching between channels, and 5Ω on-resistance flatness. Audio off-isolation is -83dB at 2kHz, and crosstalk is at least -84dB at 2kHz. ideo off-isolation is -48dB at 1MHz, and crosstalk is at least -6dB at 1MHz. Applicatio Information Switch Control The have a common command-bit structure; the only difference between them is the interface type (2-wire or 3-wire, respectively). The command controls the open/closed states of the various switches. Table 1 shows the configuration of the data bits and their related switches. After a command is issued, a logic 1 in any data-bit location clos- 8

9 Table 1. Command-Bit Mapping COMMAND BIT D7 (MSB) D6 D5 D4 D3 D2 D1 D (LSB) = Don t care SWITCH NO2 to COM2 NO1B to COM1 NO1A to COM1 SDA TERMINALS 6, 7 9, 1 1, 1 POWER-UP STATE (Open) 1 (Closed) (Open) SLAE ADDRESS BYTE MSB LSB ACK Table 2. Truth Table LOGIC NO1_ AND NO2 OPEN 1 CLOSED Table 3. Address Bit Map ADDRESS BIT (A) ADDRESS COMMAND BYTE MSB LSB ACK SCL START CONDITION STOP CONDITION Figure 2. A Complete 2-Wire Serial-Interface Tramission es the associated switch (Table 2). A logic in any data-bit location ope the associated switch. 2-Wire Serial Interface The MA4584 uses a 2-wire I 2 C-compatible serial interface. The register uses the SendByte protocol, which coists of an address byte followed by a command byte (Table 1). To address a given IC, bit A in the address byte must duplicate the value present at the A pin of that IC. The rest of the address bits must match those shown in Table 3. The command byte details are described in the Switch Control section. The 2-wire serial interface requires only two I/O lines of a standard microprocessor (µp) port. Figures 1 and 2 detail the timing diagram for signals on the 2-wire bus, and Tables 1 and 3 detail the format of the signals. The MA4584 is a receive-only device and must be controlled by the bus master device. A bus master device communicates by tramitting the address byte of the slave device over the bus and then tramitting the desired information. Each tramission coists of a start condition, an address byte, a command byte, and finally a stop condition. The slave device acknowledges the recognition of its address by pulling the SDA line low for one clock period after the address byte is tramitted. The slave device also issues a similar acknowledgment after the command byte. Start and Stop Conditio The bus master signals the beginning of a tramission with a start condition by traitioning SDA from high to low while SCL is high. When the bus master has finished communicating with the slave device, it issues a stop condition by traitioning SDA from low to high while SCL is high. The bus is then free for another tramission. Slave Address (Address Byte) The MA4584 uses an 8-bit-long slave address. To select a slave address, connect A to or. The MA4584 has two possible slave addresses, so a maximum of two of these devices may share the same address line. The slave device MA4584 monitors the serial bus continuously, waiting for a start condition followed by an address byte. When a slave device recognizes its address (111A1), it acknowledges that it is ready for further communication by pulling the SDA line low for one clock period. 9

10 CS 2% SCLK DIN t CSS t CL t CH Figure 3. 3-Wire Serial-Interface Timing Diagram CS SCLK DATA CLOCKED IN DIN t DS 2% 2% 2% 2% 7% 7% 2% 7% t DH D7 D6 D1 D SWITCHES UPDATED D7 D6 D5 D4 D3 D2 D1 D MSB LSB INPUT DATA BITS Figure 4. A Complete 3-Wire Serial Tramission 3-Wire Serial Interface The MA wire serial interface is SPI/ QSPI/MICROWIRE compatible. An active-low chipselect (CS) input enables the device to receive data for the serial input (DIN). Data is clocked in on the rising edge of the serial-clock (SCLK) signal. A total of 8 bits are needed in each write cycle. The first bit clocked into the MA4585 is the command byte s MSB; the last bit clocked in is the data byte s LSB. The first 5 bits of the command byte are don t care. While shifting data, the device remai in its original configuration. After all 8 bits are clocked into the input shift register, a rising edge on CS latches the data into the MA4585 s internal registers, initiating the device s change of state. Figures 3 and 4 detail the 3-wire protocol, and Table 1 details the command byte format. 2% t CSH t CSW Addressable Serial Interface To program several MA4585s individually using a single µp, connect DIN of each MA4585 together and control CS on each MA4585 separately. To select a particular device, drive the corresponding CS low, clock in the 8-bit command, then drive CS high to execute the command. Typically, only one MA4585 is addressed at a time. Power-Up State The feature a preset power-up state. See Table 1 to determine the power-up state of these devices. 7% Chip Information TRANSISTOR COUNT: 2259 t CSO 1

11 MA4584 MA4585 µp IN 2 OR 3 NO DECODER/ CONTROLLER SERIAL INTERFACE 1nF R L C L 35pF 2-WIRE 3-WIRE SCL CS Test Circuits/Timing Diagrams 3 3 5% t ON 5% t ON ACKNOWLEDGE BIT t R < 2 t F < 2 C L INCLUDES FITURE AND STRAY CAPACITANCE. = IN [R L / (R L + R ON )] -.5 Figure 5. Switching Time MA4584 MA4585 1nF SCL 3 5% ACKNOWLEDGE BIT 8% t R < 2 t F < 2 2-WIRE IN µp NO NO 2 OR 3 DECODER/ CONTROLLER SERIAL INTERFACE R L C L OUT CS 3 5% t BBM 8% C L INCLUDES FITURE AND STRAY CAPACITANCE. = COM [R L / (R L + R ON )] 3-WIRE t BBM Figure 6. Break-Before-Make Interval 11

12 MA4584 MA4585 µp NO_ 2 OR 3 DECODER/ CONTROLLER SERIAL INTERFACE 1nF C L 1pF IS THE MEASURED OLTAGE DUE TO CHARGE TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF. Q = C L Test Circuits/Timing Diagrams (continued) 2-WIRE 3-WIRE SCL CS DIN ACKNOWLEDGE BIT 8-BIT COMMAND ACKNOWLEDGE BIT Figure 7. Charge Injection 1nF MA4584 MA4585 1nF ANALYZER 2/3 ANALYZER COM1 NO N.C. SIGNAL GENERATOR dbm R L NO DECODER/ CONTROLLER R L SIGNAL GENERATOR dbm NO2 DECODER/ CONTROLLER COM2 2/3 5Ω a) OFF-ISOLATION b) CROSSTALK Figure 8. Off-Isolation and Crosstalk Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 12 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.