Low-Voltage, High-Isolation, Dual 2-Channel RF/Video Multiplexer

Transcription

1 9-424; Rev ; /99 Low-oltage, High-Isolation, Dual 2-Channel RF/ideo Multipleer General Description The low-voltage, dual 2-channel multipleer is designed for RF and video signal processing at frequencies up to 2MHz in 5Ω and 75Ω systems. On-chip functio are controlled through either a parallel interface or an SPI /QSPI /MICROWIRE serial interface. Each channel of the is designed using a T switch configuration, euring ecellent high-frequency off-isolation. The has low on-resistance of 6Ω ma, with an on-resistance match across all channels of 4Ω ma. Additionally, on-resistance is flat across the specified signal range (2Ω ma). The offleakage current is under na at TA =, and less than na at TA = +85 C. The operates from single +2.7 to +2 or dual ±2.7 to ±6 supplies. When operating with a positive supply of +5, the inputs maintain TTL/CMOSlevel compatibility. The is available in 2-pin DIP, wide SO, and SSOP packages. RF Switching ideo Signal Routing High-Speed Data Acquisition Automatic Test Equipment Networking Applicatio Pin Configuration Features Low Iertion Loss: < -2.5dB up to MHz High Off-Isolation: -74dB at MHz Low Crosstalk: < -7dB up to MHz 2MHz -.db Signal Bandwidth 2MHz -3dB Signal Bandwidth 6Ω (ma) On-Resistance with ±5 Supplies 4Ω (ma) On-Resistance Matching with ±5 Supplies 2Ω (ma) On-Resistance Flatness with ±5 Supplies +2.7 to +2 Single-Supply Operation ±2.7 to ±6 Dual-Supply Operation Low Power Coumption: <2µW Rail-to-Rail Bidirectional Signal Handling Parallel or SPI/QSPI/MICROWIRE-Compatible Serial Interface >±2k ESD Protection per Method 35.7 TTL/CMOS-Compatible Inputs with L = +5 Ordering Information PART TEMP. RANGE PIN-PACKAGE TOP IEW CAP C to +7 C 2 SSOP COM + NO SER/PAR COM2 NO3 CWP CPP C to +7 C C to +7 C 2 Wide SO 2 Plastic DIP EAP -4 C to +85 C 2 SSOP EWP -4 C to +85 C 2 Wide SO EPP -4 C to +85 C 2 Plastic DIP NO2 6 5 NO4 2/4 7 4 L RS LE/CS 8 9 CONTROL LOGIC 3 2 DIN EN A/SCLK A/DOUT SSOP/SO/DIP SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Maim Integrated Products For free samples & the latest literature: or phone For small orders, phone

2 Dual 2-Channel RF/ideo Multipleer ABSOLUTE MAXIMUM RATINGS (oltages referenced to ) to +3 L to (+ +.3) or 7 (whichever is lower)...-3 to to to +3 NO_, COM_ to (Note )...( -.3) to (+ +.3) 2/4, RS, LE, CS, A/SCLK, A/DOUT, EN, DIN, SER/PAR to to (+ +.3) Continuous Current into Any Terminal...±2mA Peak Current into Any Terminal (pulsed at ms, % duty cycle)...±4ma ESD per Method ±2k Continuous Power Dissipation (T A = +7 C) SSOP (derate 9.mW/ C above +7 C)...727mW Wide SO (derate mw/ C above +7 C)...8mW Plastic DIP (derate.mw/ C above +7 C)...889mW Operating Temperature Ranges C_ P... C to +7 C E_ P...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C Note : oltages on these pi eceeding + or are clamped by internal diodes. Limit forward diode current to maimum current rating. Stresses beyond those listed under Absolute Maimum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Eposure to absolute maimum rating conditio for etended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supplies (+ = L = +4.5 to +5.5, = -4.5 to -5.5, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5, = -5.) (Note 2) PARAMETER SYMBOL CONDITIONS T A MIN TYP MAX UNITS ANALOG SWITCH Analog Signal Range (Note 3) COM_, NO_ + On-Resistance R ON + = 5, = -5, 4 6 NO_ = ±2, I COM_ = 4mA 75 Ω On-Resistance Match Between Channels (Note 4) On-Resistance Flatness (Note 5) R ON R FLAT(ON) + = 5, = 5, NO_ = ±2, I COM_ = 4mA + = 5; = -5; NO_ =,, -; I COM_ = 4mA Ω Ω NO_ Off-Leakage Current (Note 6) I NO_ (OFF) + = 5.5, = -5.5, COM_ = ±4.5, NO_ = 4.5 ± -. - na COM_ Off-Leakage Current (Note 6) I COM_ (OFF) + = 5.5, = -5.5, COM_ = ±4.5, NO_ = 4.5 ± na COM_ On-Leakage Current (Note 6) I COM_ (ON) + = 5.5, = -5.5, COM_ = ±4.5, NO_ = floating na LOGIC INPUTS (2/4, RS, LE/CS, A/SCLK, AO/DOUT, EN, DIN, SER/PAR) Input Logic Threshold High Input Logic Threshold Low Input Threshold Hysteresis Input Current INH INL I IN IN_ = or L µa 2

3 Dual 2-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Dual Supplies (continued) (+ = L = +4.5 to +5.5, = -4.5 to -5.5, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5, = -5.) (Note 2) PARAMETER SYMBOL LOGIC OUTPUT (SERIAL INTERFACE) DOUT Logic Low Output OL DOUT Logic High Output OH SWITCH DYNAMIC CHARACTERISTICS Turn-On Time Turn-Off Time t ON t OFF CONDITIONS I SINK = 3.2mA I SOURCE = -ma NO_ = 3, + = 4.5, = -4.5, Figure NO_ = 3, + = 4.5, = -4.5, Figure T A MIN TYP MAX L UNITS Break-Before-Make Time Delay (Note 3) t BBM NO_ = 3, + = 5.5, = -5.5, Figure 2 8 Charge Injection Q C L =.nf, NO_ =, R S =, Figure 3 5 pc NO_ Off-Capacitance C NO_(OFF) NO_ =, f IN = MHz, Figure 4 2 pf COM_ Off-Capacitance C COM_(OFF) COM_ =, f IN = MHz, Figure 4 4 pf COM_ On-Capacitance C COM_(ON) COM_ =, f IN = MHz, Figure 4 6 pf Off-Isolation (Note 7) ISO NO_ = RMS, f = MHz, all channels off, Figure 5-74 db Channel-to-Channel Crosstalk CT NO_ = RMS, f = MHz, Figure 5-7 db -3dB Bandwidth BW Figure 5 2-channel mode 4-channel mode 2 5 MHz -.db Bandwidth BW Figure 5 2-channel mode 4-channel mode 2 5 MHz PARALLEL-INTERFACE TIMING A_, EN to LE Rise Setup Time t DS 8 A_, EN to LE Rise Hold Time t DH LE Low Pulse Width t L 8 RS Low Pulse Width t RS 8 SERIAL-INTERFACE TIMING Operating Frequency f CLK 6.25 MHz SCLK Pulse Width High t CH 8 SCLK Pulse Width Low t CL 8 DIN to SCLK Rise Setup Time t DS 6 DIN to SCLK Rise Hold Time t DH 3

4 Dual 2-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Dual Supplies (continued) (+ = L = +4.5 to +5.5, = -4.5 to -5.5, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5, = -5.) (Note 2) PARAMETER CS Fall to SCLK Rise Setup Time CS Fall to SCLK Rise Hold Time CS Rise to SCLK Rise Hold Time CS Rise to SCLK Rise Setup Time SCLK Rise to DOUT alid RS Low Pulse Width POWER SUPPLY Power-Supply Range + Supply Current Supply Current L Supply Current SYMBOL t CSS t CSS t CSH t CSS t DO t RS +, L I+ I- I L CONDITIONS C L = 5pF, T A MIN TYP MAX 5 5 UNITS ±2.7 ± = -5.5, + = µa = -5.5, + = µa L = 5.5, all IN_ = or L - 2 µa ELECTRICAL CHARACTERISTICS Single +5 Supply (+ = L = +4.5 to +5.5, =, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5.) (Note 2) PARAMETER ANALOG SWITCH Analog Signal Range (Note 3) On-Resistance On-Resistance Match Between Channels (Note 4) On-Resistance Flatness (Note 5) NO_ Off-Leakage Current (Notes 6, 8) COM_ Off-Leakage Current (Notes 6, 8) COM_ On-Leakage Current (Notes 6, 8) SYMBOL COM_, NO R ON R ON R FLAT(ON) I NO_ (OFF) I COM_ (OFF) I COM_ (ON) CONDITIONS + = 5, NO_ = 3, I COM_ = 4mA + = 5, NO_ = 3, I COM_ = 4mA + = 5; I COM_ = 4mA; NO_ = 2, 3, 4 + = 5.5; COM_ = 4.5, ; NO_ =, = 5.5; COM_ = 4.5, ; NO_ =, = 5.5; COM_ = 4.5 ; NO_ = 4.5,, or floating T A MIN TYP MAX UNITS Ω Ω Ω na na na 4

5 Dual 2-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Single +5 Supply (continued) (+ = L = +4.5 to +5.5, =, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5.) (Note 2) Turn-On Time Turn-Off Time PARAMETER SYMBOL CONDITIONS LOGIC INPUTS (2/4, RS, LE/CS, A/SCLK, AO/DOUT, EN, DIN, SER/PAR Input Logic Threshold High Input Logic Threshold Low Input Threshold Hysteresis Input Current DOUT Logic Low Output INH INL LOGIC OUTPUT (SERIAL INTERFACE) I IN OL DOUT Logic High Output OH SWITCH DYNAMIC CHARACTERISTICS t ON t OFF I SINK = 3.2mA I SOURCE = -ma NO = 3, + = 4.5, Figure NO = 3, + = 4.5, Figure T A MIN TYP MAX L UNITS IN = or L - µa.2.4 Break-Before-Make Time Delay (Note 3) t BBM NO = 3, + = 5.5, Figure 2 2 Charge Injection Q C L =.nf, NO_ = 2.5, R S =, Figure 3 5 pc Off-Isolation ISO NO_ = RMS, f = MHz, all channels off, Figure 5-65 db Channel-to-Channel Crosstalk CT NO_ = RMS, f = MHz, Figure 5-7 db -3dB Bandwidth BW Figure 5 2-channel mode 4-channel mode 75 MHz -.db Bandwidth BW Figure 5 2-channel mode 4-channel mode 7 MHz PARALLEL-INTERFACE TIMING A_, EN to LE Rise Setup Time t DS 8 A_, EN to LE Rise Hold Time t DH LE Low Pulse Width t L 8 RS Low Pulse Width t RS 8 5

6 Dual 2-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Single +5 Supply (continued) (+ = L = +4.5 to +5.5, =, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5.) (Note 2) PARAMETER SERIAL-INTERFACE TIMING Operating Frequency SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time CS Fall to SCLK Rise Setup Time CS Rise to SCLK Rise Hold Time CS Rise to SCLK Rise Setup Time CS Fall to SCLK Rise Hold Time SCLK Rise to DOUT alid RS Low Pulse Width POWER SUPPLY Power-Supply Range SYMBOL f CLK t CH t CL t DS t DH t CSS t CSH t CSS t CSS t DO t RS + CONDITIONS C L = 5pF, MIN TYP MAX L + > T A UNITS + Supply Current L Supply Current I+ I L - += 5.5, IN = or L µa - L = 5.5, all IN_ = or L - 2 µa ELECTRICAL CHARACTERISTICS Single +3 Supply (+ = L = +2.7 to +3.6, =, INH = +2, INL = +.5, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +3.) PARAMETER SYMBOL CONDITIONS T A MIN TYP MAX UNITS ANALOG SWITCH Analog Signal Range (Note 3) COM_, NO + On-Resistance R ON + = 2.7, NO_ =, I COM_ = ma 45 Ω LOGIC INPUT (2/4, RS, LE/CS, A/SCLK, AO/DOUT, EN, DIN, SER/PAR Input Logic Threshold High INH 2. Input Logic Threshold Low INL.5 Input Current I IN IN_ = or L - µa SWITCH DYNAMIC CHARACTERISTICS µa Turn-On Time t ON NO =.5, + = 2.7, 7 Figure 2 Turn-Off Time t OFF NO =.5, + = 2.7, 25 4 Figure 5 Break-Before-Make Time Delay (Note 3) t BBM NO =.5, + = 3.6, Figure

7 Dual 2-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Single +3 Supply (continued) (+ = L = +2.7 to +3.6, =, INH = +2, INL = +.5, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +3.) PARAMETER PARALLEL-INTERFACE TIMING A_, EN to LE Rise Setup Time A_, EN to LE Rise Hold Time LE Low Pulse Width RS Low Pulse Width SERIAL-INTERFACE TIMING Operating Frequency SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time CS Fall to SCLK Rise Setup Time CS Rise to SCLK Rise Hold Time CS Rise to SCLK Rise Setup Time CS Fall to SCLK Rise Hold Time SCLK Rise to DOUT alid RS Low Pulse Width POWER SUPPLY SYMBOL t DS t DH t L t RS f CLK t CH t CL t DS t DH t CSS t CSH t CSS t CSS t DO t RS CONDITIONS C L = 5pF, - + Supply Current I+ + = 3.6, IN = or L µa - L Supply Current I L L = 3.6, all IN = or L - µa T A MIN TYP MAX UNITS MHz Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 3: Guaranteed by design. Note 4: R ON = R ON(MAX) - R ON(MIN). Note 5: Resistance flatness is defined as the difference between the maimum and the minimum value of on-resistance as measured over the specified analog-signal range. Note 6: Leakage parameters are % tested at maimum rated hot temperature and guaranteed by correlation at T A =. Note 7: Off-isolation = 2log [ COM_ / NO_ ], COM_ = output, NO_ = input to off switch. Note 8: Leakage testing for single-supply operation is guaranteed by testing with dual supplies. 7

8 Dual 2-Channel RF/ideo Multipleer (+ = L = +5, = -5, T A =, unless otherwise specified.) RON (Ω) ON-RESISTANCE vs. COM (DUAL SUPPLIES) ± = ±2.5 ± = ±3 ± = ±4 ± = ± COM () toc RON (Ω) ON-RESISTANCE vs. COM (SINGLE SUPPLY) + = = = COM () Typical Operating Characteristics + = +5 + = +9 = + = +2 toc2 RON (Ω) ON-RESISTANCE vs. COM AND TEMPERATURE (DUAL SUPPLIES) T A = +85 C T A = T A = -4 C COM () toc3 RON (Ω) ON-RESISTANCE vs. COM AND TEMPERATURE (SINGLE SUPPLY) T A = +85 C T A = T A = -4 C toc4 LEAKAGE CURRENT (pa) ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE ON-LEAKAGE OFF-LEAKAGE toc5 CHARGE INJECTION (pc) CHARGE INJECTION vs. COM DUAL SUPPLIES toc6 2 5 SINGLE SUPPLY TIME () COM () t ON, t OFF vs. SUPPLY OLTAGE t ON t OFF DUAL SUPPLY OLTAGE (±) toc7 TIME () TEMPERATURE ( C) t ON, t OFF vs. TEMPERATURE t ON t OFF TEMPERATURE ( C) toc8 CURRENT (A) µ µ n n n p p p COM () POWER-SUPPLY CURRENT vs. TEMPERATURE.p TEMPERATURE ( C) I L I+, I- toc9 8

9 Dual 2-Channel RF/ideo Multipleer Typical Operating Characteristics (continued) (+ = L = +5, = -5, T A =, unless otherwise specified.) AMPLITUDE (db) INSERTION LOSS, OFF-ISOLATION, AND CROSSTALK vs. FREQUENCY (DUAL SUPPLIES) R S = 75Ω R L = 6Ω CROSSTALK ON LOSS OFF-ISOLATION -9 k M M M G FREQUENCY (Hz) toc AMPLITUDE (db) INSERTION LOSS, OFF-ISOLATION, AND CROSSTALK vs. FREQUENCY (SINGLE SUPPLY) R S = 75Ω R L = 6Ω CROSSTALK INSERTION LOSS OFF-ISOLATION -9 k M M M G FREQUENCY (MHz) toc2 9

10 Dual 2-Channel RF/ideo Multipleer PIN, 5, NAME COM + NO FUNCTION Ground. Connect to ground plane. See Grounding section. Analog Switch Common Terminal. See Truth Tables. Analog Positive Supply oltage Input Normally Open Analog Input Terminal. See Truth Tables. Pin Description 6 NO2 Normally Open Analog Input Terminal. See Truth Tables /4 RS LE/CS A/SCLK A/DOUT EN DIN L NO4 NO3 COM2 SER/PAR Multipleer Configuration Control. Connect to L to select dual 2-channel mode. Connect to for single 4-channel multipleer operation. See Truth Tables. Active-Low Reset Input. In serial mode, drive RS low to force the latches and shift registers to the power-on reset state and force all switches open. In parallel mode, drive RS low to force the latches to the power-on reset state and force switches open. See Truth Tables. In parallel mode this pin is the traparent Latch Enable. In the serial mode, this pin is the Chip-Select input. See Truth Tables. In parallel mode, A/SCLK is the most significant address bit. If 2/4 is high, A/SCLK is ignored. In the serial mode, A/SCLK is the serial shift clock input. Data is loaded on the rising edge of SCLK. See Truth Tables. In parallel mode, this pin is the least significant address bit. In serial mode, DOUT is the output from the internal 4-bit shift register. DOUT is intended for daisy-chain cascading. DOUT is not three-stated by CS. See Serial Operation. Switch Enable. Drive EN low to force all channels off. Drive high to allow normal multipleer operation. Operates asynchronously in serial mode. In parallel mode, EN is latched when the LE signal is high. Serial Data Input. In serial mode, data is loaded on the rising edge of SCLK. Connect to L or in parallel mode. Logic Supply Input. Powers the DOUT driver and other digital circuitry. L sets both the input threshold levels and the output logic levels. Normally Open Analog Input Terminal. See Truth Tables. Normally Open Analog Input Terminal. See Truth Tables. Analog Negative Supply oltage Input. Connect to for single-supply operation. Analog Switch Common Terminal. See Truth Tables. Interface Select Input. Drive low for parallel data interface operation. Drive high for serial data interface operation and to enable the DOUT driver.

11 Dual 2-Channel RF/ideo Multipleer LE/CS EN + + NO_ COM_ NO_ 3Ω OUT 3pF EN OUT 5% 5% 9% 9% t OFF t ON SWITCH IS TIMED FROM 5% LEEL OF DIGITAL SIGNAL. Figure. Turn-On/Turn-Off Time + LE/CS SER/PAR + NO_ NO_ A NO_ A COM_ OUT OUT 9% 9% 3Ω 3pF t BBM Figure 2. Break-Before-Make Time Delay + LE/CS SER/PAR + NO_ nf µf NO_ EN EN COM_ C L OUT OUT OUT Q = OUT C L OUT IS THE MEASURED OLTAGE DUE TO CHARGE TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF. Figure 3. Charge Injection

12 Dual 2-Channel RF/ideo Multipleer + + NO_ COM_ FLOATING MHz CAPACITANCE ANALYZER + + NO_ COM_ FLOATING MHz CAPACITANCE ANALYZER Figure 4. NO_, COM_ Capacitance + + NO_ 49.9Ω 56Ω 5Ω + - NO_ 24.9Ω 5Ω MEASURE NODE COM_ 56Ω 5Ω MEASURE NODE ALL SIGNALS NORMALIZED TO COM = db.. Figure 5. Off-Isolation, Crosstalk, and Bandwidth t L LE t DS t DH A, A, EN t RS. Parallel Timing Diagram RS NOTE: ALL INPUT SIGNALS ARE SPECIFIED WITH t R AND t F <. TIMING IS MEASURED FROM 5% OF DIGITAL SIGNAL. 2

13 Dual 2-Channel RF/ideo Multipleer CS SCLK t CSS t DS t CH t CL t CSH t DH DIN A A BIT 3 DISABLE t DO DOUT NOTE: ALL INPUT SIGNALS ARE SPECIFIED WITH t R AND t F <. TIMING IS MEASURED FROM 5% OF DIGITAL SIGNAL.. Serial Timing Diagram Detailed Description Logic-Level Tralators The is cotructed of high-frequency T switches, as shown in Figure 8. The logic-level inputs are tralated by amplifier A into a + to logic signal that drives the internal control logic. The internal control logic drives the gates of N-channel MOSFETs N and N2 from + to, turning them fully on or off. The same signal drives inverter A2 (which drives the P- channel MOSFETs P and P2, turning them fully on or off) from + to, and tur the N-channel MOSFET N3 on and off. The logic-level threshold is determined by L and. Switch On Condition When the switch is on, MOSFETs N, N2, P, and P2 are on and MOSFET N3 is off (Figure 8). The signal path is COM_ to NO_, and because both N-channel and P-channel MOSFETs act as pure resistances, it is symmetrical (i.e., signals pass in either direction). The off MOSFET, N3, has no DC conduction, but has a small amount of capacitance to. The s cotruction allows an eceptional 2MHz -3dB bandwidth. Frequency respoe in 75Ω systems is reasonably flat up to 5MHz, with typically 2.5dB of iertion loss. Higher-impedance circuits show even lower attenuation (and vice versa), but slightly lower bandwidth due to the increased effect of the internal and eternal capacitance and the switch s on-resistance. The is optimized for ±5 operation. Using lower supply voltages or a single supply increases switching time, on-resistance (and therefore on-state attenuation), and nonlinearity. Switch Off Condition When the switch is off, MOSFETs N, N2, P, and P2 are off and MOSFET N3 is on (Figure 8). The signal path is through the parasitic off-capacitances of N, N2, P, and P2, but it is shunted to ground by N3. This forms a highpass filter whose eact characteristics are dependent on the source and load impedances. In 75Ω systems, and below MHz, the attenuation eceeds 8dB. This value decreases with increasing frequency and increasing circuit impedances. Eternal capacitance and board layout dominate overall performance. 3

14 Dual 2-Channel RF/ideo Multipleer NO_ N P N2 P2 COM_ N3 + L A_ A CONTROL LOGIC A2 Figure 8. T-Switch Cotruction Applicatio Information Power-Supply Coideratio Overview The cotruction is typical of many CMOS analog switches. It has four supply pi: +,, L, and. + and are used to drive the internal CMOS switches and set the limits of the analog voltage on any switch. Reverse ESD-protection diodes are internally connected between each analog signal pin and both + and. If the voltage on any pin eceeds + or, one of these diodes conducts. During normal operation these reverse-biased ESD diodes leak, forming the only current drawn from and +. irtually all the analog leakage current is through the ESD diodes. Although the ESD diodes on a given signal pin are identical, and therefore fairly well balanced, they are reverse-biased differently. Each is biased by either + or and the analog signal. This mea their leakages vary as the signal varies. The difference in the two diode leakages from the signal path to the + and pi cotitutes the analog signal-path leakage current. All analog leakage current flows to the supply terminals, not to the other switch terminal. This eplai how both sides of a given switch can show leakage currents of either the same or opposite polarity. There is no connection between the analog signal paths and. The analog signal paths coist of an N-channel and P-channel MOSFET with their sources and drai paralleled and their gates driven out of phase to + and by the logic-level tralators. L and power the internal logic and logic-level tralators, and set the input logic thresholds. The logic-level tralators convert the logic levels to switched + and signals to drive the gates of the analog switches. Therefore, the gate-to-source and gate-to-drain impedances are the only connection between the logic supplies and the analog supplies. Bipolar-Supply Operation The operates with bipolar supplies between ±2.7 and ±6. The + and supplies are not required to be symmetrical, but their sum cannot eceed the absolute maimum rating of 3.. Do not connect the + pin to +3 and connect the logic-level input pi to TTL logic-level signals. This eceeds the absolute maimum ratings, and may cause damage to the part and/or eternal circuits. CAUTION: The absolute maimum + to differential voltage is 3.. Typical ±6-olt or 2-olt supplies with ±% tolerances can be as high as 3.2. This voltage can damage the. Even ±5% tolerance supplies may have overshoot or noise spikes that eceed 3.. 4

15 Dual 2-Channel RF/ideo Multipleer Single-Supply Operation The operates from a single supply between +2.7 and +2 when is connected to. Observe all of the precautio listed in the Bipolar- Supply Operation section. Note, however, that these parts are optimized for ±5 operation, and AC and DC characteristics are degraded significantly when operating at less than ±5. As the overall supply voltage (+ to ) is reduced, switching speed, on-resistance, off-isolation, and distortion are degraded (see Typical Operating Characteristics). Single-supply operation also limits signal levels and interferes with grounded signals. When =, AC signals are limited to 3m below. oltages below this level are clipped by the internal ESD-protection diodes, and the parts can be damaged if ecessive current flows. Power Off When power to the is off (i.e., + = and = ), the Absolute Maimum Ratings still apply. This mea that none of the pi can eceed ±.3. oltages beyond ±.3 cause the internal ESDprotection diodes to conduct, with potentially catastrophic coequences. Power-Supply Sequencing When applying power to the, follow this sequence: +,, L, then logic inputs. Apply signals on the analog NO_ and COM_ pi any time after + and are set. Turning on all pi simultaneously is acceptable only if the circuit design guarantees concurrent power-up. The power-down sequence is the opposite of the power-up sequence. That is, the L and logic inputs must go to zero potential before (or simultaneously with) the then + supplies. Always observe the Absolute Maimum Ratings to eure proper operation. Grounding DC Ground Coideratio Satisfactory high-frequency operation requires that careful coideration be given to grounding. For most applicatio, a ground plane is strongly recommended and the pin must connect to it with solid copper. While the + and power-supply pi are common to all switches in a given package, each input pair is separated with ground pi that are not internally connected to each other. This contributes to the overall high-frequency performance by reducing channel-to-channel crosstalk. The digital inputs have voltage thresholds determined by L and. ( does not influence the logic-level threshold.) With L = +5 and =, the threshold is about.6, euring compatibility with TTL- and CMOSlogic drivers. AC Ground and Bypassing A ground plane is mandatory for satisfactory highfrequency operation. Prototyping using hand wiring or wire-wrap boards is not recommended. Make the ground plane solid metal underneath the device, without interruptio. Avoid routing traces under the device itself. For DIP packages, this applies to both sides of a two-sided board. Failure to observe this has a minimal effect on the on characteristics of the switch at high frequencies, but it will degrade the off-isolation and crosstalk. When using the SO package of the on PC boards with a buried ground plane, connect the pi to the ground plane with a separate via. Do not share this via with any other ground path. Providing a ground via on both sides of the SMT land further enhances the off-isolation by lowering the parasitic inductance. With the DIP package, connect the through-holes directly to the buried plane or thermally relieve them, as required, to meet manufacturability requirements. Again, do not use these through-hole pads as the current path for any other components. Bypass the + and pi to the ground plane with surface-mount.µf capacitors. Locate these capacitors as close as possible to the pi on the same side of the board as the device. Do not use feedthroughs or vias for bypass capacitors. If board layout dictates that the bypass capacitors are mounted on the opposite side of the PC board, use short feedthroughs or vias, directly under the + and pi. Use multiple vias if possible. If =, connect it directly to the ground plane with solid copper. Keep all traces short. Signal Routing Keep all signal traces as short as possible. Separate all signal traces from each other, and keep them away from any other traces that could induce interference. Separating the signal traces with generously sized ground wires also helps minimize interference. Routing signals via coaial cable, terminated as close to the as possible, provides the highest isolation. Board Layout IC sockets degrade high-frequency performance and are not recommended if signal bandwidth eceeds 5MHz. Surface-mount parts, having shorter internal lead frames, provide the best high-frequency performance. Keep all bypass capacitors close to the device, and separate all signal leads with ground planes. Use 5

16 Dual 2-Channel RF/ideo Multipleer vias to connect the ground planes on each side of the board. Logic-level signal routing is not critical. Impedance Matching The is intended for use in 75Ω systems, where the inputs are terminated eternal to the IC and the COM terminals are connected to an impedance of 6Ω or higher. The operates in 5Ω and 75Ω systems with terminatio through the IC. However, variatio in on-resistance and on-resistance flatness cause nonlinearities. Crosstalk and Off-Isolation The graphs shown in the Typical Operating Characteristics for crosstalk and off-isolation are taken on adjacent channels. The adjacent channel is the worst-case condition. For eample, NO has the worst off-isolation to COM due to its close proimity. Choosing channels wisely necessitates separating the most seitive channels from the most offeive. Conversely, the above information also applies to the NO3 and NO4 inputs to the COM2 pin. Power-On Reset (POR) The has internal circuitry to guarantee that all switches are off on power-up (POR). This is equivalent to the state resulting from asserting RS during normal operation. Serial Operation The serial mode is activated by driving the SER/PAR input pin to a logic high. The data is then entered using a 4-bit SPI/MICROWIRE write operation. Systems that must write longer data streams can ignore all but the last four bits. Refer to for a detailed diagram of the serial-interface logic. The first bit loaded is A, then A, then an unused bit, followed by the disable bit. There are four flip-flops in the input shift register. The output of the 4th shift register is output on DOUT on the rising edge of A/SCLK. This allows cascading of multiple s using only one chip-select line. For eample, one 6-bit write programs the shift registers of four cascaded s. The data from the shift register is moved to the internal control latches only upon the rising edge of CS, so all four s change state simultaneously. RS has the same effect as the internal power-on reset (POR) signal. The POR state is A = A = and disable =. In serial mode, 2/4 is not used. Connect it to or L; do not leave 2/4 unconnected. Parallel Operation The parallel mode is activated by driving SER/PAR to a logic low. The is then programmed by a latched parallel bus scheme. Refer to for a detailed diagram of the parallel-interface logic. If 2/4 is high, A is disabled and the is configured as a dual -of-2 multipleer. If 2/4 is low, the is configured as a -of-4 multipleer. It is best to hard-wire 2/4 to a known state for the desired mode of operation, or to use a dedicated microcontroller port pin. 6

17 Dual 2-Channel RF/ideo Multipleer Parallel Operation SER/PAR A A EN LE RS 2/4 Truth Tables SWITCH STATES Maintain previous state. All switches off, latches are cleared. Serial Mode. Refer to Serial Operation Truth Table. All switches off. Connect NO to COM Connect NO2 to COM Connect NO3 to COM2 Connect NO4 to COM2 Connect NO to COMand NO3 to COM2 Connect NO2 to COMand NO4 to COM2 = Don t Care. Note: 2/4 is not latched when LE is high. When LE is low, all latches are traparent. A, A and EN are latched. Connect COM to COM2 eternally for -of-4 single-ended operation. Serial Operation SER/PAR CS SCLK DIN EN RS DOUT SWITCH STATES All switches off, latches and shift register are cleared. This is the Power-On Reset (POR) state. High-Z Parallel Mode. Refer to Parallel Operation Truth Table. * * All switches off. Chip uelected. * Input shift register loads one bit from DIN. DOUT updates on rising edge of SCLK. * Contents of shift register traferred to control latches. = Don t Care. *DOUT is delayed by 4 clock cycles from DIN. 7

18 Dual 2-Channel RF/ideo Multipleer Control Bit and 2/4 Logic DISABLE BIT BIT 3 A BIT A BIT 2/4 PIN SWITCH STATES All switches off. Connects NO to COM Connects NO2 to COM Connects NO3 to COM2 Connects NO4 to COM2 Connects NO to COM and NO3 to COM2 Connects NO2 to COM and NO4 to COM2 Truth Tables (continued) = Don't Care. Note: A, A, BIT 3, and DISABLE are the 4 bits latched into the with a MICROWIRE/SPI write, respectively. A is the LSB (first bit clocked in), BIT 3 is not used, and DISABLE is the MSB (last bit clocked in). Chip Information TRANSISTOR COUNT: 853 8

19 Dual 2-Channel RF/ideo Multipleer Package Information PDIPN.EPS SSOP.EPS 9

20 Dual 2-Channel RF/ideo Multipleer Package Information (continued) SOICW.EPS Maim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maim product. No circuit patent licees are implied. Maim reserves the right to change the circuitry and specificatio without notice at any time. 2 Maim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maim Integrated Products Printed USA is a registered trademark of Maim Integrated Products.