Low-Voltage, High-Isolation, Dual 4-Channel RF/Video Multiplexer

Transcription

1 9-425; Rev ; /99 Low-oltage, High-Isolation, Dual 4-Channel RF/ideo Multipleer General Description The low-voltage, dual 4-channel multipleer is designed for RF and video signal processing at frequencies up to 8MHz in 5Ω and 75Ω systems. A fleible digital interface allows control of on-chip functio through either a parallel interface or an SPI / MICROWIRE serial port. Each channel of the is designed using a T switch configuration, euring ecellent high-frequency off-isolation. The has low on-resistance of 6Ω ma, with an on-resistance match across all channels of 4Ω ma. Additionally, on-resistance is flat across the specified signal range (2Ω ma). The offleakage current is under na at T A =, and less than na at T A = +85 C. The operates from single +2.7 to +2 or dual ±2.7 to ±6 supplies. When operating with a +5 supply, the inputs maintain TTL- and CMOS-level compatibility. The is available in 28-pin narrow DIP, wide SO, and space-saving SSOP packages. RF Switching ideo Signal Routing High-Speed Data Acquisition Applicatio Automatic Test Equipment Networking Pin Configuration Features Low Iertion Loss: -2.5dB up to MHz High Off-Isolation: -74dB at MHz Low Crosstalk: -7dB up to MHz 6MHz -.db Signal Bandwidth 8MHz -3dB Signal Bandwidth 6Ω (ma) On-Resistance with ±5 Supplies 4Ω (ma) On-Resistance Matching with ±5 Supplies 2Ω (ma) On-Resistance Flatness with ±5 Supplies +2.7 to +2 Single Supply ±2.7 to ±6 Dual Supplies Low Power Coumption: <2µW Rail-to-Rail, Bidirectional Signal Handling Parallel or SPI/MICROWIRE-Compatible Serial Interface >±2k ESD Protection per Method 35.7 TTL/CMOS-Compatible Inputs with L = +5 Ordering Information TOP IEW COM + NO COM2 - NO5 PART TEMP. RANGE PIN-PACKAGE CAI C to +7 C 28 SSOP CWI C to +7 C 28 Wide SO CPI C to +7 C 28 Narrow Plastic DIP EAI EWI -4 C to +85 C -4 C to +85 C 28 SSOP 28 Wide SO 5 24 NO6 EPI -4 C to +85 C 28 Narrow Plastic DIP NO NO7 NO NO8 NO4 9 L 4/8 8 SER/PAR RS LE/CS 2 3 CONTROL LOGIC 7 6 EN A/DOUT A2/SCLK 4 SSOP/SO/DIP 5 A/DIN SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Maim Integrated Products For free samples & the latest literature: or phone For small orders, phone

2 Dual 4-Channel RF/ideo Multipleer ABSOLUTE MAXIMUM RATINGS (oltages referenced to ) to +3. L to (+ +.3) or 7 (whichever is lower) to to to +3. NO_, COM_ (Note )...(- -.3) to (+ +.3) 4/8, RS, LE/CS, A2/SCLK, A/DIN, A/DOUT, EN, SER/PAR to to (+ +.3) Continuous Current into Any Terminal...±2mA Peak Current into Any Terminal (pulsed at ms, % duty cycle)...±4ma ESD per Method ±2k Continuous Power Dissipation (T A = +7 C) SSOP (derate 9.52mW/ C above +7 C)...762mW Wide SO (derate 2.5mW/ C above +7 C)...W Plastic DIP (derate 4.29mW/ C above +7 C)...4W Operating Temperature Ranges C_ I... C to +7 C E_ I...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C Note : oltages on these pi eceeding + or - are clamped by internal diodes. Limit forward diode current to maimum current rating. Stresses beyond those listed under Absolute Maimum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Eposure to absolute maimum rating conditio for etended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supplies (+ = L = +4.5 to +5.5, - = -4.5 to -5.5, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5, - = -5.) (Note 2) PARAMETER SYMBOL CONDITIONS T A MIN TYP MAX ANALOG SWITCH Analog Signal Range COM_, (Note 3) NO - + On-Resistance R ON + = 5, - = -5, NO_ = ±2, 4 6 I COM_ = 4mA 75 On-Resistance Match Between + = 5, - = 5, NO_ = ±2, 4 R ON Channels (Note 4) I COM_ = 4mA 5 On-Resistance Flatness + = 5; - = -5; NO_ =,, -; R (Note 5) FLAT(ON) I COM_ = ma 3 NO_ Off-Leakage Current + = 5.5, - = -5.5, -. I (Note 6) NO_(OFF) COM_ = ±4.5, NO_ = COM_ Off-Leakage Current + = 5.5, - = -5.5, I (Note 6) COM_(OFF) COM_ = ±4.5, NO_ = COM_ On-Leakage Current + = 5.5, - = -5.5, COM_ = ±4.5, I (Note 6) COM_(ON) NO_ = ±4.5 or floating -2 2 LOGIC INPUTS (4/8, (Pi RS, LE/CS, A2/SCLK, A/DIN, A/DOUT, EN, SER/PAR) Input Logic Threshold High INH Input Logic Threshold Low INL.5.8 Input Threshold Hysteresis.2 Input Current I IN IN_ = or L -.3 LOGIC OUTPUT (SERIAL INTERFACE) DOUT Logic Low Output OL I SINK = 3.2mA.4 DOUT Logic High Output OH I SOURCE = -ma L - UNITS Ω Ω Ω na na na µa 2

3 Dual 4-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Dual Supplies (continued) (+ = L = +4.5 to +5.5, - = -4.5 to -5.5, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5, - = -5.) (Note 2) PARAMETER SYMBOL CONDITIONS T A MIN TYP MAX UNITS SWITCH DYNAMIC CHARAC- CHARACTERISTICS Turn-On Time t ON NO_ = 3, + = 4.5, - = -4.5, Figure 6 Turn-Off Time t OFF NO_ = 3, + = 4.5, - = -4.5, 5 3 Figure 35 Break-Before-Make Time Delay (Note 3) t BBM NO_ = ±3, + = 5.5, - = -5.5, Figure 2 8 Charge Injection Q C L =.nf, NO_ =, R S =, Figure 3 5 pc NO_ Off-Capacitance C NO_(OFF) NO_ =, f IN = MHz, Figure 4 2 pf COM_ Off-Capacitance C COM_(OFF) COM_ =, f IN = MHz, Figure 4 4 pf COM_ On-Capacitance C COM_(ON) COM_ =, f IN = MHz, Figure 4 7 pf Off-Isolation (Note 7) ISO NO_ = RMS, f = MHz, all channels off, Figure 5-74 db Channel-to-Channel Crosstalk CT NO_ = RMS, f = MHz, Figure 5-7 db -3dB Bandwidth BW Figure 5 4-channel mode 8-channel mode 8 4 MHz -.db Bandwidth BW Figure 5 4-channel mode 8-channel mode 6 MHz PARALLEL-INTERFACE MODE INPUT TIM- TIMING A_, EN to LE Rise Setup Time t DS 8 A_, EN to LE Rise Hold Time t DH LE Low Pulse Width t L 8 RS Low Pulse Width t RS 8 SERIAL-INTERFACE PERIPHERAL TIMING INTER- Operating Frequency f CLK 6.25 MHz SCLK Pulse Width High t CH 8 SCLK Pulse Width Low t CL 8 DIN to SCLK Rise Setup Time t DS 6 DIN to SCLK Rise Hold Time t DH CS Fall to SCLK Rise Setup Time t CSS 5 SCLK Rise to DOUT alid t DO C L = 5pF, 5 CS Rise to SCLK Rise Hold Time t CSH CS Rise to SCLK Rise Setup Time t CSS 8 CS Fall to SCLK Rise Hold Time t CSS 8 RS Low Pulse Width t RS 8 3

4 Dual 4-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Dual Supplies (continued) (+ = L = +4.5 to +5.5, - = -4.5 to -5.5, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5, - = -5.) (Note 2) PARAMETER POWER SUPPLY Power-Supply Range + Supply Current - Supply Current L Supply Current SYMBOL +, - L I+ I- I L CONDITIONS + = 5.5, - = = 5.5, - = L = 5.5, all IN_ = or L T A MIN TYP MAX ±2.7 ± UNITS µa µa µa ELECTRICAL CHARACTERISTICS Single +5 Supply (+ = L = +4.5 to +5.5, - =, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5.) (Note 2) PARAMETER SYMBOL CONDITIONS T A MIN TYP MAX UNITS ANALOG SWITCH Analog Signal Range (Note 3) COM_, NO_ + On-Resistance R ON + = 5, NO_ = 3, I COM_ = 4mA Ω On-Resistance Match Between 8 R ON + = 5, NO_ = 3, I COM_ = 4mA Channels (Note 4) Ω On-Resistance Flatness + = 5, I 4 R COM_ = 4mA, (Note 5) FLAT(ON) NO_ = 2, 3, 4 2 Ω NO_ Off Leakage Current (Notes 6, 9) COM_ Off Leakage Current (Notes 6, 9) COM_ On Leakage Current (Notes 6, 9) I NO_(OFF) I COM(OFF) I COM_(ON) + = 5.5; COM_ = 4.5, ; NO_ =, = 5.5; COM_ = 4.5, ; NO_ =, = 5.5; COM_ = 4.5, ; NO_ = 4.5,, or floating LOGIC INPUTS (Pi (4/8, RS, through LE/CS, A2/SCLK, A/DIN, A/DOUT, EN, SER/PAR) Input Logic Threshold High INH Input Logic Threshold Low INL Input Threshold Hysteresis Input Current I IN IN = or L LOGIC OUTPUT (SERIAL INTERFACE) DOUT Logic Low Output OL I SINK = 3.2mA DOUT Logic High Output OH I SOURCE = -ma L -.4 na na na µa 4

5 Dual 4-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Single +5 Supply (continued) (+ = L = +4.5 to +5.5, - =, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5.) (Note 2) PARAMETER SYMBOL SWITCH DYNAMIC CHARAC- CHARACTERISTICS Turn-On Time Turn-Off Time t ON t OFF CONDITIONS NO_ = 3, + = 4.5, Figure NO_ = 3, + = 4.5, Figure T A MIN TYP MAX UNITS Break-Before-Make Time Delay (Note 3) t BBM NO_ = 3, + = 5.5, Figure 2 2 Charge Injection Q C L =.nf, NO_ = 2.5, R S =, Figure 3 5 pc Off-Isolation ISO NO_ = RMS, f = MHz, all channels off, Figure 5-65 db Channel-to-Channel Crosstalk CT NO_ = RMS, f = MHz, Figure 5-7 db -3dB Bandwidth BW Figure 5 4-channel mode 8-channel mode 75 MHz -.db Bandwidth BW Figure 5 4-channel mode 8-channel mode 7 MHz PARALLEL-INTERFACE MODE INPUT TIMING TIM- A_, EN to LE Rise Setup Time t DS 8 A_, EN to LE Rise Hold Time t DH LE Low Pulse Width t L 8 RS Low Pulse Width t RS 8 SERIAL-INTERFACE PERIPHERAL TIMING INTER- Operating Frequency f CLK 6.25 MHz SCLK Pulse Width High t CH 8 SCLK Pulse Width Low t CL 8 DIN to SCLK Rise Setup Time t DS 6 DIN to SCLK Rise Hold Time t DH CS Fall to SCLK Rise Setup Time t CSS 5 CS Fall to SCLK Rise Hold Time t CSS 8 CS Rise to SCLK Rise Hold Time t CSH CS Rise to SCLK Rise Setup Time t CSS 8 SCLK Rise to DOUT alid t DO C L = 5pF, 5 RS Low Pulse Width t RS 8 5

6 Dual 4-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Single +5 Supply (continued) (+ = L = +4.5 to +5.5, - =, INH = +2.4, INL = +.8, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +5.) (Note 2) PARAMETER POWER SUPPLY SYMBOL CONDITIONS + = 5.5, IN = or L L = 5.5, all IN_ = or L T A MIN TYP MAX Power-Supply Range L + > Supply Current L Supply Current + I+ I L UNITS µa µa ELECTRICAL CHARACTERISTICS Single +3 Supply (+ = L = +2.7 to +3.6, - =, INH = +2, INL = +.5, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +3..) PARAMETER ANALOG SWITCH Analog Signal Range On-Resistance Turn-Off Time COM_, NO_ R ON t OFF t BBM t DS t DH t L CONDITIONS + = 2.7, NO_ =, I COM_ = ma LOGIC INPUTS (Pi (4/8, RS, through LE/CS, A2/SCLK, A/DIN, A/DOUT, EN, SER/PAR) Input Logic Threshold High INH Input Logic Threshold Low INL Input Current I IN IN_ = or L SWITCH DYNAMIC CHARAC- CHARACTERISTICS Turn-On Time Operating Frequency SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time RS Low Pulse Width SYMBOL t ON t RS f CLK t CH t CL t DS t DH t RS NO_ =.5, + = 2.7, Figure NO_ =.5, + = 2.7, Figure NO_ =.5, + = 3.6, Figure 2 T A MIN TYP MAX UNITS Ω µa Break-Before-Make Time Delay (Note 3) PARALLEL-INTERFACE MODE INPUT TIMING TIM- A_, EN to LE Rise Setup Time A_, EN to LE Rise Hold Time LE Low Pulse Width RS Low Pulse Width SERIAL-INTERFACE PERIPHERAL TIMING INTER- MHz 6

7 Dual 4-Channel RF/ideo Multipleer ELECTRICAL CHARACTERISTICS Single +3 Supply (continued) (+ = L = +2.7 to +3.6, - =, INH = +2, INL = +.5, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =, + = L = +3..) PARAMETER CS Fall to SCLK Rise Setup Time CS Rise to SCLK Rise Hold Time CS Rise to SCLK Rise Setup Time CS Fall to SCLK Rise Hold Time SCLK Rise to DOUT alid POWER SUPPLY + Supply Current L Supply Current SYMBOL t CSS t CSH t CSS t CSS t DO I+ I L CONDITIONS C L = 5pF, T A MIN TYP MAX = 3.6, IN = or L - L = 3.6, all IN = or L - Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 3: Guaranteed by design. Note 4: R ON = R ON(MAX) - R ON(MIN). Note 5: Resistance flatness is defined as the difference between the maimum and the minimum value of on-resistance as measured over the specified analog-signal range. Note 6: Leakage parameters are % tested at maimum rated hot temperature and guaranteed by correlation at T A =. Note 7: Off isolation = 2log [ COM_ / ( NC_ or NO_ )], COM_ = output, NC_ or NO_ = input to off switch. Note 8: Between any two switches. Note 9: Leakage testing for single-supply operation is guaranteed by testing with dual supplies. 25 UNITS µa µa 7

8 Dual 4-Channel RF/ideo Multipleer (+ = L = +5, - = -5, T A =, unless otherwise noted.) ON-RESISTANCE (Ω) ON-RESISTANCE vs. COM (DUAL SUPPLIES) ±2.5 ±3 ±4 ±5 ± COM () - Typical Operating Characteristics ON-RESISTANCE (Ω) ON-RESISTANCE vs. COM (SINGLE SUPPLY) + = = = = COM () - = + = +9 + = +2-2 ON-RESISTANCE (Ω) ON-RESISTANCE vs. COM AND TEMPERATURE (DUAL SUPPLIES) T A = +85 C T A = +5 C T A = T A = C T A = -4 C -3 ON-RESISTANCE (Ω) ON-RESISTANCE vs. COM AND TEMPERATURE (SINGLE SUPPLY) - = T A = +85 C T A = +5 C T A = T A = C T A = -4 C COM () COM () LEAKAGE CURRENT (A) n n p p p ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE ON-LEAKAGE OFF-LEAKAGE -5 CHARGE INJECTION (pc) CHARGE INJECTION vs. COM DUAL SUPPLIES SINGLE SUPPLY -6.p TEMPERATURE ( C) COM () 8

9 Dual 4-Channel RF/ideo Multipleer Typical Operating Characteristics (continued) (+ = L = +5, - = -5, T A =, unless otherwise noted.) ton, toff () ON/OFF TIME vs. SUPPLY OLTAGE t OFF t ON -7 ton, toff () ON/OFF TIME vs. TEMPERATURE t ON t OFF -8 SUPPLY CURRENT (A) µ µ n n n p p SUPPLY CURRENT vs. TEMPERATURE I+ I- I L SUPPLY OLTAGE (±) TEMPERATURE ( C) p TEMPERATURE ( C) AMPLITUDE (db) INSERTION LOSS, OFF-ISOLATION, AND CROSSTALK vs. FREQUENCY (DUAL SUPPLIES) R S = 75Ω R L = 6Ω CROSSTALK ON LOSS OFF-ISOLATION -9 k M M M G FREQUENCY (Hz) - AMPLITUDE (db) INSERTION LOSS, OFF-ISOLATION, AND CROSSTALK vs. FREQUENCY (SINGLE SUPPLY) R S = 75Ω R L = 6Ω CROSSTALK INSERTION LOSS OFF-ISOLATION -9 k M M M G FREQUENCY (Hz) - 9

10 Dual 4-Channel RF/ideo Multipleer PIN, 5, 7, 9, 2, 23, NAME COM + Analog Switch Common Terminal. See Truth Table. Analog Positive Supply oltage Input FUNCTION Ground. Connect all ground pi to a ground plane. See Grounding section. Pin Description 4 NO Normally Open Analog Input Terminal. See Truth Tables. 6 NO2 Normally Open Analog Input Terminal. See Truth Tables. 8 NO3 Normally Open Analog Input Terminal. See Truth Tables. NO4 Normally Open Analog Input Terminal. See Truth Tables. 4/8 Multipleer Configuration Control. Connect to L to select dual 2-channel mode. Connect to for single 4-channel multipleer operation. See Truth Tables. 2 RS Active-Low Reset Input. In serial mode, drive RS low to force the latches and shift registers to the poweron reset state and force all switches open. In parallel mode, drive RS low to force the latches to the poweron reset state and force all switches open. See Truth Tables. 3 LE/CS In parallel mode, this pin is the traparent Latch Enable. In the serial mode, this pin is the Chip-Select Input. See Truth Tables. 4 A2/SCLK Most Significant Address Bit in parallel mode with 4/8 low. If 4/8 pin is high, this pin is ignored. In the serial mode, this is the Serial Shift Clock Input. Data is loaded on the rising edge of SCLK. See Truth Tables. 5 A/DIN Address Input in the parallel mode. Serial Data Input in serial mode. In serial mode, data is loaded on SCLK s rising edge. 6 A/DOUT Least Significant Address Input in the parallel mode. In the serial mode this is an output from the internal 4-bit shift register. DOUT is intended for daisy-chain cascading. DOUT is not three-stated by CS. See Serial Operation. 7 EN Switch Enable. Drive EN low to force all channels off. Drive high to allow normal multipleer operation. Operates asynchronously in serial mode. In parallel mode, EN is latched when LE signal is high. 8 SER/PAR Interface Select Input. Drive low for parallel data interface operation. Drive high for serial data interface operation and to enable the DOUT driver. 9 L Logic Supply Input. Powers the DOUT driver and other digital circuitry. L sets both the digital input and output logic levels. 2 NO8 Normally Open Analog Input Terminal. See Truth Tables. 22 NO7 Normally Open Analog Input Terminal. See Truth Tables. 24 NO6 Normally Open Analog Input Terminal. See Truth Tables. 26 NO5 Normally Open Analog Input Terminal. See Truth Tables Analog Negative Supply oltage Input. Connect to ground plane for single-supply operation. 28 COM2 Analog Switch Common Terminal. See Truth Tables.

11 Dual 4-Channel RF/ideo Multipleer LE/CS EN + + NO_ COM_ NO_ 3Ω OUT 3pF EN OUT 5% 5% 9% 9% - t OFF t ON - Figure. Turn-On/Turn-Off Time + LE/CS SER/PAR + NO_ NO_ NO_ A A COM_ OUT OUT 9% - 3Ω 3pF t BBM - Figure 2. Break-Before-Make Time Delay + LE/CS SER/PAR + NO_ nf µf NO_ EN EN COM_ C L OUT OUT OUT - Q = OUT C L - OUT IS THE MEASURED OLTAGE DUE TO CHARGE TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF. Figure 3. Charge Injection

12 Dual 4-Channel RF/ideo Multipleer + + NO_ COM_ - FLOATING MHz CAPACITANCE ANALYZER NO_ COM_ FLOATING MHz CAPACITANCE ANALYZER - Figure 4. NO_, COM_ Capacitance + + NO_ 49.9Ω 56Ω 5Ω + - NO_ 24.9Ω 5Ω MEASURE NODE - - COM_ 56Ω 5Ω MEASURE NODE ALL SIGNALS NORMALIZED TO COM = db. Figure 5. Off-Isolation, Crosstalk, and Bandwidth t L LE t DS t DH A, A, A2, EN t RS RS. Parallel Timing Diagram NOTE: ALL INPUT SIGNALS ARE SPECIFIED WITH t R AND t F <. TIMING IS MEASURED FROM 5% OF DIGITAL SIGNAL. 2

13 Dual 4-Channel RF/ideo Multipleer CS SCLK t CSS t DS t CH t CL t CSH t DH DIN A A A2 DISABLE t DO DOUT NOTE: ALL INPUT SIGNALS ARE SPECIFIED WITH t R AND t F <. TIMING IS MEASURED FROM 5% OF DIGITAL SIGNAL.. Serial Timing Diagram Detailed Description Logic-Level Tralators The is cotructed of high-frequency T switches, as shown in Figure 8. The logic-level inputs are tralated by amplifier A into a + to - logic signal that drives amplifier A2. Amplifier A2 drives the gates of N-channel MOSFETs N and N2 from + to -, turning them fully on or off. The same signal drives inverter A3 (which drives the P-channel MOSFETs P and P2, turning them fully on or off) from + to -, and tur the N-channel MOSFET N3 on and off. The logiclevel threshold is determined by L and. Switch On Condition When the switch is on, MOSFETs N, N2, P, and P2 are on and MOSFET N3 is off (Figure 8). The signal path is COM_ to NO_, and because both N-channel and P-channel MOSFETs act as pure resistances, it is symmetrical (i.e., signals may pass in either direction). The off MOSFET, N3, has no DC conduction, but has a small amount of capacitance to. The four on MOSFETs also have capacitance to ground that, together with the series resistance, forms a lowpass filter. All of these capacitances are distributed evenly along the series resistance, so they act as a tramission line rather than a simple R-C filter. The s cotruction allows an eceptional 8MHz bandwidth when the switches are on. COM_ + CC INPUT - NORMALLY OPEN SWITCH CONSTRUCTION N A A2 A3 Figure 8. T-Switch Cotruction Typical attenuation in 75Ω systems is 2.5dB and is reasonably flat up to 5MHz. Higher-impedance circuits show even lower attenuation (and vice versa), but slightly lower bandwidth due to the increased effect of the internal and eternal capacitance and the switch s internal resistance. P N3 ESD DIODES ON, NO_, AND COM_ N2 P2 + + NO 3

14 Dual 4-Channel RF/ideo Multipleer The is optimized for ±5 operation. Using lower supply voltages or a single supply increases switching time, on-resistance (and therefore on-state attenuation), and nonlinearity. Switch Off Condition When the switch is off, MOSFETs N, N2, P, and P2 are off and MOSFET N3 is on (Figure 8). The signal path is through the parasitic off-capacitances of the series MOSFETs, but it is shunted to ground by N3. This forms a highpass filter whose eact characteristics are dependent on the source and load impedances. In 75Ω systems, and below MHz, the attenuation can eceed 8dB. This value decreases with increasing frequency and increasing circuit impedances. Eternal capacitance and board layout have a major role in determining overall performance. Applicatio Information Power-Supply Coideratio Overview The cotruction is typical of many CMOS analog switches. It has four supply pi: +, -, L, and. + and - are used to drive the internal CMOS switches and set the limits of the analog voltage on any switch. Reverse ESD-protection diodes are internally connected between each analog signal pin and both + and -. If the voltage on any pin eceeds + or -, one of these diodes will conduct. During normal operation these reverse-biased ESD diodes leak, forming the only current drawn from - and +. irtually all the analog leakage current is through the ESD diodes. Although the ESD diodes on a given signal pin are identical, and therefore fairly well balanced, they are reverse-biased differently. Each is biased by either + or - and the analog signal. This mea their leakages vary as the signal varies. The difference in the two diode leakages from the signal path to the + and - pi cotitutes the analog signal-path leakage current. All analog leakage current flows to the supply terminals, not to the other switch terminal. This eplai how both sides of a given switch can show leakage currents of either the same or opposite polarity. There is no connection between the analog signal paths and. The analog signal paths coist of an N-channel and P-channel MOSFET with their sources and drai paralleled and their gates driven out of phase with + and - by the logic-level tralators. L and power the internal logic and logic-level tralators, and set the input logic thresholds. The logic-level tralators convert the logic levels to switched + and - signals to drive the gates of the analog switches. This drive signal is the only connection between the logic supplies and the analog supplies. Bipolar-Supply Operation The operates with bipolar supplies between ±2.7 and ±6. The + and - supplies are not required to be symmetrical, but their sum cannot eceed the absolute maimum rating of 3.. Do not connect the + pin to +3 and connect the logic-level input pi to +5 logic-level signals. This level eceeds the absolute maimum ratings, and may cause damage to the part and/or eternal circuits. CAUTION: The absolute maimum + to - differential voltage is 3.. Typical ±6-olt or 2-olt supplies with ±% tolerances can be as high as 3.2. This voltage can damage the. Even ±5% tolerance supplies may have overshoot or noise spikes that eceed 3.. Single-Supply Operation The operates from a single supply between +2.7 and +2 when - is connected to. Observe all of the precautio listed in the Bipolar- Supply Operation section. Note, however, that these parts are optimized for ±5 operation, and AC and DC characteristics are degraded significantly when operating at less than ±5. As the overall supply voltage (+ to -) is reduced, switching speed, on-resistance, offisolation, and distortion are degraded (see Typical Operating Characteristics). Single-supply operation also limits signal levels and interferes with grounded signals. When - =, AC signals are limited to -.3. oltages below -.3 can be clipped by the internal ESD-protection diodes, and the parts can be damaged if ecessive current flows. Power Off When power to the is off (i.e., + = and - = ), the Absolute Maimum Ratings still apply. This mea that none of the pi can eceed ±.3. oltages beyond ±.3 cause the internal ESDprotection diodes to conduct, with potentially catastrophic coequences. Power-Supply Sequencing When applying power to the, follow this sequence: +, - (if biased to potential other than ground), L, then logic inputs. Apply signals on the analog NO_ and COM_ pi any time after +, -, and voltages are set. Turning on all pi simultaneously is acceptable only if the circuit design guarantees concurrent power-up. 4

15 Dual 4-Channel RF/ideo Multipleer The power-down sequence is the opposite of the power-up sequence. That is, the L and logic inputs must go to zero potential before (or simultaneously with) the - then + supplies. The Absolute Maimum Ratings must always be observed in order to eure proper operation. Grounding DC Ground Coideratio Satisfactory high-frequency operation requires that careful coideration be given to grounding. For most applicatio, a ground plane is strongly recommended, and all pi must connect to it with solid copper. While the + and - power-supply pi are common to all switches in a given package, each input is separated with ground pi that are not internally connected to each other. This contributes to the overall high-frequency performance by reducing channel-to-channel crosstalk. All the pi have ESD diodes to + and -. In systems that have separate digital and analog (signal) grounds, connect all pi to analog signal ground. Preserving a good signal ground is much more important than preserving a digital ground. Ground current is only a few nanoamperes. The digital inputs have voltage thresholds determined by L and (- does not influence the logic-level threshold). With +5 applied to L, the threshold is about.6, euring compatibility with TTL- and CMOS-logic drivers. AC Ground and Bypassing A ground plane is mandatory for satisfactory highfrequency operation. Prototyping using hand wiring or wire-wrap boards is not recommended. Connect all pi to the ground plane with solid copper. (The pi etend the high-frequency ground through the package wire-frame, into the silicon itself, thus improving isolation.) Make the ground plane solid metal underneath the device, without interruptio. There should be no traces under the device itself. For DIP packages, this applies to both sides of a two-sided board. Failure to observe this has a minimal effect on the on characteristics of the switch at high frequencies, but will degrade the off-isolation and crosstalk. When using the s SO package on PC boards with a buried ground plane, connect each pin to the ground plane with a separate via. Do not share this via with any other ground path. Providing a ground via on both sides of the SMT land further enhances the off-isolation by lowering the parasitic inductance. The DIP package can have the through-holes directly tied to the buried plane, or thermally relieved as required to meet manufacturability requirements. Again, do not use the throughhole pads as the current path for any other components. Bypass all + and - pi to the ground plane with surface-mount.µf capacitors. Locate these capacitors as close as possible to the pi on the same side of the board as the device. Do not use feedthroughs or vias for bypass capacitors. If board layout dictates that the bypass capacitors are mounted on the opposite side of the PC board, use short feedthroughs or vias, directly under the + and - pi. Use multiple vias if possible. If - is, connect it directly to the ground plane with solid copper. Keep all traces short. Signal Routing Keep all signal leads as short as possible. Separate all signal leads from each other, and keep them away from any other traces that could induce interference. Separating the signal traces with generously sized ground wires also helps minimize interference. Routing signals via coaial cable, terminated as close to the as possible, provides the highest isolation. Board Layout IC sockets degrade high-frequency performance and should not be used if signal bandwidth eceeds 5MHz. Surface-mount parts, having shorter internal lead frames, provide the best high-frequency performance. Keep all bypass capacitors close to the device, and separate all signal leads with ground planes. Such grounds tend to be wedge-shaped as they get closer to the device. Use vias to connect the ground planes on each side of the board, and place the vias in the ape of the wedge-shaped grounds that separate signal leads. Logic-level signal lead placement is not critical. Impedance Matching The is intended for use in 75Ω systems, where the inputs are terminated eternal to the IC and the COM terminals see an impedance of 6Ω or higher. The can operate in 5Ω and 75Ω systems with terminatio through the IC. However, variatio in R ON and R ON flatness cause nonlinearities. Crosstalk and Off-Isolation The graphs shown in Typical Operating Characteristics for crosstalk and off-isolation are taken on adjacent channels. The adjacent channel is the worst-case condition. For eample, NO has the worst off-isolation to COM due to their proimity. Furthermore, NO has the most crosstalk to NO2, and the least crosstalk to NO4. Choosing channels wisely necessitates separating the most seitive channels from the most offeive. Conversely, the above information also applies to the NO5 NO8 inputs to the COM2 pin. 5

16 Dual 4-Channel RF/ideo Multipleer Power-On Reset (POR) The has internal circuitry to guarantee a known state on power-up. In the default state, A = A = A2 =, disable =, and all switches are off. This state is equivalent to asserting RS during normal operation. Serial Operation The serial mode is activated by driving the SER/PAR input pin to a logic high. The data is then entered using a normal SPI/MICROWIRE write operation. Refer to Figure 7 for a detailed diagram of the serial-interface logic. There are four flip-flops in the shift register, with the output of the fourth shift register being output on the DOUT pin. Note: DOUT changes on the rising edge of SCLK. This allows cascading of multiple s using only one chip-select line. For eample, one 6-bit write could load the shift registers of four cascaded s. The data from the shift register is moved to the internal control latches only upon the rising edge of CS, so all four s change state simultaneously. Parallel Operation The parallel mode is activated by driving SER/PAR to a logic low. The is programmed by a latched parallel bus scheme. Refer to for a detailed diagram of the parallel-interface logic. Note that 4/8 is not latched. It is best to hard-wire 4/8 to a known state for the desired mode of operation, or to use a dedicated microcontroller port pin. Parallel Operation Truth Tables SER/PAR A2 A A EN LE RS 4/8 SWITCH STATES Maintain previous state. All switches off, latches are cleared. Serial Mode. Refer to Serial Operation Truth Table. All switches off. Connects NO to COM Connects NO2 to COM Connects NO3 to COM Connects NO4 to COM Connects NO5 to COM2 Connects NO6 to COM2 Connects NO7 to COM2 Connects NO8 to COM2 Connect NO to COM and NO5 to COM2 Connect NO2 to COM and NO6 to COM2 Connect NO3 to COM and NO7 to COM2 Connect NO4 to COM and NO8 to COM2 = Don t Care Note: 4/8 is not latched when LE is high. When LE is low, all latches are traparent. A2, A, A, and EN are latched. Connect COM to COM2 eternally for -of-8 single-ended operation. 6

17 Dual 4-Channel RF/ideo Multipleer Serial Operation SER/PAR CS SCLK DIN EN RS DOUT High-Z * * * * * Truth Tables (continued) ON SWITCHES/STATES All switches off. Latches and shift register are cleared. This is the power-on reset (POR) state. Parallel Mode. Refer to Parallel Operation Truth Table. All switches off. Chip uelected. Input shift register loads one bit from DIN. DOUT updates on SCLK s rising edge. Input shift register loads one bit from DIN. DOUT updates on SCLK s rising edge. Contents of shift register traferred to control latches. = Don t Care *DOUT is delayed by 4 clock cycles from DIN. Control Bit and 4/8 Logic DISABLE BIT A2 BIT A BIT A BIT 4/8 PIN All switches off. Connect NO to COM Connect NO2 to COM Connect NO3 to COM Connect NO4 to COM Connect NO5 to COM2 Connect NO6 to COM2 Connect NO7 to COM2 Connect NO8 to COM2 ON SWITCHES/STATES Connect NO to COM and NO5 to COM2 Connect NO2 to COM and NO6 to COM2 Connect NO3 to COM2 and NO7 to COM2 Connect NO4 to COM2 and NO8 to COM2 = Don t Care Note: DISABLE, A2, A, and A are the 4 bits latched into the with a MICROWIRE/SPI write. A is the LSB (first bit in time). DISABLE is the MSB (last bit in time). 7

18 Dual 4-Channel RF/ideo Multipleer Chip Information TRANSISTOR COUNT: 33 Package Information 28LNPDIP.EPS 8

19 Dual 4-Channel RF/ideo Multipleer Package Information (continued) SOICW.EPS 9

20 Dual 4-Channel RF/ideo Multipleer Package Information (continued) SSOP.EPS Maim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maim product. No circuit patent licees are implied. Maim reserves the right to change the circuitry and specificatio without notice at any time. 2 Maim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maim Integrated Products Printed USA is a registered trademark of Maim Integrated Products.