Quad, Rail-to-Rail, Fault-Protected, SPDT Analog Switch

Transcription

1 ; Rev 1; 1/99 Quad, Rail-to-Rail, Fault-Protected, General Description The quad, single-pole/double-throw (SPDT), fault-protected analog switch is pin-compatible with the industry-standard MAX333 and MAX333A. The features fault-protected inputs and Rail-to-Rail signal handling. The normally open (NO_ ) and normally closed ( ) terminals are protected from overvoltage faults up to ±25 with power on and up to ±4 with power off. During a fault condition, NO_ and become high impedance with only nanoamperes of leakage current flowing to the source. In addition, the output () clamps to the appropriate polarity supply rail and provides up to ±1mA of load current. This eures unambiguous rail-to-rail outputs when a fault occurs. The operates from dual ±4.5 to ±18 power supplies or a single +9 to +36 supply. All digital inputs have +.8 and +2.4 logic thresholds, euring both TTL and CMOS logic compatibility when using ±15 supplies or a +12 supply. On-resistance is 175Ω max and is matched between switches to 1Ω max. The offleakage current is only.5 at TA = and 1 at TA = +85 C. Redundant/Backup Systems Test Equipment Communicatio Systems Industrial and Process Control INPUTS 1 2 OSC IN 3 4 FLYING CAPACITOR LEEL TRANSLATOR (2-CHANNEL) Applicatio Portable Itruments Data-Acquisition Systems Avionics Systems Typical Operating Circuit OUTPUTS Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Pg Features Rail-to-Rail Signal Handling ±4 Fault Protection with Power Off ±25 Fault Protection with ±15 Supplies All Switches Off with Power Off No Power-Supply Sequencing Required During Power-Up or Power-Down Output Clamped to Appropriate Supply oltage During Fault Condition No Traition Glitch 1kΩ (typ) Output Clamp Resistance During Overvoltage 175Ω (max) Signal Paths with ±15 Supplies 2 (typ) Fault Respoe Time ±4.5 to ±18 Dual Supplies +9 to +36 Single Supply Pin-Compatible with Industry-Standard MAX333/MAX333A TTL/CMOS-Compatible Logic Inputs with ±15 or Single +9 to +15 Supplies PART TEMP. RANGE PIN-PACKAGE CAP CWP C to +7 C C to +7 C 2 SSOP 2 Wide SO Ordering Information continued at end of data sheet. TOP IEW IN1 1 NO1 2 COM1 3 NC1 4-5 GND 6 NC2 7 COM2 8 NO2 9 IN2 1 Ordering Information Pin Configuration/ Functional Diagram 2 IN4 19 NO4 18 COM4 17 NC N.C. 14 NC3 13 COM3 12 NO3 11 IN3 SSOP/SO/DIP/CERDIP SWITCHES ARE SHOWN WITH LOGIC "" INPUT N.C. = NOT INTERNALLY CONNECTED Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS oltages Referenced to GND to to +.3 to to +44., IN_ (Note 1)... (- -.3) to ( +.3), NO_ (Note 2)...( - 4) to (- + 4), NO_ to...-4 to +4, NO_ Overvoltage with Switch Power On (supplies at ±15)...-3 to +3, NO_ Overvoltage with Switch Power Off...-4 to +4 Continuous Current into Any Terminal...±3mA Peak Current into Any Terminal (pulsed at 1ms,1% duty cycle)...±5ma Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supplies Continuous Power Dissipation (T A = +7 C) 2-Pin SSOP (derate 1.53mW/ C above +7 C)...842mW 2-Pin Wide SO (derate 1.mW/ C above +7 C).. 8mW 2-Pin Plastic DIP (derate 11.11mW/ C above +7 C) 889mW 2-Pin CERDIP (derate 11.11mW/ C above +7 C)...889mW Operating Temperature Ranges C... C to +7 C E...-4 C to +85 C M C to +125 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Note 1: and IN_ pi are not fault protected. Signals on or IN_ exceeding or - are clamped by internal diodes. Limit forward diode current to maximum current rating. Note 2: and NO_ pi are fault protected. Signals on or NO_ exceeding -25 to +25 may damage the device. These limits apply with power applied to or -. The limit is ±4 with = - =. ( = +15, - = -15, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) PARAMETER ANALOG SWITCH Fault-Free Analog Signal Range (Note 2) SYMBOL NO_, CONDITIONS = +15, - = -15, NO _ or = ±15 T A MIN TYP MAX to NO_ or to NO _ or NC _ = ±1, R ON C, E 2 On-Resistance I COM _ = 1mA M 25 Ω to NO_ or to 1 6 NO _ or NC _ = ±1, On-Resistance Match Between R ON C, E 1 I COM _ = 1mA Channels (Note 4) M 15 Ω On-Resistance Flatness = +5,, -5, I = 1mA 4 Ω NO_ or Off-Leakage I NO_(OFF), NO _ or NC _ = ±14, C, E -1 1 Current (Note 5) I (OFF) COM _ = 14 M On-Leakage Current = ±14, I (ON) C, E -2 2 (Note 5) NO_ or = ±14 or floating M -4 4 FAULT Fault-Protected Analog Signal Applies with power on NO_, Range (Note 2) Applies with power off Output Leakage Current, NO_ or = ±25, I C, E -2 2 Supplies On no connection to ON channel M NO_ or Off Input Leakage NO _ or NC _ = ±25, I NO_, I C, E -2 2 Current, Supplies On COM _ = 1 M -1 1 ± ± UNITS 2

3 ELECTRICAL CHARACTERISTICS Dual Supplies (continued) ( = +15, - = -15, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) PARAMETER SYMBOL CONDITIONS T A MIN TYP MAX UNITS NO_ or Input Leakage I NO_, I NO_ or = ±4, C, E -2 2 Current, Supplies Off =, - = M -1 1 On-Clamp Output NO_ or = Current, Supplies On I NO_ or = -25 ma On-Clamp Output R Resistance, Supplies On NO_ or NC = ±25 3 kω ±Fault Output Clamp Turn-On R L = 1kΩ, Delay Time (Note 6) NO_ or = ±25 2 ±Fault Recovery Time R L = 1kΩ, (Note 6) NO_ or = ± µs LOGIC INPUT IN_ Input Logic Threshold High IN_H 2.4 IN_ Input Logic Threshold Low IN_L.8 IN_ Input Current Logic High or I IN_H, I IN_L IN_ = +.8 or +2.4 Low -5 5 SWITCH DYNAMIC CHARACTERISTICS Turn-On Time Turn-Off Time Break-Before-Make Time Delay Charge Injection (Note 6) NO_ or Off-Capacitance On-Capacitance Off-Isolation (Note 7) Channel-to-Channel Crosstalk (Note 8) POWER SUPPLY Power-Supply Range Supply Current - Supply Current GND Supply Current t BBM Q C N_(OFF) C (ON) ISO CT, - I+ I- I GND = ±1, R L = 2kΩ; Figure 2 NO_ = ±1, R L = 2kΩ; Figure 2 = ±1, R L = 1kΩ; Figure 3 C L = 1pF, = ; Figure 4 f = 1MHz; Figure 5 f = 1MHz; Figure 5 R L = 5Ω, C L = 15pF, N_ = 1 RMS, f = 1MHz; Figure 6 R L = 5Ω, C L = 15pF, N_ = 1 RMS, f = 1MHz; Figure 6 All IN_ = or +5, NO_ = = All IN_ = or +5, NO_ = = All IN_ = or +5, NO_ = = 1 25 C, E 4 M C, E 3 M pc pf pf db db ±4.5 ±

4 ELECTRICAL CHARACTERISTICS Single Supply ( = +12, - =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) PARAMETER ANALOG SWITCH Fault-Free Analog Signal Range (Note 2) SYMBOL NO_, CONDITIONS = +12, - =, NO _ or = +12 or = +12, to NO_, to R NO _ or NC _ = +1, C, E 45 On-Resistance ON I COM _ = 1mA M 525 Ω -NO_ On-Resistance = +12, 4 1 Match Between Channels R ON NO _ or NC _ = +1, C, E 2 Ω (Note 4) I COM _ = 1mA M 3 = +12, NO_ or Off-Leakage I NO_(OFF), = +1, +1, C, E -1 1 Current (Notes 5, 9) I (OFF) NO_ or = +1, +1 M -2 2 = +12, On-Leakage Current I (ON) = +1, C, E -2 2 (Notes 5, 9) NO_ or = +1 or floating M -4 4 FAULT Fault-Protected Analog Signal Applies with power on NO_, Range (Note 2) Applies with power off NO_ or = ±25, -1 1 Output Leakage Current, I = +12, C, E -2 2 Supply On (Note 9) no connection to ON channel M -1 1 NO_ or = ±25, -2 2 NO_ or Off Input Leakage I NO_, I =, C, E -2 2 Current, Supply On (Note 9) = +12 M NO_ or Input Leakage NO_ or = ±4, I NO_, I C, E -2 2 Current, Supply Off (Note 9) =, - = M -1 1 On-Clamp Output Current, Supply On On-Clamp Output Resistance, Supply On LOGIC INPUT IN_ Input Logic Threshold High IN_ Input Logic Threshold Low IN_ Input Current Logic High or Low I R NO_ or = ±25, = +12 NO_ or = ±25, = +12 T A MIN TYP MAX IN_H 2.4 IN_L I IN_H, I IN_L IN_ = +.8 or UNITS ma kω 4

5 ELECTRICAL CHARACTERISTICS Single Supply (continued) ( = +12, - =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) PARAMETER SYMBOL SWITCH DYNAMIC CHARACTERISTICS Turn-On Time Turn-Off Time Break-Before-Make Time Delay t BBM CONDITIONS = +1, R L = 2kΩ; Figure 2 = +1, R L = 2kΩ; Figure 2 = +1, R L = 1kΩ; Figure 3 T A MIN TYP MAX 5 1 UNITS Charge Injection Q C L = 1pF, = ; Figure 4 2 pc NO_ or Off-Capacitance C N_(OFF) f = 1MHz; Figure 5 5 pf On-Capacitance C (ON) f = 1MHz; Figure 5 15 pf Off-Isolation (Note 7) ISO R L = 5Ω, C L = 15pF, NO_ = 1 RMS, f = 1MHz; Figure 6-62 db Channel-to-Channel Crosstalk (Note 8) CT R L = 5Ω, C L = 15pF, NO_ = 1 RMS, f = 1MHz; Figure 6-65 db POWER SUPPLY Power-Supply Range 9 36 Supply Current I+ All IN_ = or +5, NO_ = = and GND Supply Current I GND All IN_ = or +12, NO_ = = All IN_ = or +5, NO_ = = Note 3: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 4: R ON = R ON(MAX) - R ON(MIN). Note 5: Leakage parameters are 1% tested at maximum-rated hot temperature and guaranteed by correlation at T A =. Note 6: Guaranteed by design. Note 7: Off-isolation = 2log1( / NO_ ), = output, NO_ = input to off switch. Note 8: Between any two analog inputs. Note 9: Leakage testing for single-supply operation is guaranteed by testing with dual supplies. 5

6 ( = +15, - = -15, T A =, unless otherwise noted.) RON (Ω) RON (Ω) ton, toff () ON-RESISTANCE vs. COM (DUAL SUPPLIES) ± = ± ± = ±1 18 ± = ± ± = ±15 6 ± = ± COM () ON-RESISTANCE vs. COM AND TEMPERATURE (SINGLE SUPPLY) 45 T 4 A = +125 C T A = +85 C 35 T A = +7 C T A = T A = C T 1 A = -4 C T A = -55 C = = COM () TURN-ON/TURN-OFF TIME vs. SUPPLY OLTAGE (DUAL SUPPLIES) ±4 ±6 ±8 ±1 ±12 ±14 ±16 ±18 SUPPLY OLTAGE () toc1 toc4 toc7a RON (Ω) LEAKAGE CURRENT (A) ON-RESISTANCE vs. COM (SINGLE SUPPLY) = +9 = +12 = = = COM () ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE Typical Operating Characteristics = +2 = +25 = +3 I ON ( = +15, - = -15) I ON ( = +12, - = ) I OFF ( = +15, - = -15) I OFF ( = +12, - = ) TEMPERATURE ( C) ton, toff () TURN-ON/TURN-OFF TIME vs. SUPPLY OLTAGE (SINGLE SUPPLY) SUPPLY OLTAGE () toc2 toc5 toc7b RON (Ω) Q (pc) ton, toff () ON-RESISTANCE vs. COM AND TEMPERATURE (DUAL SUPPLIES) T A = +125 C T A = C T A = -4 C T A = -55 C T A = +85 C T A = +7 C T A = = = COM () CHARGE INJECTION vs. COM DUAL SUPPLIES SINGLE SUPPLY COM () TURN-ON/TURN-OFF TIME vs. TEMPERATURE (DUAL SUPPLIES) 4 2 = = TEMPERATURE ( C) toc3 toco6 toc8a 6

7 Typical Operating Characteristics (continued) ( = +15, - = -15, T A =, unless otherwise noted.) ton, toff () SUPPLY CURRENT () TURN-ON/TURN-OFF TIME vs. TEMPERATURE (SINGLE SUPPLY) 5 = = TEMPERATURE ( C) POWER-SUPPLY CURRENT vs. TEMPERATURE (SINGLE SUPPLY) I+ I GND = = IN = +5 toc8b toc9c SUPPLY CURRENT () LOGIC-LEEL THRESHOLD () POWER-SUPPLY CURRENT vs. TEMPERATURE (DUAL SUPPLIES, IN = ) I+ 2 1 I GND = = TEMPERATURE ( C) LOGIC-LEEL THRESHOLD vs. SUPPLY OLTAGE DUAL-SUPPLY RANGE I- SINGLE-SUPPLY RANGE toc9a toc1 SUPPLY CURRENT () POWER-SUPPLY CURRENT vs. TEMPERATURE (DUAL SUPPLIES, IN = +5) = = TEMPERATURE ( C) NO_ or (1/div) O (1/div) O I+ I GND I- OEROLTAGE WITH ±25 INPUT toc9b toc TEMPERATURE ( C) SUPPLY OLTAGE () 5µs/div FAULT-FREE SIGNAL WITH ±15 INPUT FAULT RECOERY TIME NO_ or (1/div) O toc12 NO_ or (1/div) toc13 O (1/div) O (1/div) O 5µs/div 2µs/div 7

8 Typical Operating Characteristics (continued) ( = +15, - = -15, T A =, unless otherwise noted.) RESPONSE (db) BANDWIDTH FREQUENCY RESPONSE (DUAL SUPPLIES) OFF ISOLATION CROSSTALK FREQUENCY (MHz) = = -15 toc14a RESPONSE (db) FREQUENCY RESPONSE (SINGLE SUPPLY) -1 BANDWIDTH OFF ISOLATION -7 CROSSTALK -8-9 = = FREQUENCY (MHz) toc14b Pin Description PIN NAME FUNCTION 1, 1, 11, 2 IN1, IN2, IN3, IN4 Logic Control Digital Inputs 2, 9, 12, 19 NO1, NO2, NO3, NO4 Normally Open Inputs* 3, 8, 13, 18 COM1, COM2, COM3, COM4 Analog Switch Common Outputs* 4, 7, 14, 17 NC1, NC2, NC3, NC4 Normally Closed Inputs* 5 - Negative Analog Supply oltage Input 6 GND Digital Ground 15 N.C. No Connection. Not internally connected. 16 Positive Analog and Digital Supply-oltage Input *When the voltage on NO_ or does not exceed or -, NO_ (or ) and pi are bidirectional. Detailed Description The is a fault-protected analog switch with special operation and cotruction. Traditional fault-protected switches are cotructed using three-series CMOS devices. This combination produces good fault protection but fairly high on-resistance when the signals are within about 3 of each supply rail. These series devices are not capable of handling signals up to the power-supply rails. The differs coiderably from traditional faultprotected switches, with three advantages. First, it is cotructed with two parallel FETs, allowing very low on-resistance when the switch is on. Second, they allow signals on the or NO_ pi that are within or slightly beyond the supply rails to be passed through the switch to the terminal, allowing rail-to-rail signal operation. Third, when a signal on or NO_ exceeds the supply rails by about 15m (a fault condition), the voltage on is limited to the appropriate polarity supply voltage. Operation is identical for both fault polarities. The fault-protection extends to ±25 with power on and ±4 with power off. The has a parallel N-channel and P-channel MOSFET switch configuration with input voltage seors. The simplified internal structure is shown in Figure 1. The parallel N1 and P1 MOSFETs form the switch element. N3 and P3 are seor elements to sample the input voltage and compare it agait the power-supply rails. 8

9 or NO_ INPUT N3 SENSE SWITCH P3 SENSE SWITCH COMPARATOR N-CHANNEL DRIER P-CHANNEL DRIER N1 P1 -(-15) CLAMP N2 OUTPUT CLAMP P2 +(+15) Fault Condition The protects devices connected to its output () through its unique fault-protection circuitry. When the input voltage is raised above either supply rail, the internal see and comparator circuitries (N3 and N-channel driver or P3 and P-channel driver) disconnect the output () from the input (Figure 1). If the switch driven above the supply rail has an on state, the clamp circuitries (N2 or P2) connect the output to the appropriate supply rail. Table 1 summarizes the s operation under normal and fault conditio. Row 5 shows a negative fault condition when the supplies are on. It shows that with supplies of ±15, if the input voltage is between -15 and -25, the output () clamps to the negative supply rail of -15. With this technique, the SPDT switch is capable of withstanding a worse-case condition of opposite fault polarities at its inputs. +15 COMPARATOR Figure 1. Simplified Internal Structure During normal operation of a conducting channel, N1 and P1 remain on with a typical 125Ω on-resistance between NO_ (or ) and. If the input voltage exceeds either supply rail by about 15m, the parallel combination switches (N1, P1) are forced off through the driver and seing circuitries. At the same time, the output ( ) is clamped to the appropriate supply rail by the clamp circuitries (N2, P2). Two clamp circuits limit the output voltage to the supply voltages. For simplicity, Figure 1 shows only one side of the SPDT switch configuration. The complete circuit is composed of two channels with their outputs connected. Normal Operation Two comparators continuously compare the voltage on the NO_ (or ) pin with and - supply voltages. When the signal on NO_ (or ) is between and -, the switch behaves normally, with FETs N1 and P1 turning on and off in respoe to NO_ (or ) signals (Figure 1). For any voltage between the supply rails, the switch is bidirectional; therefore, and (or NO_ ) are interchangeable. Only NO_ and can be exposed to overvoltages beyond the supply range and within the specified breakdown limits of the device. Traient Fault Condition When a fast rising or falling traient on NO_ (or ) exceeds or -, the output () follows the input (IN_) to the supply rail by only a few nanoseconds. This delay is due to the switch on-resistance and circuit capacitance to ground. However, when the input traient retur to within the supply rails there is a longer recovery time. For positive faults, the recovery time is typically 2.5µs. For negative faults, the recovery time is typically 1.3µs. These values depend on the output resistance and capacitance. The delays are not dependent on the fault amplitude. Higher output resistance and capacitance increase the recovery times. Fault Protection, oltage, and Power Off The maximum fault voltage on the NO_ or pi is ±4 from ground when the power is off. With ±15 supply voltages, the highest voltage on NO_ (or ) can be +25, and the lowest voltage on NO_ (or ) can be -25. Exceeding these limits can damage the chip. IN_ Logic-Level Thresholds The logic-level thresholds are TTL/CMOS-compatible when is +15. Raising increases the threshold slightly; when reaches +25, the level threshold is 2.8 higher than the TTL output high-level minimum of 2.4, but still compatible with CMOS outputs (see the Typical Operating Characteristics). Increasing - has no effect on the logic-level thresholds, but it does increase the gate-drive voltage to the signal FETs, reducing their on-resistance. 9

10 Table 1. Switch States in Normal and Fault Conditio POWER SUPPLIES (, -) On INPUT RANGE Between Rails On NO_ Off OUTPUT On Between Rails Off On NO_ On Between and (+4 - ) On Off On Between and (+4 - ) Off On On Between - and (-4 - -) On Off - On Between - and (-4 - -) Off On - Off Between Rails Off Off Follows the load terminal voltage. Failure Modes The is not a lightning arrester or surge protector. Exceeding the fault-protection voltage limits on NO_ or, even for very short periods, can cause the device to fail. Applicatio Information Ground There is no connection between the analog signal paths and GND. The analog signal paths coist of an N-channel and P-channel MOSFET with their sources and drai paralleled and their gates driven out of phase to and - by the logic-level tralators. and GND power the internal logic and logic-level tralators and set the input logic thresholds. The logiclevel tralators convert the logic levels to switched and - signals to drive the gates of the switches. This drive signal is the only connection between the power supplies and the analog signals. GND, IN_, and have ESD protection diodes to and -. Supply Current Reduction When the logic signals are driven rail-to-rail from to +12 or -15 to +15, the supply current reduces to approximately half of the supply current when the logic input levels are at to 5. Power Supplies The operates with bipolar supplies between ±4.5 and ±18. The and - supplies need not be symmetrical, but their difference can not exceed the absolute maximum rating of +44. The operates from a single supply between +9 and +36 when - is connected to GND. Test Circuits/Timing Diagrams t R < 2 t F < IN 5% 5% -1 COM +1-1 t OPEN 5% 5% 5% 5% t OPEN LOGIC INPUT IN_ +15 NO_ GND (REPEAT TEST FOR IN2, IN3, AND IN4.) SWITCH OUTPUT 2kΩ Figure 2. Switching-Time Test Circuit 1

11 LOGIC INPUT SWITCH OUTPUT SWITCH OUTPUT +3 COM COM O2 O1 5% t D.9 O t D.9 O Test Circuits/Timing Diagrams (continued) LOGIC INPUT COM IN_ GND NO NC R L2 O2 C L INCLUDES FIXTURE AND STRAY CAPACITANCE. LOGIC INPUT. R L1 C L2 R L = 1Ω C L = 35pF O1 C L1 Figure 3. Break-Before-Make IN_ IN_ IN_ 5Ω GND OR NO_ - CL 1pF OUT OUT OUT - OUT IS THE MEASURED OLTAGE DUE TO CHARGE- TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF. - IS CONNECTED TO GND () FOR SINGLE-SUPPLY OPERATION. Q = OUT x C L Figure 4. Charge Injection NO_ ADDRESS SELECT IN_ GND - 1MHz CAPACITANCE ANALYZER - - IS CONNECTED TO GND () FOR SINGLE-SUPPLY OPERATION. Figure 5., NO_, Capacitance 11

12 1nF Test Circuits/Timing Diagrams (continued) IN 5Ω NETWORK ANALYZER 5Ω OFF ISOLATION = 2 log ON LOSS = 2 log OUT IN OUT IN ADDRESS SELECT IN_ NO_, OUT MEAS. REF. CROSSTALK = 2 log OUT IN GND - 5Ω 5Ω 1nF - MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT SOCKET TERMINALS. OFF ISOLATION IS MEASURED BETWEEN AND OFF NO_ OR TERMINALS. ON LOSS IS MEASURED BETWEEN AND ON NO_ OR TERMINALS. CROSSTALK IS MEASURED BETWEEN TERMINALS WITH ALL SWITCHES ON. SIGNAL DIRECTION THROUGH SWITCH IS REERSED; WORST ALUES ARE RECORDED. - IS CONNECTED TO GND () FOR SINGLE-SUPPLY OPERATION. Figure 6. Frequency Respoe, Off-Isolation, and Crosstalk Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE CPP C to +7 C 2 Plastic DIP EAP -4 C to +85 C 2 SSOP EWP EPP -4 C to +85 C -4 C to +85 C 2 Wide SO 2 Plastic DIP MJP -55 C to +125 C 2 CERDIP TRANSISTOR COUNT: 448 Chip Information Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 12 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.