PART. MAX7401CSA 0 C to +70 C 8 SO MAX7405EPA MAX7401ESA MAX7405CSA MAX7405CPA MAX7405ESA V SUPPLY CLOCK

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1 ; Rev 1; 6/99 8th-Order, Lowpass, Bessel, General Description The / 8th-order, lowpass, Bessel, switched-capacitor filters (SCFs) operate from a single +5 () or +3 () supply. These devices draw only 2mA of supply current and allow corner frequencies from 1Hz to 5kHz, making them ideal for low-power post-dac filtering and anti-aliasing applications. They feature a shutdown mode that reduces supply current to.2. Two clocking options are available on these devices: self-clocking (through the use of an external capacitor) or external clocking for tighter corner-frequency control. An offset adjust pin allows for adjustment of the DC output level. The / Bessel filters provide low overshoot and fast settling. Their fixed response simplifies the design task to selecting a clock frequency. ADC Anti-Aliasing Post-DAC Filtering Air-Bag Electronics TOP IEW Applications CT2 Base Stations Speech Processing Pin Configuration Features 8th-Order, Lowpass Bessel Filters Low Noise and Distortion: -82 THD + Noise Clock-Tunable Corner Frequency (1Hz to 5kHz) 1:1 Clock-to-Corner Ratio Single-Supply Operation +5 () +3 () Low Power 2mA (Operating Mode).2 (Shutdown Mode) Available in 8-Pin SO/DIP Packages Low Output Offset: ±5m PART CPA ESA EPA Ordering Information TEMP. RANGE CSA C to +7 C 8 SO CSA CPA ESA EPA C to +7 C -4 C to +85 C -4 C to +85 C PIN-PACKAGE 8 Plastic DIP 8 SO C to +7 C 8 SO C to +7 C -4 C to +85 C -4 C to +85 C 8 Plastic DIP 8 Plastic DIP 8 SO 8 Plastic DIP / COM IN GND CLK SHDN OS Typical Operating Circuit DD 4 5 OUT SUPPLY SO/DIP.1µF DD SHDN INPUT IN OUT OUTPUT CLOCK CLK COM GND OS.1µF Maxim Integrated Products 1 For free samples & the latest literature: or phone For small orders, phone

2 / ABSOLUTE MAXIMUM RATINGS DD to GND to to +4 IN, OUT, COM, OS, CLK to ( DD +.3) SHDN to +6 OUT Short-Circuit Duration...1sec Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Continuous Power Dissipation (T A = +7 C) 8-Pin SO (derate 5.88mW/ C above +7 C)...471mW 8-Pin DIP (derate 9.9mW/ C above +7 C)...727mW Operating Temperature Ranges MAX74 _C_A... C to +7 C MAX74 _E_A...-4 C to +85 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1sec)...+3 C ( DD = +5, filter output measured at OUT, 1kΩ 5pF load to GND at OUT, OS = COM,.1µF from COM to GND, SHDN = DD, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER FILTER CHARACTERISTICS Corner Frequency Clock-to-Corner Ratio Clock-to-Corner Tempco Output oltage Range Output Offset oltage DC Insertion Gain with Output Offset Removed SYMBOL f C f CLK /f C OFFSET (Note 1) IN = COM = DD / 2 CONDITIONS COM = DD / 2 (Note 2) MIN TYP MAX.1 to 5 1: DD -.25 ±5 ± UNITS khz ppm/ C m Total Harmonic Distortion plus Noise THD+N f IN = 2Hz, IN = 4p-p, measurement bandwidth = 22kHz -82 OS oltage Gain to OUT Input oltage Range at OS A OS OS 1 COM ±.1 / COM oltage Range COM Input, COM externally driven Output, COM internally biased DD / 2 DD / 2 DD / DD / 2 DD / 2 DD / Input Resistance at COM Clock Feedthrough Resistive Output Load Drive R COM R L kω mp-p kω Maximum Capacitive Load at OUT C L 5 5 pf Input Leakage Current at COM Input Leakage Current at OS CLOCK Internal Oscillator Frequency Clock Input Current Clock Input High Clock Input Low f OSC I CLK IH IL SHDN = GND, COM = to DD OS = to ( DD - 1) (Note 3) C OSC = 1pF (Note 4) CLK = or 5 ±.1 ±1 ±.1 ± ±15 ±3 DD khz 2

3 ELECTRICAL CHARACTERISTICS (continued) ( DD = +5, filter output measured at OUT, 1kΩ 5pF load to GND at OUT, OS = COM,.1µF from COM to GND, SHDN = DD, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER POWER REQUIREMENTS SYMBOL Measured at DC ELECTRICAL CHARACTERISTICS CONDITIONS MIN TYP MAX Supply oltage DD Supply Current I DD Operating mode, no load, IN = OS = COM Shutdown Current Power-Supply Rejection Ratio SHUTDOWN SHDN Input High SHDN Input Low I SHDN PSRR SDH SDL SHDN = GND, CLK driven from to DD DD SHDN Input Leakage Current SHDN = to DD ±.1 ±1 ( DD = +3, filter output measured at OUT, 1kΩ 5pF load to GND at OUT, OS = COM,.1µF from COM to GND, SHDN = DD, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX FILTER CHARACTERISTICS Corner Frequency f C (Note 1).1 to 5 Clock-to-Corner Ratio f CLK /f C 1:1 Clock-to-Corner Tempco 1 Output oltage Range.25 DD -.25 Output Offset oltage OFFSET IN = COM = DD / 2 ±5 ±25 DC Insertion Gain with Output Offset Removed COM = DD / 2 (Note 2) UNITS ma UNITS khz ppm/ C m / Total Harmonic Distortion plus Noise Maximum Capacitive Load at OUT Input Leakage Current at COM Input Leakage Current at OS f THD+N IN = 2Hz, IN = 2.5p-p, -84 measurement bandwidth = 22kHz OS oltage Gain to OUT A OS 1 Input oltage Range at OS OS COM ±.1 COM oltage Range DD / 2 COM DD / 2 DD / 2 COM internally biased or externally driven Input Resistance at COM R COM Clock Feedthrough 1 Resistance Output Load Drive R L 1 1 C L 5 5 SHDN = GND, COM = to DD OS = to ( DD - 1) (Note 3) ±.1 ±1 ±.1 ±1 / kω mp-p kω pf 3

4 / ELECTRICAL CHARACTERISTICS (continued) ( DD = +3, filter output measured at OUT, 1kΩ 5pF load to GND at OUT, OS = COM,.1µF from COM to GND, SHDN = DD, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) CLOCK PARAMETER Internal Oscillator Frequency Clock Input Current Clock Input High Clock Input Low POWER REQUIREMENTS Supply oltage Supply Current Shutdown Current Power-Supply Rejection Ratio SHUTDOWN SHDN Input High SHDN Input Low SYMBOL f OSC I CLK IH IL DD I DD I SHDN PSRR SDH SDL CONDITIONS C OSC = 1pF (Note 4) CLK = or 3 Operating mode, no load, IN = OS = COM SHDN = GND, CLK driven from to DD Measured at DC MIN TYP MAX DD DD -.5 ±15 ± SHDN Input Leakage Current SHDN = to DD ±.1 ± UNITS khz ma FILTER CHARACTERISTICS / ( DD = +5 for, DD = +3 for ; filter output measured at OUT; 1kΩ 5pF load to GND at OUT; SHDN = DD ; COM = OS = DD /2; f CLK = 1kHz; T A = T MIN to T MAX ; unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER Insertion Gain Relative to DC Gain CONDITIONS MIN TYP MAX f IN =.5f C f IN = f C f IN = 3f C f IN = 6f C UNITS Note 1: The maximum f C is defined as the clock frequency, f CLK = 1 f C, at which the peak SINAD drops to 68 with a sinusoidal input at.2f C. Note 2: DC insertion gain is defined as OUT / IN. Note 3: OS voltages above DD - 1 saturate the input and result in a 75 typical input leakage current. Note 4: For, f OSC (khz) / C OSC (pf). For, f OSC (khz) / C OSC (pf). 4

5 GAIN () FREQUENCY RESPONSE INPUT FREQUENCY (khz) f C = 1kHz toc1 GAIN () PASSBAND FREQUENCY RESPONSE INPUT FREQUENCY (Hz) Typical Operating Characteristics ( DD = +5 for, DD = +3 for ; f CLK = 1kHz; SHDN = DD ; COM = OS = DD / 2; T A = +25 C; unless otherwise noted.) f C = 1kHz MAX749 toc2 PHASE SHIFT (DEGREES) PHASE RESPONSE INPUT FREQUENCY (Hz) f C = 1kHz toc3 / SUPPLY CURRENT (ma) NO LOAD SUPPLY CURRENT vs. SUPPLY OLTAGE toc4 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE NO LOAD toc5 OFFSET OLTAGE (m) OFFSET OLTAGE vs. SUPPLY OLTAGE IN = COM = DD / 2 toc SUPPLY OLTAGE () TEMPERATURE ( C) SUPPLY OLTAGE () OFFSET OLTAGE (m) OFFSET OLTAGE vs. TEMPERATURE IN = COM = DD / 2 toc7 OSCILLATOR FREQUENCY (khz) 1, INTERNAL OSCILLATOR FREQUENCY vs. C OSC CAPACITANCE toc8 NORMALIZED OSCILLATOR FREQUENCY NORMALIZED OSCILLATOR FREQUENCY vs. SUPPLY OLTAGE C OSC = 39pF toc TEMPERATURE ( C) C OSC CAPACITANCE (nf) SUPPLY OLTAGE () 5

6 / Typical Operating Characteristics (continued) ( DD = +5 for, DD = +3 for ; f CLK = 1kHz; SHDN = DD ; COM = OS = DD / 2; T A = +25 C; unless otherwise noted.) NORMALIZED OSCILLATOR FREQUENCY NORMALIZED OSCILLATOR FREQUENCY vs. TEMPERATURE C OSC = 39pF TEMPERATURE ( C) toc1 THD + NOISE () THD PLUS NOISE vs. INPUT SIGNAL AMPLITUDE NO LOAD (SEE TABLE A) AMPLITUDE (p-p) B A toc11 THD + NOISE () THD PLUS NOISE vs. INPUT SIGNAL AMPLITUDE AND RESISTIE LOAD f IN = 2Hz f C = 1kHz MEASUREMENT BW = 22kHz R L = 5Ω R L = 1kΩ R L = 1kΩ AMPLITUDE (p-p) toc THD PLUS NOISE vs. INPUT SIGNAL AMPLITUDE NO LOAD (SEE TABLE A) toc THD PLUS NOISE vs. INPUT SIGNAL AMPLITUDE AND RESISTIE LOAD f IN = 2Hz f C = 1kHz MEASUREMENT BW = 22kHz toc14 THD + NOISE () A B THD + NOISE () R L = 5Ω R L = 1kΩ R L = 1kΩ AMPLITUDE (p-p) AMPLITUDE (p-p) Table A. THD Plus Noise vs. Input Signal Amplitude Test Conditions TRACE f IN (Hz) f C (khz) A 1 5 B 2 1 f CLK (khz) 5 1 MEASUREMENT BANDWIDTH (khz)

7 PIN NAME 1 COM 2 IN Filter Input 3 GND Ground FUNCTION Common Input. Biased internally at mid-supply. Bypass externally to GND with a.1µf capacitor. To override internal biasing, drive with an external supply. 4 DD Positive Supply Input: +5 for, +3 for 5 OUT Filter Output 6 OS 7 SHDN Shutdown Input. Drive low to enable shutdown mode; drive high or connect to DD for normal operation. 8 CLK Offset Adjust Input. To adjust output offset, bias OS externally. Connect OS to COM if no offset adjustment is needed. Refer to Offset and Common-Mode Input Adjustment section. Clock Input. To override the internal oscillator, connect to an external clock; otherwise, connect an external capacitor (C OSC ) from CLK to GND to set the internal oscillator frequency. Detailed Description The / Bessel filters provide low overshoot and fast settling responses. Both parts operate with a 1:1 clock-to-corner frequency ratio and a 5kHz maximum corner frequency. Lowpass Bessel filters such as the / delay all frequency components equally, preserving the shape of step inputs (subject to the attenuation of the higher frequencies). Bessel filters settle quickly an important characteristic in applications that use a multiplexer (mux) to select an input signal for an analog-todigital converter (ADC). An anti-aliasing filter placed between the mux and the ADC must settle quickly after a new channel is selected. Figure 1 shows the difference between Bessel and Butterworth filters when a 1kHz square wave is applied to the filter input. With the filter cutoff frequencies set at 5kHz, trace B shows the Bessel filter response and trace C shows the Butterworth filter response. Background Information Most switched-capacitor filters (SCFs) are designed with biquadratic sections. Each section implements two filtering poles, and the sections are cascaded to produce higher order filters. The advantage to this approach is ease of design. However, this type of design is highly sensitive to component variations if any section s Q is high. An alternative approach is to emulate a passive network using switched-capacitor integrators with summing and scaling. Figure 2 shows a basic 8th-order ladder filter structure. A B C 2µs/div A: 1kHz INPUT SIGNAL B: BESSEL FILTER RESPONSE; f C = 5kHz C: BUTTERWORTH FILTER RESPONSE; f C = 5kHz Figure 1. Bessel vs. Butterworth Filter Response + - R1 IN L1 C2 Pin Description L3 L5 L7 Figure 2. 8th-Order Ladder Filter Network C4 C6 C8 2/div 2/div 2/div R2 / 7

8 / A switched-capacitor filter such as the / emulates a passive ladder filter. The filter s component sensitivity is low when compared to a cascaded biquad design because each component affects the entire filter shape, not just one pole-zero pair. In other words, a mismatched component in a biquad design will have a concentrated error on its respective poles, while the same mismatch in a ladder filter design results in an error distributed over all poles. Clock Signal External Clock The / family of SCFs is designed for use with external clocks that have a 4% to 6% duty cycle. When using an external clock with these devices, drive CLK with a CMOS gate powered from to DD. arying the rate of the external clock adjusts the corner frequency of the filter as follows: f C = f CLK / 1 Internal Clock When using the internal oscillator, connect a capacitor (C OSC ) between CLK and ground. The value of the capacitor determines the oscillator frequency as follows: f OSC (khz) = where K = 38 for and K = 34 for. Minimize the stray capacitance at CLK so that it does not affect the internal oscillator frequency. ary the rate of the internal oscillator to adjust the filter s corner frequency by a 1:1 clock-to-corner frequency ratio. For example, an internal oscillator frequency of 1kHz produces a nominal corner frequency of 1kHz. Input Impedance vs. Clock Frequencies The / s input impedance is effectively that of a switched-capacitor resistor and is inversely proportional to frequency. The input impedance values determined below represent the average input impedance since the input current is not continuous. As a rule, use a driver with an output impedance less than 1% of the filter s input impedance. Estimate the input impedance of the filter using the following formula: ZIN K13 ; C OSC in pf COSC 1 f CLK CIN = ( ) where f CLK = clock frequency and C IN = 3.37pF. Low-Power Shutdown Mode These devices feature a shutdown mode that is activated by driving SHDN low. In shutdown mode, the filter s supply current reduces to.2 (typ) and its output becomes high impedance. For normal operation, drive SHDN high or connect to DD. Applications Information Offset and Common-Mode Input Adjustment The voltage at COM sets the common-mode input voltage and is biased at mid-supply with an internal resistordivider. Bypass COM with a.1µf capacitor and connect OS to COM. For applications requiring offset adjustment or DC level shifting, apply an external bias voltage through a resistor-divider network to OS, as shown in Figure 3. (Note: Do not leave OS unconnected.) The output voltage is represented by this equation: OUT = ( IN - COM ) + OS with COM = DD / 2 (typical), and where ( IN - COM ) is lowpass filtered by the SCF, and OS is added at the output stage. See the Electrical Characteristics for the voltage range of COM and OS. Changing the voltage on COM or OS significantly from mid-supply reduces the filter s dynamic range. Power Supplies The operates from a single +5 supply, and the operates from a single +3 supply. Bypass DD to GND with a.1µf capacitor. If dual supplies are required (±2.5 for, ±1.5 for ), connect COM to system ground and connect.1µf INPUT CLOCK SUPPLY IN CLK DD GND SHDN OUT COM OS.1µF.1µF OUTPUT 5k 5k 5k Figure 3. Offset Adjustment Circuit 8

9 Table 1. Typical Harmonic Distortion + - FILTER INPUT CLOCK f CLK (khz) IN CLK GND to the negative supply. Figure 4 shows an example of dual-supply operation. Single- and dual-supply performance are equivalent. For either single- or dual-supply operation, drive CLK and SHDN from GND (- in dualsupply operation) to DD. For ±5 dual-supply applications, use the MAX291 MAX DD GND *DRIE SHDN TO - FOR LOW-POWER SHUTDOWN MODE. Figure 4. Dual-Supply Operation - f C (khz) SHDN OUT COM OS * OUTPUT.1µF f IN (Hz) µF IN (p-p) 4 2 TYPICAL HARMONIC DISTORTION () 2nd rd th 5th Anti-Aliasing and Post-DAC Filtering When using the / for anti-aliasing or post-dac filtering, synchronize the DAC and the filter clocks. If the clocks are not synchronized, beat frequencies may alias into the passband. The high clock-to-corner frequency ratio (1:1) also eases the requirements of pre- and post-scf filtering. At the input, a lowpass filter prevents the aliasing of frequencies around the clock frequency into the passband. At the output, a lowpass filter attenuates the clock feedthrough. A high clock-to-corner frequency ratio allows a simple RC lowpass filter, with the cutoff frequency set above the SCF corner frequency, to provide input anti-aliasing and reasonable output clock attenuation Harmonic Distortion Harmonic distortion arises from nonlinearities within the filter. These nonlinearities generate harmonics when a pure sine wave is applied to the filter input. Table 1 lists the / s typical harmonic-distortion values with a 1kΩ load at T A = +25 C. Chip Information / Input Signal Amplitude Range The optimal input signal range is determined by observing the voltage level at which the total harmonic distortion plus noise (THD+N) is minimized for a given corner frequency. The Typical Operating Characteristics show graphs of the devices THD+N response as the input signal s peak-to-peak amplitude is varied. These measurements are made with OS and COM biased at midsupply. TRANSISTOR COUNT:

10 / Package Information SOICN.EPS 1

11 Package Information (continued) PDIPN.EPS / 11

12 / NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.