Quad, Rail-to-Rail, Fault-Protected, SPDT Analog Switch

Transcription

1 ; Rev 1; 1/99 Quad, Rail-to-Rail, Fault-Protected, General Description The quad, single-pole/double-throw (SPDT), fault-protected analog switch is pin-compatible with the industry-standard MAX333 and MAX333A. The features fault-protected inputs and Rail-to-Rail signal handling. The normally open (NO_ ) and normally closed ( ) terminals are protected from overvoltage faults up to ±25V with power on and up to ±4V with power off. During a fault condition, NO_ and become high impedance with only nanoamperes of leakage current flowing to the source. In addition, the output () clamps to the appropriate polarity supply rail and provides up to ±1mA of load current. This ensures unambiguous rail-to-rail outputs when a fault occurs. The operates from dual ±4.5V to ±18V power supplies or a single +9V to +36V supply. All digital inputs have +.8V and +2.4V logic thresholds, ensuring both TTL and CMOS logic compatibility when using ±15V supplies or a +12V supply. On-resistance is 175Ω max and is matched between switches to 1Ω max. The offleakage current is only.5 at TA = and 1 at TA = +85 C. Redundant/Backup Systems Test Equipment Communications Systems Industrial and Process Control INPUTS V1 V2 OSC IN V3 V4 FLYING CAPACITOR LEVEL TRANSLATOR (2-CHANNEL) Applications Portable Instruments Data-Acquisition Systems Avionics Systems Typical Operating Circuit OUTPUTS V1 - V2 V3 - V4 Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Patent Pending Features Rail-to-Rail Signal Handling ±4V Fault Protection with Power Off ±25V Fault Protection with ±15V Supplies All Switches Off with Power Off No Power-Supply Sequencing Required During Power-Up or Power-Down Output Clamped to Appropriate Supply Voltage During Fault Condition No Transition Glitch 1kΩ (typ) Output Clamp Resistance During Overvoltage 175Ω (max) Signal Paths with ±15V Supplies 2ns (typ) Fault Response Time ±4.5V to ±18V Dual Supplies +9V to +36V Single Supply Pin-Compatible with Industry-Standard MAX333/MAX333A TTL/CMOS-Compatible Logic Inputs with ±15V or Single +9V to +15V Supplies PART TEMP. RANGE PIN-PACKAGE CAP CWP C to +7 C C to +7 C 2 SSOP 2 Wide SO Ordering Information continued at end of data sheet. TOP VIEW IN1 1 NO1 2 COM1 3 NC1 4 5 GND 6 NC2 7 COM2 8 NO2 9 IN2 1 Ordering Information Pin Configuration/ Functional Diagram SSOP/SO/DIP/CERDIP 2 IN4 19 NO4 18 COM4 17 NC N.C. 14 NC3 13 COM3 12 NO3 11 IN3 SWITCHES ARE SHOWN WITH LOGIC "" INPUT N.C. = NOT INTERNALLY CONNECTED Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Voltages Referenced to GND...-.3V to +44.V V to +.3V to...-.3v to +44.V, IN_ (Note 1)... ( -.3V) to ( +.3V), NO_ (Note 2)...( - 4V) to ( + 4V), NO_ to...-4v to +4V, NO_ Overvoltage with Switch Power On (supplies at ±15V)...-3V to +3V, NO_ Overvoltage with Switch Power Off...-4V to +4V Continuous Current into Any Terminal...±3mA Peak Current into Any Terminal (pulsed at 1ms,1% duty cycle)...±5ma Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supplies Continuous Power Dissipation (T A = +7 C) 2-Pin SSOP (derate 1.53mW/ C above +7 C)...842mW 2-Pin Wide SO (derate 1.mW/ C above +7 C).. 8mW 2-Pin Plastic DIP (derate 11.11mW/ C above +7 C) 889mW 2-Pin CERDIP (derate 11.11mW/ C above +7 C)...889mW Operating Temperature Ranges C... C to +7 C E...-4 C to +85 C M C to +125 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Note 1: and IN_ pins are not fault protected. Signals on or IN_ exceeding or are clamped by internal diodes. Limit forward diode current to maximum current rating. Note 2: and NO_ pins are fault protected. Signals on or NO_ exceeding -25V to +25V may damage the device. These limits apply with power applied to or. The limit is ±4V with = =. ( = +15V, = -15V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) PARAMETER ANALOG SWITCH Fault-Free Analog Signal Range (Note 2) SYMBOL V NO_, V CONDITIONS = +15V, = -15V, V NO _ or V = ±15V T A MIN TYP MAX to NO_ or to V NO _ or V NC _ = ±1V, R ON C, E 2 On-Resistance I COM _ = 1mA M 25 Ω to NO_ or to 1 6 V NO _ or V NC _ = ±1V, On-Resistance Match Between R ON C, E 1 I COM _ = 1mA Channels (Note 4) M 15 Ω On-Resistance Flatness V = +5V,, -5V, I = 1mA 4 Ω NO_ or Off-Leakage I NO_(OFF), V NO _ or V NC _ = ±14V, C, E -1 1 Current (Note 5) I (OFF) V COM _ = 14V M On-Leakage Current V = ±14V, I (ON) C, E -2 2 (Note 5) V NO_ or V = ±14V or floating M -4 4 FAULT Fault-Protected Analog Signal Applies with power on V NO_, V Range (Note 2) Applies with power off V -1 1 Output Leakage Current, V NO_ or V = ±25V, I C, E -2 2 Supplies On no connection to ON channel M NO_ or Off Input Leakage V NO _ or V NC _ = ±25V, I NO_, I C, E -2 2 Current, Supplies On V COM _ = 1V M -1 1 ± ± UNITS V 2

3 ELECTRICAL CHARACTERISTICS Dual Supplies (continued) ( = +15V, = -15V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) PARAMETER SYMBOL CONDITIONS T A MIN TYP MAX UNITS NO_ or Input Leakage V I NO_, I NO_ or V = ±4V, C, E -2 2 Current, Supplies Off =, = M -1 1 On-Clamp Output V NO_ or V = +25V Current, Supplies On I V NO_ or V = -25V ma On-Clamp Output R V Resistance, Supplies On NO_ or V NC = ±25V 3 kω ±Fault Output Clamp Turn-On Delay Time (Note 6) ±Fault Recovery Time (Note 6) LOGIC INPUT IN_ Input Logic Threshold High IN_ Input Logic Threshold Low IN_ Input Current Logic High or R L = 1kΩ, V NO_ or V = ±25V V IN_H 2.4 V V IN_L.8 V I IN_H, I IN_L V IN_ = +.8V or +2.4V Low -5 5 SWITCH DYNAMIC CHARACTERISTICS Turn-On Time Turn-Off Time Break-Before-Make Time Delay Charge Injection (Note 6) NO_ or Off-Capacitance On-Capacitance Off-Isolation (Note 7) Channel-to-Channel Crosstalk (Note 8) POWER SUPPLY Power-Supply Range Supply Current Supply Current GND Supply Current t BBM Q C N_(OFF) C (ON) V ISO V CT, I+ I- I GND R L = 1kΩ, V NO_ or V = ±25V V = ±1V, R L = 2kΩ; Figure 2 V NO_ = ±1V, R L = 2kΩ; Figure 2 V = ±1V, R L = 1kΩ; Figure 3 C L = 1pF, V = ; Figure 4 f = 1MHz; Figure 5 f = 1MHz; Figure 5 R L = 5Ω, C L = 15pF, V N_ = 1V RMS, f = 1MHz; Figure 6 R L = 5Ω, C L = 15pF, V N_ = 1V RMS, f = 1MHz; Figure 6 All V IN_ = or +5V, V NO_ = V = All V IN_ = or +5V, V NO_ = V = All V IN_ = or +5V, V NO_ = V = C, E 4 M C, E 3 M ns 2.5 µs ns ns ns pf pf db ±4.5 ±18 V pc db 3

4 ELECTRICAL CHARACTERISTICS Single Supply ( = +12V, =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) PARAMETER ANALOG SWITCH Fault-Free Analog Signal Range (Note 2) SYMBOL V NO_, V CONDITIONS = +12V, =, V NO _ or V = +12V or T A MIN TYP MAX = +12V, to NO_, to R V NO _ or V NC _ = +1V, C, E 45 On-Resistance ON I COM _ = 1mA M 525 Ω -NO_ On-Resistance = +12V, 4 1 Match Between Channels R ON V NO _ or V NC _ = +1V, C, E 2 Ω (Note 4) I COM _ = 1mA M 3 = +12V, NO_ or Off-Leakage I NO_(OFF), V = +1V, +1V, C, E -1 1 Current (Notes 5, 9) I (OFF) V NO_ or V = +1V, +1V M -2 2 = +12V, On-Leakage Current I (ON) V = +1V, C, E -2 2 (Notes 5, 9) V NO_ or V = +1V or floating M -4 4 FAULT Fault-Protected Analog Signal Applies with power on V NO_, V Range (Note 2) Applies with power off V V NO_ or V = ±25V, -1 1 Output Leakage Current, I = +12V, C, E -2 2 Supply On (Note 9) no connection to ON channel M -1 1 V NO_ or V = ±25V, -2 2 NO_ or Off Input Leakage I NO_, I V =, C, E -2 2 Current, Supply On (Note 9) = +12V M NO_ or Input Leakage V NO_ or V = ±4V, I NO_, I C, E -2 2 Current, Supply Off (Note 9) =, = M -1 1 On-Clamp Output V NO_ or V = ±25V, I Current, Supply On = +12V ma On-Clamp Output V NO_ or V = ±25V, R Resistance, Supply On = +12V kω LOGIC INPUT IN_ Input Logic Threshold High V IN_H 2.4 V IN_ Input Logic Threshold Low V IN_L.8 V IN_ Input Current Logic High or I IN_H, I IN_L V IN_ = +.8V or +2.4V Low -5 5 UNITS V 4

5 ELECTRICAL CHARACTERISTICS Single Supply (continued) ( = +12V, =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A =.) (Note 3) Turn-On Time PARAMETER Break-Before-Make Time Delay SYMBOL SWITCH DYNAMIC CHARACTERISTICS Turn-Off Time t BBM CONDITIONS V = +1V, R L = 2kΩ; Figure 2 V = +1V, R L = 2kΩ; Figure 2 V = +1V, R L = 1kΩ; Figure 3 T A MIN TYP MAX UNITS ns ns ns Charge Injection Q C L = 1pF, V = ; Figure 4 2 pc NO_ or Off-Capacitance C N_(OFF) f = 1MHz; Figure 5 5 pf On-Capacitance C (ON) f = 1MHz; Figure 5 15 pf Off-Isolation (Note 7) V ISO R L = 5Ω, C L = 15pF, V NO_ = 1V RMS, f = 1MHz; Figure 6-62 db Channel-to-Channel Crosstalk (Note 8) V CT R L = 5Ω, C L = 15pF, V NO_ = 1V RMS, f = 1MHz; Figure 6-65 db POWER SUPPLY Power-Supply Range 9 36 V Supply Current I+ All V IN_ = or +5V, V NO_ = V = and GND Supply Current I GND All V IN_ = or +12V, V NO_ = V = All V IN_ = or +5V, V NO_ = V = Note 3: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 4: R ON = R ON(MAX) - R ON(MIN). Note 5: Leakage parameters are 1% tested at maximum-rated hot temperature and guaranteed by correlation at T A =. Note 6: Guaranteed by design. Note 7: Off-isolation = 2log1(V / V NO_ ), V = output, V NO_ = input to off switch. Note 8: Between any two analog inputs. Note 9: Leakage testing for single-supply operation is guaranteed by testing with dual supplies. 5

6 ( = +15V, = -15V, T A =, unless otherwise noted.) RON (Ω) RON (Ω) ton, toff (ns) ON-RESISTANCE vs. V COM (DUAL SUPPLIES) V± = ±4.5V V± = ±1V 18 V± = ±12V V± = ±15V 6 V± = ±18V V COM (V) ON-RESISTANCE vs. V COM AND TEMPERATURE (SINGLE SUPPLY) 45 T 4 A = +125 C T A = +85 C 35 T A = +7 C T 1 A = -4 C T A = -55 C = +12V 5 = V COM (V) T A = T A = C TURN-ON/TURN-OFF TIME vs. SUPPLY VOLTAGE (DUAL SUPPLIES) ±4 ±6 ±8 ±1 ±12 ±14 ±16 ±18 SUPPLY VOLTAGE (V) toc1 toc4 toc7a RON (Ω) LEAKAGE CURRENT (A) ON-RESISTANCE vs. V COM (SINGLE SUPPLY) = +9V = +12V = +15V 1 = +36V 5 = V COM (V) ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE Typical Operating Characteristics = +2V = +25V = +3V I ON ( = +15V, = -15V) I ON ( = +12V, = ) I OFF ( = +15V, = -15V) I OFF ( = +12V, = ) TEMPERATURE ( C) ton, toff (ns) TURN-ON/TURN-OFF TIME vs. SUPPLY VOLTAGE (SINGLE SUPPLY) SUPPLY VOLTAGE (V) toc2 toc5 toc7b RON (Ω) Q (pc) ton, toff (ns) ON-RESISTANCE vs. V COM AND TEMPERATURE (DUAL SUPPLIES) T A = C T A = -4 C T A = -55 C T A = +125 C T A = +85 C T A = +7 C T A = = +15V = -15V V COM (V) CHARGE INJECTION vs. V COM DUAL SUPPLIES SINGLE SUPPLY V COM (V) TURN-ON/TURN-OFF TIME vs. TEMPERATURE (DUAL SUPPLIES) 4 2 = +15V = -15V TEMPERATURE ( C) toc3 toco6 toc8a 6

7 Typical Operating Characteristics (continued) ( = +15V, = -15V, T A =, unless otherwise noted.) ton, toff (ns) SUPPLY CURRENT () TURN-ON/TURN-OFF TIME vs. TEMPERATURE (SINGLE SUPPLY) 5 = +12V = TEMPERATURE ( C) POWER-SUPPLY CURRENT vs. TEMPERATURE (SINGLE SUPPLY) I+ I GND = +12V = V IN = +5V toc8b toc9c SUPPLY CURRENT () LOGIC-LEVEL THRESHOLD (V) POWER-SUPPLY CURRENT vs. TEMPERATURE (DUAL SUPPLIES, V IN = ) I GND -2 I = +15V = -15V TEMPERATURE ( C) I+ LOGIC-LEVEL THRESHOLD vs. SUPPLY VOLTAGE DUAL-SUPPLY RANGE SINGLE-SUPPLY RANGE toc9a toc1 SUPPLY CURRENT () POWER-SUPPLY CURRENT vs. TEMPERATURE (DUAL SUPPLIES, V IN = +5V) = +15V = -15V TEMPERATURE ( C) NO_ or (1V/div) OV (1V/div) OV I+ I GND I- OVERVOLTAGE WITH ±25V INPUT toc9b toc TEMPERATURE ( C) SUPPLY VOLTAGE (V) 5µs/div FAULT-FREE SIGNAL WITH ±15V INPUT FAULT RECOVERY TIME NO_ or (1V/div) OV toc12 NO_ or (1V/div) toc13 OV (1V/div) OV (1V/div) OV 5µs/div 2µs/div 7

8 Typical Operating Characteristics (continued) ( = +15V, = -15V, T A =, unless otherwise noted.) RESPONSE (db) BANDWIDTH FREQUENCY RESPONSE (DUAL SUPPLIES) OFF ISOLATION CROSSTALK FREQUENCY (MHz) = +15V = -15V toc14a RESPONSE (db) BANDWIDTH FREQUENCY RESPONSE (SINGLE SUPPLY) OFF ISOLATION CROSSTALK FREQUENCY (MHz) = +12V = toc14b Pin Description PIN NAME FUNCTION 1, 1, 11, 2 IN1, IN2, IN3, IN4 Logic Control Digital Inputs 2, 9, 12, 19 NO1, NO2, NO3, NO4 Normally Open Inputs* 3, 8, 13, 18 COM1, COM2, COM3, COM4 Analog Switch Common Outputs* 4, 7, 14, 17 NC1, NC2, NC3, NC4 Normally Closed Inputs* 5 Negative Analog Supply Voltage Input 6 GND Digital Ground 15 N.C. No Connection. Not internally connected. 16 Positive Analog and Digital Supply-Voltage Input *When the voltage on NO_ or does not exceed or, NO_ (or ) and pins are bidirectional. Detailed Description The is a fault-protected analog switch with special operation and construction. Traditional fault-protected switches are constructed using three-series CMOS devices. This combination produces good fault protection but fairly high on-resistance when the signals are within about 3V of each supply rail. These series devices are not capable of handling signals up to the power-supply rails. The differs considerably from traditional faultprotected switches, with three advantages. First, it is constructed with two parallel FETs, allowing very low on-resistance when the switch is on. Second, they allow signals on the or NO_ pins that are within or slightly beyond the supply rails to be passed through the switch to the terminal, allowing rail-to-rail signal operation. Third, when a signal on or NO_ exceeds the supply rails by about 15mV (a fault condition), the voltage on is limited to the appropriate polarity supply voltage. Operation is identical for both fault polarities. The fault-protection extends to ±25V with power on and ±4V with power off. The has a parallel N-channel and P-channel MOSFET switch configuration with input voltage sensors. The simplified internal structure is shown in Figure 1. The parallel N1 and P1 MOSFETs form the switch element. N3 and P3 are sensor elements to sample the input voltage and compare it against the power-supply rails. 8

9 or NO_ INPUT -15V -15V +15V N3 SENSE SWITCH P3 SENSE SWITCH COMPARATOR N-CHANNEL DRIVER P-CHANNEL DRIVER N1 P1 -V(-15V) CLAMP N2 OUTPUT CLAMP P2 +V(+15V) Fault Condition The protects devices connected to its output () through its unique fault-protection circuitry. When the input voltage is raised above either supply rail, the internal sense and comparator circuitries (N3 and N-channel driver or P3 and P-channel driver) disconnect the output () from the input (Figure 1). If the switch driven above the supply rail has an on state, the clamp circuitries (N2 or P2) connect the output to the appropriate supply rail. Table 1 summarizes the s operation under normal and fault conditions. Row 5 shows a negative fault condition when the supplies are on. It shows that with supplies of ±15V, if the input voltage is between -15V and -25V, the output () clamps to the negative supply rail of -15V. With this technique, the SPDT switch is capable of withstanding a worse-case condition of opposite fault polarities at its inputs. +15V COMPARATOR Figure 1. Simplified Internal Structure During normal operation of a conducting channel, N1 and P1 remain on with a typical 125Ω on-resistance between NO_ (or ) and. If the input voltage exceeds either supply rail by about 15mV, the parallel combination switches (N1, P1) are forced off through the driver and sensing circuitries. At the same time, the output ( ) is clamped to the appropriate supply rail by the clamp circuitries (N2, P2). Two clamp circuits limit the output voltage to the supply voltages. For simplicity, Figure 1 shows only one side of the SPDT switch configuration. The complete circuit is composed of two channels with their outputs connected. Normal Operation Two comparators continuously compare the voltage on the NO_ (or ) pin with and supply voltages. When the signal on NO_ (or ) is between and, the switch behaves normally, with FETs N1 and P1 turning on and off in response to NO_ (or ) signals (Figure 1). For any voltage between the supply rails, the switch is bidirectional; therefore, and (or NO_ ) are interchangeable. Only NO_ and can be exposed to overvoltages beyond the supply range and within the specified breakdown limits of the device. Transient Fault Condition When a fast rising or falling transient on NO_ (or ) exceeds or, the output () follows the input (IN_) to the supply rail by only a few nanoseconds. This delay is due to the switch on-resistance and circuit capacitance to ground. However, when the input transient returns to within the supply rails there is a longer recovery time. For positive faults, the recovery time is typically 2.5µs. For negative faults, the recovery time is typically 1.3µs. These values depend on the output resistance and capacitance. The delays are not dependent on the fault amplitude. Higher output resistance and capacitance increase the recovery times. Fault Protection, Voltage, and Power Off The maximum fault voltage on the NO_ or pins is ±4V from ground when the power is off. With ±15V supply voltages, the highest voltage on NO_ (or ) can be +25V, and the lowest voltage on NO_ (or ) can be -25V. Exceeding these limits can damage the chip. IN_ Logic-Level Thresholds The logic-level thresholds are TTL/CMOS-compatible when is +15V. Raising increases the threshold slightly; when reaches +25V, the level threshold is 2.8V higher than the TTL output high-level minimum of 2.4V, but still compatible with CMOS outputs (see the Typical Operating Characteristics). Increasing has no effect on the logic-level thresholds, but it does increase the gate-drive voltage to the signal FETs, reducing their on-resistance. 9

10 Table 1. Switch States in Normal and Fault Conditions POWER SUPPLIES (, ) INPUT RANGE On Between Rails On Off On Between Rails Off On NO_ On Between and (+4V - ) On Off On Between and (+4V - ) Off On On Between and (-4V - ) On Off On Between and (-4V - ) Off On Off Between Rails Off Off Follows the load terminal voltage. NO_ OUTPUT Failure Modes The is not a lightning arrester or surge protector. Exceeding the fault-protection voltage limits on NO_ or, even for very short periods, can cause the device to fail. Applications Information Ground There is no connection between the analog signal paths and GND. The analog signal paths consist of an N-channel and P-channel MOSFET with their sources and drains paralleled and their gates driven out of phase to and by the logic-level translators. and GND power the internal logic and logic-level translators and set the input logic thresholds. The logiclevel translators convert the logic levels to switched and signals to drive the gates of the switches. This drive signal is the only connection between the power supplies and the analog signals. GND, IN_, and have ESD protection diodes to and. Supply Current Reduction When the logic signals are driven rail-to-rail from to +12V or -15V to +15V, the supply current reduces to approximately half of the supply current when the logic input levels are at to 5V. Power Supplies The operates with bipolar supplies between ±4.5V and ±18V. The and supplies need not be symmetrical, but their difference can not exceed the absolute maximum rating of +44V. The operates from a single supply between +9V and +36V when is connected to GND. Test Circuits/Timing Diagrams t R < 2ns t F < 2ns 3V +1V V IN 5% 5% V -1V V COM +1V V -1V t OPEN 5% 5% 5% 5% t OPEN LOGIC INPUT IN_ +15V NO_ GND -15V (REPEAT TEST FOR IN2, IN3, AND IN4.) SWITCH OUTPUT 2kΩ Figure 2. Switching-Time Test Circuit 1

11 LOGIC INPUT SWITCH OUTPUT SWITCH OUTPUT +3V V V COM V V COM V V O2 V O1 5% t D.9V O t D.9V O Test Circuits/Timing Diagrams (continued) LOGIC INPUT V COM IN_ GND +15V -15V NO NC R L2 V O2 C L INCLUDES FIXTURE AND STRAY CAPACITANCE. LOGIC INPUT. R L1 C L2 R L = 1Ω C L = 35pF V O1 C L1 Figure 3. Break-Before-Make V IN_ IN_ V V IN_ 5Ω V GND OR NO_ CL 1pF V OUT V OUT V OUT V OUT IS THE MEASURED VOLTAGE DUE TO CHARGE- TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF. IS CONNECTED TO GND (V) FOR SINGLE-SUPPLY OPERATION. Q = V OUT x C L Figure 4. Charge Injection NO_ ADDRESS SELECT IN_ GND 1MHz CAPACITANCE ANALYZER IS CONNECTED TO GND (V) FOR SINGLE-SUPPLY OPERATION. Figure 5., NO_, Capacitance 11

12 1nF Test Circuits/Timing Diagrams (continued) V IN NETWORK ANALYZER 5Ω 5Ω OFF ISOLATION = 2 log ON LOSS = 2 log V OUT V IN V OUT V IN ADDRESS SELECT IN_ NO_, V OUT MEAS. REF. CROSSTALK = 2 log V OUT V IN GND 5Ω 5Ω 1nF MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT SOCKET TERMINALS. OFF ISOLATION IS MEASURED BETWEEN AND OFF NO_ OR TERMINALS. ON LOSS IS MEASURED BETWEEN AND ON NO_ OR TERMINALS. CROSSTALK IS MEASURED BETWEEN TERMINALS WITH ALL SWITCHES ON. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. IS CONNECTED TO GND (V) FOR SINGLE-SUPPLY OPERATION. Figure 6. Frequency Response, Off-Isolation, and Crosstalk Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE CPP C to +7 C 2 Plastic DIP EAP -4 C to +85 C 2 SSOP EWP EPP -4 C to +85 C -4 C to +85 C 2 Wide SO 2 Plastic DIP MJP -55 C to +125 C 2 CERDIP TRANSISTOR COUNT: 448 Chip Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

13 ENGLISH?????????? WHAT'S NEW PRODUCTS SOLUTIONS DESIGN APPNOTES SUPPORT BUY COMPANY MEMBERS Part Number Table Notes: See the QuickView Data Sheet for further information on this product family or download the full data sheet (PDF, 224kB). Other options and links for purchasing parts are listed at: Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day. Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt. More: See full data sheet or Part Naming Conventions. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Part Number Free Sample Buy Direct Package: TYPE PINS SIZE DRAWING CODE/VAR * Temp RoHS/Lead-Free? C/D RoHS/Lead-Free: No CPP+ EPP+ CPP EPP CWP+T CWP+ PDIP;2 pin;.3" Dwg: 21-43D (PDF) Use pkgcode/variation: P2+2* PDIP;2 pin;.3" Dwg: 21-43D (PDF) Use pkgcode/variation: P2+2* PDIP;2 pin;.3" Dwg: 21-43D (PDF) Use pkgcode/variation: P2-2* PDIP;2 pin;.3" Dwg: 21-43D (PDF) Use pkgcode/variation: P2-2* SOIC;2 pin;.3" Dwg: 21-42B (PDF) Use pkgcode/variation: W2+4* SOIC;2 pin;.3" Dwg: 21-42B (PDF) Use pkgcode/variation: W2+4* C to +7C RoHS/Lead-Free: Yes -4C to +85C RoHS/Lead-Free: Yes C to +7C RoHS/Lead-Free: No -4C to +85C RoHS/Lead-Free: No C to +7C C to +7C RoHS/Lead-Free: Yes RoHS/Lead-Free: Yes

14 CWP-T CWP EWP SOIC;2 pin;.3" Dwg: 21-42B (PDF) Use pkgcode/variation: W2-4* SOIC;2 pin;.3" Dwg: 21-42B (PDF) Use pkgcode/variation: W2-4* SOIC;2 pin;.3" Dwg: 21-42B (PDF) Use pkgcode/variation: W2-4* C to +7C C to +7C RoHS/Lead-Free: No RoHS/Lead-Free: No -4C to +85C RoHS/Lead-Free: No EWP-T -4C to +85C RoHS/Lead-Free: No CAP CAP+T CAP+ CAP-T EAP+ EAP+T EAP EAP-T SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2-2* SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2+2* SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2+2* SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2-2* SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2+2* SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2+2* SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2-2* SSOP;2 pin;.29" Dwg: 21-56C (PDF) Use pkgcode/variation: A2-2* C to +7C C to +7C C to +7C C to +7C RoHS/Lead-Free: No RoHS/Lead-Free: Yes RoHS/Lead-Free: Yes RoHS/Lead-Free: No -4C to +85C RoHS/Lead-Free: Yes -4C to +85C RoHS/Lead-Free: Yes -4C to +85C RoHS/Lead-Free: No -4C to +85C RoHS/Lead-Free: No Didn't Find What You Need? CONTACT US: SEND US AN C opyright 27 by Maxim Integrated Products, Dallas Semiconductor Legal Notices P rivacy P olicy