Improved Quad CMOS Analog Switches

Transcription

1 Improved Quad CMOS Analog Switches DESCRIPTION The analog switches are highly improved versions of the industry-standard DG2A, DG22. These devices are fabricated in proprietary silicon gate CMOS process, resulting in lower on-resistance, lower leakage, higher speed, and lower power consumption. These quad single-pole single-throw switches are designed for a wide variety of applications in telecommunications, instrumentation, process control, computer peripherals, etc. An improved charge injection compensation design minimizes switching transients. The DG2B and DG22B can handle up to ± 22 V input signals, and have an improved continuous current rating of 3 ma. An epitaxial layer prevents latchup. All devices feature true bi-directional performance in the on condition, and will block signals to the supply voltages in the off condition. The DG2B is a normally closed switch and the DG22B is a normally open switch. (see Truth Table.) FEATURES ± 22 V supply voltage rating TTL and CMOS compatible logic Low on-resistance - R DS(on) : 45 Low leakage - I D(on) : 2 pa Single supply operation possible Extended temperature range Fast switching - t ON : 2 ns Low glitching - Q: pc Compliant to RoHS Directive 22/95/EC BENEFITS Wide analog signal range Simple logic interface Higher accuracy Minimum transients Reduced power consumption Superior to DG2A, DG22 Space savings (TSSOP) APPLICATIONS Industrial instrumentation Test equipment Communications systems Disk drives Computer peripherals Portable instruments Sample-and-hold circuits Pb-free Available RoHS* COMPLIANT FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG2B Dual-In-Line, SOIC and TSSOP IN 6 IN 2 D 2 5 D 2 S 3 4 S V+ GND 5 2 NC S 4 6 S 3 TRUTH TABLE Logic DG2B DG22B ON OFF OFF ON Logic.8 V Logic 2.4 V D 4 7 D 3 IN IN 3 * Pb containing terminations are not RoHS compliant, exemptions may apply Top View THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

2 ORDERING INFORMATION Temp. Range Package Part Number - 55 C to 25 C 6-pin CerDIP - 4 C to 85 C 6-pin Plastic DIP 6-pin narrow SOIC 6-pin TSSOP DG2BAK DG22BAK DG2BDJ DG2BDJ-E3 DG22BDJ DG22BDJ-E3 DG2BDY DG2BDY-E3 DG2BDY-T DG2BDY-T-E3 DG22BDY DG22BDY-E3 DG22BDY-T DG22BDY-T-E3 DG2BDQ DG2BDQ-E3 DG2BDQ-T DG2BDQ-T-E3 DG22BDQ DG22BDQ-E3 DG22BDQ-T DG22BDQ-T-E3 ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit Voltages Referenced, V+ to 44 GND 25 Digital Inputs a () - 2 to (V+) + 2, V S, V D or 3 ma, whichever occurs first Current (Any terminal) 3 Peak Current S or D (Pulsed at ms, % duty cycle max.) Storage Temperature Power Dissipation (Package) b (AK, DK suffix) - 65 to (DJ, DY, DQ suffix) - 65 to 25 6-pin plastic DIP c 47 6-pin narrow SOIC and TSSOP d 64 6-pin CerDIP e 9 LCC-2 f 7 Notes: a. Signals on S X, D X, or IN X exceeding V+ or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate 6.5 mw/ C above 75 C. d. Derate 7.6 mw/ C above 75 C. e. Derate 2 mw/ C above 75 C. f. Derate mw/ C above 75 C. V ma C mw 2 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

3 SCHEMATIC DIAGRAM (typical channel) V+ 5 V Reg S X IN X Level Shift/ Drive V+ D X GND SPECIFICATIONS a Parameter Symbol Figure. Test Conditions Unless Specified V+ = 5 V, = - 5 V V IN = 2.4 V,.8 V f Temp. b Typ. c A Suffix - 55 C to 25 C D Suffix - 4 C to 85 C Min. d Max. d Min. d Max. d Analog Switch Analog Signal Range e V ANALOG V Drain-Source Room R On-Resistance DS(on) V D = ± V, I S = ma R DS(on) Match R DS(on Room 2 Source Off Leakage Room ± I Current S(off) V S = ± 4 V, V D = ± 4 V Drain Off Leakage Room ± I Current D(off) V D = ± 4 V, V S = ± 4 V Drain On Leakage Current Digital Control I D(on) V S = V D = ± 4 V Room ± Unit 85 Input Voltage High V INH Input Voltage Low V INL.8.8 V Input Current I INH or I INL V INH or V INL - - µa Input Capacitance C IN Room 5 pf Dynamic Characteristics Turn-On Time t ON Room V S = 2 V Turn-Off Time t OFF see switching time test circuit Room ns Charge Injection Q C L = pf, V g = V R g = Room pc Source-Off Capacitance C S(off) Room 5 V S = V, f = MHz Drain-Off Capacitance C D(off) Room 5 pf Channel On Capacitance C D(on) V D = V S = V, f = MHz Room 6 Off Isolation OIRR Room 9 C L = 5 pf, R L = Channel-to-Channel X V S = V RMS, f = khz Crosstalk TALK Room 95 db Power Supply Positive Supply Current I+ Negative Supply Current I- Power Supply Range for Continuous Operation V IN = or 5 V Room Room P ± 4.5 ± 22 ± 4.5 ± 22 V na µa 3 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

4 SPECIFICATIONS (for Single Supply) a Parameter Symbol Test Conditions Unless Specified V+ = 2 V, = V V IN = 2.4 V,.8 V f Temp. b Typ. c A Suffix - 55 C to 25 C D Suffix - 4 C to 85 C Min. d Max. d Min. d Max. d Analog Switch Analog Signal Range e V ANALOG 2 2 V Drain-Source On-Resistance R DS(on) V D = 3 V, 8 V, I S = ma Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 C, = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function. Room Dynamic Characteristics Turn-On Time t ON V S = 8 V Room ns Turn-Off Time t OFF see switching time test circuit Room C Charge Injection Q L = nf, V gen = 6 V Room 4 pc R gen = Power Supply Positive Supply Current I+ Negative Supply Current I- Power Supply Range for Continuous Operation V IN = or 5 V Room Room P V Unit µa Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

5 TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 9 V+ = 5 V = - 5 V 9 8 ± 5 V 8 7 R DS(on) (Ω) 7 6 ± V ± 5 V R DS(on) (Ω) C 85 C 25 C 4 3 ± 2 V C V D - Drain Voltage (V) R DS(on) vs. V D and Power Supply Voltages V D - Drain Voltage (V) R DS(on) vs. V D and Temperature V+ = 5 V R DS(on) (Ω) V V 2 V 5 V V TH (V) V D - Drain Voltage (V) R DS(on) vs. V D and Single Power Supply Voltages V+ Positive Supply (V) Input Switching Threshold vs. Supply Voltage 8 6 V+ = 22 V = - 22 V T A = 25 C na V+ = 5 V = - 5 V V S, V D = ± 4 V 4 I S, I D - Current (pa) 2-2 I S( of f), I D(of f) I D(on) - Current I S, I D pa pa I S( of f), I D(of f) Temperature ( C) Leakage Currents vs. Analog Voltage pa Temperature ( C) Leakage Currents vs. Temperature 5 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

6 TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 4 = V 4 3 Switching T ime (ns) 3 2 t on Switching Time (ns) 2 t off t on t of f V+ - Positive Supply (V) Switching Time vs. Single Supply Voltage ± 4 ± 8 ± 2 ± 6 ± 2 V+, Positive and Negative Supplies (V) Switching Time vs. Power Supply Voltage V+ = 5 V = - 5 V Q - Charge (pc) - V+ = 5 V = - 5 V V+ = 2 V = V OIRR (db) R L = Ω V ANALO G - Analog Voltage (V) Q S, Q D - Charge Injection vs. Analog Voltage 4 K K M M f - Frequency (Hz) Off Isolation vs. Frequency 4 I+ - Supply Current (ma) K K K M f - Frequency (Hz) Supply Current vs. Switching Frequency THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

7 TEST CIRCUITS + 5 V V S = + 2 V S V+ D Logic Input 3 V V % t r < 2 ns t f < 2 ns 3 V IN GND R L kω C L 35 pf Switch Output 9 % t OFF - 5 V R L t ON = V S R L + R DS(on) Figure 2. Switching Time + 5 V C + 5 V V S R g = Ω V, 2.4 V C S IN V+ D R L V S S R g = Ω IN V, 2.4 V S 2 NC V+ D D 2 Ω GND C V, 2.4 V IN 2 R L - 5 V GND C Off Isolation = 2 log V S C = RF bypass X TALK Isolation = 2 log V S - 5 V Figure 3. Off Isolation Figure 4. Channel-to-Channel Crosstalk + 5 V Δ R g S V+ D V g 3 V IN GND C L pf IN X ON OFF ON - 5 V Δ = measured voltage error due to charge injection The charge injection in coulombs is Q = C L x Δ Figure 5. Charge Injection 7 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

8 APPLICATIONS V+ + 5 V Logic Input Low = Sample High = Hold + 5 V kω + 5 V V IN - 5 V - LMA + 5 MΩ 5. MΩ pf 2 Ω J22 2N44 UT 3 pf DG2B - 5 V pf J J7 Aquisition T ime = 25 µs Aperature T ime = µs Sample to Hold Of fset = 5 mv Droop Rate = 5 mv/s - 5 V Figure 6. Sample-and-Hold + 5 V C 4 V 6 f C4 Select pf C 3 2 TTL Control f C3 Select f C2 Select f C Select pf C 2.5 µf C.5 µf V oltage Gain - db 8 4 f C f C2 f C3 f C4 f L f L2 f L3 f L4-5 V DG2B GND R 3 = MΩ - 4 K K K M f - Frequency (Hz) R = kω V LMA - 5 V UT A L (V oltage Gain Below Break Frequency) = f C (Break Frequency) = R 3 R = (4 db) + f L (Unity Gain Frequency) = 2πR 3 C X 2πR C X R 2 = kω 3 pf Max. Attenuation = R DS(on) kω - 47 db Figure 7. Active Low Pass Filter with Digitally Selected Break Frequency 8 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

9 APPLICATIONS + 5 V + 5 V 3 pf V IN V L V V + LMA V IN2 CH DG V DG22B + 5 V R F 8 k Ω R F 9.9 k Ω R F k Ω GND - 5 V Gain = R F + R G R G Gain (x) Gain 2 (x) Gain 3 (x) Gain 4 (x) Logic High = Switch On GND R G 2 k Ω R G2 Ω R G3 Ω Figure 8. A Precision Amplifier with Digitally Programable Input and Gains maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg? THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

10 Package Information JEDEC Part Number: MS E Dim Min Max Min Max A A B C D E e.27 BSC. BSC H L ECN: S-3946 Rev. F, 9-Jul- DWG: 53 D H C All Leads e B A L. mm.4 IN Document Number: Jul-

11 Package Information E E D S Q A A L B e B C e A 5 MAX Dim Min Max Min Max A A B B C D E E e e A L Q S ECN: S-3946 Rev. D, 9-Jul- DWG: 5482 Document Number: Jul-

12 Package Information TSSOP: 6-LEAD DIMENSIONS IN MILLIMETERS Symbols Min Nom Max A -..2 A.5..5 A B C D E E e L..6.7 L.9.. y - -. θ 3 6 ECN: S-692-Rev. D, 23-Oct-6 DWG: 5624 Document Number: Oct-6

13 PAD Pattern RECOMMENDED MINIMUM PAD FOR TSSOP-6.93 (4.9).55 (.4).28 (7.5).7 (4.35).4 (.35).26 (.65).2 (.3) Recommended Minimum Pads Dimensions in inches (mm) Revision: 2-Sep- Document Number: 635 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

14 Application Note 826 RECOMMENDED MINIMUM PADS FOR SO-6 RECOMMENDED MINIMUM PADS FOR SO (9.449).47 (.94) APPLICATION NOTE.246 (6.248).52 (3.86).22 (.559). (.27).28 (.7) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index Document Number: Revision: 2-Jan-8

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