N- and P-Channel 60-V (D-S), 175 C MOSFET

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1 N- and P-Channel -V (D-S), 75 C MOSFET Si4559EY PRODUCT SUMMARY V DS (V) R DS(on) (Ω) I D (A) N-Channel.55 at V GS = V ± at V GS = 4.5 V ± 3.9 P-Channel -.2 at V GS = - V ± 3..5 at V GS = V ± 2.8 FEATURES Halogen-free According to IEC Definition TrenchFET Power MOSFETs 75 C Maximum Junction Temperature Compliant to RoHS Directive 22/95/EC D S 2 SO-8 S 8 D G 2 7 D S 2 3 D 2 G D 2 G G 2 Top View Ordering Information: Si4559EY-T-E3 (Lead (Pb)-free) Si4559EY-T-GE3 (Lead (Pb)-free and Halogen-free) S N-Channel MOSFET D 2 P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T A = 25 C, unless otherwise noted Parameter Symbol N-Channel P-Channel Unit Drain-Source Voltage V DS - V Gate-Source Voltage V GS ± 2 ± 2 Continuous Drain Current (T J = 75 C) a T A = 25 C ± 4.5 ± 3. I D T A = 7 C ± 3.8 ± 2. A Pulsed Drain Current I DM ± 3 ± 3 Continuous Source Current (Diode Conduction) a I S T A = 25 C Maximum Power Dissipation a 2.4 P D W T A = 7 C.7 Operating Junction and Storage Temperature Range T J, T stg - 55 to 75 C THERMAL RESISTANCE RATINGS Parameter Symbol N- or P-Channel Unit Maximum Junction-to-Ambient a R thja 2.5 C/W Notes: a. Surface Mounted on FR4 board, t s. Document Number: 77 S9-389-Rev. E, 2-Jul-9

2 Si4559EY SPECIFICATIONS T J = 25 C, unless otherwise noted Parameter Symbol Test Conditions Min. Typ. a Max. Unit Static V DS = V GS, I D = 25 µa N-Ch Gate Threshold Voltage V GS(th) V DS = V GS, I D = - 25 µa P-Ch - Gate-Body Leakage I GSS V DS = V, V GS = ± 2 V Zero Gate Voltage Drain Current On-State Drain Current b I DSS I D(on) Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width 3 µs, duty cycle 2 %. N-Ch ± P-Ch ± V DS = V, V GS = V N-Ch 2 V DS = - V, V GS = V P-Ch - 2 V DS = V, V GS = V, T J = 55 C N-Ch 25 V DS = - V, V GS = V, T J = 55 C P-Ch - 25 V DS 5 V, V GS = V N-Ch 2 V DS - 5 V, V GS = - V P-Ch - 2 V GS = V, I D = 4.5 A N-Ch V GS = - V, I D = - 3. A Drain-Source On-State Resistance b P-Ch..2 R DS(on) V GS = 4.5 V, I D = 3.9 A N-Ch V GS = V, I D = A P-Ch.25.5 V DS = 5 V, I D = 4.5 A Forward Transconductance b N-Ch 3 g fs V DS = - 5 V, I D = - 3. A P-Ch 7.5 I S = 2. A, V GS = V Diode Forward Voltage b N-Ch.9.2 V SD I S = - 2. A, V GS = V P-Ch Dynamic a Total Gate Charge Q N-Channel N-Ch 9 3 g V DS = 3 V, V GS = V, I D = 4.5 A P-Ch 25 N-Ch 4 Gate-Source Charge Q gs P-Channel P-Ch 4 V DS = - 3 V, V GS = - V N-Ch 3 Gate-Drain Charge Q gd I D = - 3. A P-Ch. N-Ch 3 2 Turn-On Delay Time t d(on) N-Channel P-Ch 8 5 V DD = 3 V, R L = 3 Ω N-Ch 2 Rise Time t r I D A, V GEN = V, R g = Ω P-Ch 2 Turn-Off Delay Time Fall Time t d(off) t f P-Channel V DD = - 3 V, R L = 3 Ω N-Ch P-Ch I D - A, V GEN = - V, R g = Ω N-Ch 2 P-Ch 35 5 I F = 2 A, di/dt = A/µs N-Ch 35 Source-Drain Reverse Recovery Time t rr I F = - 2 A, di/dt = A/µs P-Ch 9 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V na µa A Ω S V nc ns 2 Document Number: 77 S9-389-Rev. E, 2-Jul-9

3 Si4559EY N-CHANNEL TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 3 3 V GS = V thru 5 V T C = - 55 C V C 5 C 2 V, V 3 V V DS - Drain-to-Source Voltage (V) Output Characteristics Transfer Characteristics R DS(on) - On-Resistance (Ω) V GS = 4.5 V V GS = V C - Capacitance (pf) 8 4 C iss C oss.25 2 C rss On-Resistance vs. Drain Current V DS - Drain-to-Source Voltage (V) Capacitance I D = 4.5 A V DS =3V R DS(on) - On-Resistance (Normalized) I D = 4.5 V V GS = V Q g - Total Gate Charge (nc) Gate Charge T J - Junction Temperature ( C) On-Resistance vs. Junction Temperature Document Number: 77 S9-389-Rev. E, 2-Jul-9 3

4 Si4559EY N-CHANNEL TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 2. I D = 4.5 A I S - Source Current (A) T J = 75 C T J = 25 C R DS(on) - On-Resistance (Ω) V SD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage V GS(th) Variance (V) I D = 25 µa Power (W) T J - Temperature ( C) Threshold Voltage.. 3 Time (s) Single Pulse Power 2 Duty Cycle =.5 Normalized Effective Transient Thermal Impedance Single Pulse Notes: P DM t t 2 t. Duty Cycle, D = t 2 2. Per Unit Base = R thja = 2.5 C/W 3. T JM - T A = P DM Z (t) thja 4. Surface Mounted Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 4 Document Number: 77 S9-389-Rev. E, 2-Jul-9

5 Si4559EY P-CHANNEL TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 3 2 V GS = V, 9 V, 8 V, 7 V, V T C = - 55 C 24-5 C V 4 V C 4 3 V V DS - Drain-to-Source Voltage (V) Output Characteristics Transfer Characteristics. 4 R DS(on) - On-Resistance (Ω) V GS = 4.5 V V GS = V C - Capacitance (pf) C rss C oss C iss On-Resistance vs. Drain Current V DS - Drain-to-Source Voltage (V) Capacitance I D = 3. A 2. I D = 3. A V DS = 3 V R DS(on) - On-Resistance (Normalized) V GS = V Q g - Total Gate Charge (nc) Gate Charge T J - Junction Temperature ( C) On-Resistance vs. Junction Temperature Document Number: 77 S9-389-Rev. E, 2-Jul-9 5

6 Si4559EY P-CHANNEL TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 2.5 I S - Source Current (A) T J = 75 C T J = 25 C R DS(on) - On-Resistance (Ω) I D = 3. A V SD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage T C = 25 C Single Pulse V GS(th) Variance (V).25. I D = 25 μa Power (W) T J - Temperature ( C) Threshold Voltage.. Time (s) Single Pulse Power 3 2 Normalized Effective Transient Thermal Impedance. Duty Cycle = Single Pulse Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient t t 2 t. Duty Cycle, D = t 2 2. Per Unit Base = R thja = 2.5 C/W 3. T JM - T A = P DM Z (t) thja maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?77. Notes: P DM 4. Surface Mounted 3 Document Number: 77 S9-389-Rev. E, 2-Jul-9

7 Package Information SOIC (NARROW): 8-LEAD JEDEC Part Number: MS E H S D A.25 mm (Gage Plane) h x 45 C All Leads e B A L q. mm.4" MILLIMETERS INCHES DIM Min Max Min Max A A B C D E e.27 BSC.5 BSC H h L q 8 8 S ECN: C-527-Rev. I, -Sep- DWG: 5498 Document Number: 792 -Sep-

8 VISHAY SILICONIX TrenchFET Power MOSFETs Application Note 88 Mounting LITTLE FOOT, SO-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 82, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs, ( for the basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. In the case of the SO-8 package, the thermal connections are very simple. Pins 5,, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are.2 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board Figure. Single MOSFET SO-8 Pad Pattern With Copper Spreading Figure 2. Dual MOSFET SO-8 Pad Pattern With Copper Spreading The minimum recommended pad patterns for the single-mosfet SO-8 with copper spreading (Figure ) and dual-mosfet SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, thermal connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least.2 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. APPLICATION NOTE Document Number: 774 Revision: 8-Jun-7

9 Application Note 82 RECOMMENDED MINIMUM PADS FOR SO-8.72 (4.39).28 (.7) APPLICATION NOTE.47 (.94).24 (.248).52 (3.8).22 (.559).5 (.27) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index Document Number: Revision: 2-Jan-8

10 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, Vishay ), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Vishay s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer s technical experts. Product specifications do not expand or otherwise modify Vishay s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2/5/EU of The European Parliament and of the Council of June 8, 2 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 22/95/EC. We confirm that all the products identified as being compliant to Directive 22/95/EC conform to Directive 2/5/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS79A standards. Please note that some Vishay documentation may still make reference to the IEC definition. We confirm that all the products identified as being compliant to IEC conform to JEDEC JS79A standards. Revision: 2-Oct-2 Document Number: 9

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