16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers

Transcription

1 DG46, DG47 6-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers DESCRIPTION The DG46 is a 6 channel single-ended analog multiplexer designed to connect one of sixteen inputs to a common output as determined by a 4-bit binary address. The DG47 selects one of eight differential inputs to a common differential output. Break-before-make switching action protects against momentary shorting of inputs. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable () function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (A x ) and enable () are TTL compatible over the full specified operating temperature range. Applications for the DG46, DG47 include high speed data acquisition, audio signal switching and routing, ATE systems, and avionics. High performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. Designed in the 44 V silicon-gate CMOS process, the absolute maximum voltage rating is extended to 44 V, allowing operation with ± 2 V supplies. Additionally single (2 V) supply operation is allowed. An epitaxial layer prevents latchup. For applications information please request documents 76 and 764. FEATURES Low on-resistance - R DS(on) : 5 Low charge injection - Q: 5 pc Fast transition time - t TRANS : 2 ns Available Low power:.2 mw Single supply capability Available 44 V supply max. rating Material categorization: For definitions of compliance please see Note * This datasheet provides information about parts that are RoHS-compliant and/or parts that are non-rohs-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information/tables in this datasheet for details. BEFITS Higher accuracy Reduced glitching Improved data throughput Reduced power consumption Increased ruggedness Wide supply ranges: ± 5 V to ± 2 V APPLICATIONS Data acquisition systems Audio signal routing Medical instrumentation ATE systems Battery powered systems High-rel systems Single supply systems FUTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG46 Dual-In-Line and SOIC Wide-Body DG47 Dual-In-Line and SOIC Wide-Body 28 D S 8 D b D a S 8a S S 7 S 8b 4 25 S 7a S S 6 S 7b 5 24 S 6a S S 5 S 6b 6 23 S 5a S S 4 S 5b 7 22 S 4a S S 3 S 4b 8 2 S 3a S 9 2 S 2 S 3b S 2a S S 9 GND A Decoders/Drivers S A S 2b S b GND 9 2 Decoders/Drivers S a A Top View Top View S3-258-Rev. K, 9-Dec-3 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

2 DG46, DG47 FUTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG46 PLCC and LCC DG47 PLCC and LCC S S S 7 S S 6 S S 5 S S 4 S 9 2 S 3 S 2 S 2 S 9 9 S Decoders/Drivers GND A 3 A 6 D S 8 S 7b S 7a S 6b S 6a S 5b S 5a S 4b S 4a S 3b S 3a S 2b S 2a S b S a GND A S 8b D b D a S 8a Decoders/Drivers Top View Top View TRUTH TABLE (DG46) A 3 A ON SWITCH X X X X None TRUTH TABLE (DG47) A ON SWITCH PAIR X X X None Notes Logic = V AL.8 V Logic = V AH 2.4 V X = Do not Care ORDERING INFORMATION (DG46) TEMP. RANGE PACKAGE PART NUMBER -4 C to 85 C 28-Pin Plastic DIP 28-Pin PLCC 28-Pin Widebody SOIC DG46DJ, DG46DJ-E3 DG46DN, DG46DN-T-E3 DG46DW, DG46DW-E3, DG46DW-T-E3 ORDERING INFORMATION (DG47) TEMP. RANGE PACKAGE PART NUMBER -4 C to 85 C 28-Pin Plastic DIP 28-Pin PLCC 28-Pin Widebody SOIC DG47DJ, DG47DJ-E3 DG47DN, DG47DN-T-E3 DG47DW, DG47DW-E3, DG47DW-T-E3 Note -T indicates Tape and Reel, -E3 indicates Lead-Free and RoHS Compliant, NO -E3 indicates standard Tin/Lead finish. S3-258-Rev. K, 9-Dec-3 2 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

3 DG46, DG47 ABSOLUTE MAXIMUM RATINGS PARAMETER LIMIT UNIT Voltages Referenced to to V - f 44 GND to -25 Digital Inputs a, V S, V D () - 2 to () + 2 V or 2 ma, whichever occurs first Current (Any terminal) 3 Peak Current, S or D (Pulsed at ms, % duty cycle max.) Storage Temperature (AK, AZ Suffix) -65 to 5 (DJ, DN Suffix) -65 to 25 Power Dissipation (Package) b 28-Pin Plastic PLCC c Pin Plastic DIP b Pin Widebody SOIC 45 Notes a. Signals on SX, DX or INX exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6 mw/ C above 75 C. d. Derate 2 mw/ C above 75 C. e. Derate 3.5 mw/ C above 75 C. f. Also applies when = GND V ma C mw S3-258-Rev. K, 9-Dec-3 3 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

4 DG46, DG47 SPECIFICATIONS a PARAMETER SYMBOL TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 5 V, = -5 V V AL =.8 V, V AH = 2.4 V f TEMP. b TYP. c D SUFFIX -4 C TO 85 C Analog Switch Analog Signal Range e V ANALOG Full V Drain-Source V R D = ± V, I S = - ma Room 5 - On-Resistance DS(on) sequence each switch on Full 5-25 R DS(on) Matching Between Channels g R DS(on) V D = ± V Room % Room Source Off Leakage Current I S(off) Full V = V Room.4 - V D = ± V DG46 Drain Off Leakage Current I V S = ± V Full D(off) Room.4 - DG47 na Full Drain On Leakage Current I D(on) Room.4 - V S = V D = ± DG46 Full sequence each switch on Room.4 - DG47 Full Digital Control Logic High Input Voltage V INH Full Logic Low Input Voltage V INL Full V Logic High Input Current I AH V A = 2.4 V, 5 V Full - - Logic Low Input Current I AL V = V, 2.4 V, V A = V Full - - μa Logic Input Capacitance C in f = MHz Room pf Dynamic Characteristics Transition Time t TRANS see figure 2 Room 2-35 Full Room Break-Before-Make Interval t OP see figure 4 Full - - ns Room 5-2 Enable Turn-On Time t ON() Full see figure 3 Room 7-5 Enable Turn-Off Time t OFF() Full Charge Injection Q V S = V, C L = nf, R S = Room pc Off Isolation h V OIRR = V, R L = k f = khz Room db Source Off Capacitance C S(off) V = V, V S = V, f = MHz Room Room Drain Off Capacitance C D(off) V = V DG47 Room V D = V Drain On Capacitance C f = MHz DG46 Room D(on) DG47 Room Power Supplies Positive Supply Current I+ Negative Supply Current I- Positive Supply Current I+ Negative Supply Current I- V = V A = or 5 V V = 2.4 V, V A = V MIN. d MAX. d Room 3-3 Full Room Full Room 5-5 Full - 7 Room Full UNIT pf μa S3-258-Rev. K, 9-Dec-3 4 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

5 DG46, DG47 SPECIFICATIONS a (for Single Supply) PARAMETER SYMBOL TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 2 V, = V V AL =.8 V, V AH = 2.4 V f TEMP. b Notes a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function. g. R DS(on) = R DS(on) max. - R DS(on) min. h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin. TYP. c D SUFFIX -4 C TO 85 C Analog Switch Analog Signal Range e V ANALOG Full - 2 V Drain-Source On-Resistance R DS(on) V D = 3 V, V, I S = - ma Room 9-2 R DS(on) Matching Between sequence each switch on Channels g R DS(on) Room % Source Off Leakage Current I S(off) V = V Room. - - Drain Off Leakage Current I D(off) V D = V or.5 V DG46 Room V S =.5 V or V DG47 Room na Drain On Leakage Current I D(on) sequence each switch on DG47 Room V S = V D = ± V DG46 Room Dynamic Characteristics Switching Time of Multiplexer t OP V S = 8 V, V S8 = V, V IN = 2.4 V Room 3-45 Enable Turn-On Time t ON() VINH = 2.4 V, V INL = V Room 25-6 ns Enable Turn-Off Time t OFF() V S = 5 V Room 5-3 Charge Injection Q C L = nf, V S = 6 V, R S = Room pc Power Supplies Positive Supply Current I+ Negative Supply Current I- V = V or 5 V, V A = V or 5 V MIN. d MAX. d Room 3-3 Full Room Full UNIT μa Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S3-258-Rev. K, 9-Dec-3 5 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

6 DG46, DG47 TYPICAL CHARACTERISTICS (T A = 25 C, unless otherwise noted) On-Resistance (Ω) R DS(on) ± 8 V ± V ± 2 V ± 5 V ± 2 V ± 5 V V D - Drain Voltage (V) - On-Resistance (Ω) R DS(on) C 85 C 25 C C - 4 C - 55 C V D - Drain Voltage (V) = 5 V = - 5 V 5 5 R DS(on) vs. V D and Supply R DS(on) vs. V D and Temperature - On-Resistance (Ω) 24 = V = 7.5 V 2 6 V 2 2 V - Current (pa) = 5 V = - 5 V V S = - V D for I D(of f) V D = V S(open) for I D(on) I S( of f) R DS(on) V 2 V 22 V I D, I S DG47 I D(on), I D(of f) DG46 I D(on), I D(of f) V D - Drain Voltage (V) R DS(on) vs. V D and Supply V S, V D - Source Drain Voltage (V) I D, I S Leakage Currents vs. Analog Voltage na 35 na = 5 V = - 5 V V D = "4 V 3 I D, I S - Current na pa pa I D(on), I D(of f) I S( of f) Time (ns) t TRA N S t ON(E N) pa 5 t OFF(E N ). pa Temperature ( C) I D, I S Leakages vs. Temperature ± 5 ± ± 5 ± 2 V SUPPL Y - Supply Voltage (V) Switching Times vs. Bipolar Supplies S3-258-Rev. K, 9-Dec-3 6 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

7 DG46, DG47 TYPICAL CHARACTERISTICS (T A = 25 C, unless otherwise noted) 7 6 = V T ime (ns) 4 3 t TRA N S Q (pc) 4 3 = 2 V, = V t ON(E N) 2 2 = 5 V, = - 5 V t OFF(E N ) Supply Voltage (V) Switching Times vs. Single Supply V S - Source Voltage (V) Charge Injection vs. Analog Voltage E N = 5 V A X = or 5 V I+ - 4 ISOL (db) I - Current (ma) I- I GND K K K M M - K K K M M f - Frequency (Hz) f - Frequency (Hz) Off-Isolation vs. Frequency Supply Currents vs. Switching Frequency = 5 V = - 5 V 22 2 Time (ns) 8 t TRA N S t ON(E N) (V) V TH 4 t OFF(E N ) Temperature ( C) t ON /t OFF vs. Temperature V SUPPLY - Supply Voltage (V) Switching Threshold vs. Supply Voltage S3-258-Rev. K, 9-Dec-3 7 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

8 DG46, DG47 SCHEMATIC DIAGRAM (Typical Channel) GND V REF D A A X Level Shift Decode/ Drive S S n Fig. TEST CIRCUITS + 5 V V S A 3 S 2 - S 5 DG46 S 6 A D GND 5 Ω 3 Ω ± V ± V 35 pf Logic Input 3 V V 5 % t r < 2 ns t f < 2 ns - 5 V + 5 V Switch Output V S V 9 % V DG47 A GND S b * S 8b D b ± V ± V V S8 t TRA N S S ON 9 % S 8 ON t TRA N S 5 Ω 3 Ω 35 pf - 5 V * = S a - S 8a, S 2b S ± 7b, D a Fig. 2 - Transition Time S3-258-Rev. K, 9-Dec-3 8 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

9 DG46, DG47 TEST CIRCUITS + 5 V A 3 A S S 2 - S 6 DG46-5 V 5 Ω GND - 5 V D 3 Ω 35 pf Logic Input 3 V V 5 % t r < 2 ns t f < 2 ns t ON() t OFF() + 5 V V A S b Sa - S8a S 2b - S 8b DG47-5 V Switch Output 9 % 9 % D a and D b GND 5 Ω 3 Ω - 5 V 35 pf Fig. 3 - Enable Switching Time + 5 V V A 3 All S and D a DG46 DG V Logic Input 3 V V 5 % t r < 2 ns t f < 2 ns 5 Ω A GND D,D b - 5 V 3 Ω 35 pf Switch Output V S V 8 % t OP Fig. 4 - Break-Before-Make Interval S3-258-Rev. K, 9-Dec-3 9 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

10 APPLICATIONS HINTS Sampling speed is limited by two consecutive events: the transition time of the multiplexer, and the settling time of the sampled signal at the output. t TRANS is given on the data sheet. Settling time at the load depends on several parameters: R DS(on) of the multiplexer, source impedance, multiplexer and load capacitances, charge injection of the multiplexer and accuracy desired. The settling time for the multiplexer alone can be derived from the model shown in figure 5. Assuming a low impedance signal source like that presented by an op amp or a buffer amplifier, the settling time of the RC network for a given accuracy is equal to n : % ACCURACY # BITS N R S = R DS(on) C D(on) UT Fig. 5 - Simplified Model of One Multiplexer Channel The maximum sampling frequency of the multiplexer is: f s = () Nt SETTLING + t TRANS where N = number of channels to scan t SETTLING = n = n x R DS(on) x C D(on) DG46, DG47 For the DG46 then, at room temp and for 2-bit accuracy, using the maximum limits: f s = (2) F s or = 694 khz (3) f s From the sampling theorem, to properly recover the original signal, the sampling frequency should be more than twice the maximum component frequency of the original signal. This assumes perfect bandlimiting. In a real application sampling at three to four times the filter cutoff frequency is a good practice. Therefore from equation 2 above: f c = -- f (4) 4 s = 73 khz From this we can see that the DG46 can be used to sample 6 different signals whose maximum component frequency can be as high as 73 khz. If for example, two channels are used to double sample the same incoming signal then its cutoff frequency can be doubled. The block diagram shown in figure 6 illustrates a typical data acquisition front end suitable for low-level analog signals. Differential multiplexing of small signals is preferred since this method helps to reject any common mode noise. This is especially important when the sensors are located at a distance and it may eliminate the need for individual amplifiers. A low R DS(on), low leakage multiplexer like the DG47 helps to reduce measurement errors. The low power dissipation of the DG47 minimizes on-chip thermal gradients which can cause errors due to temperature mismatch along the parasitic thermocouple paths. Please refer to Application Note AN23 for additional information. To Sensor To Sensor 8 Analog Multiplexer DG47 Inst Amp S/H 2-Bit A/D Converter Controller Fig. 6 - Measuring Low-Level Analog Signals is more accurate when using a Differential Multiplexing Technique maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S3-258-Rev. K, 9-Dec-3 Document Number: 76 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

11 Package Information E E S D Q A() L A B e B L C e A 5 MAX. Dim Min Max Min Max ECN: S-3946 Rev. F, 9-Jul- DWG: 5488 Document Number: Jul-

12 Package Information PLCC: 28-LEAD D-SQUARE D -SQUARE B B e D 2 DIM. MILLIMETERS IHES MIN. MAX. MIN. MAX. A B B D D D e.27 BSC.5 BSC ECN: T9-766-Rev. D, 28-Sep-9 DWG: 549 D. mm.4" A Document Number: Sep-9

13 Package Information SOIC (WIDE-BODY): 28-LEADS D CAVITY NO R R R R PIN INDICATOR dp SURFACE POLISHED DETAIL A (4 ).4..5 TYP..7.3 R ± DETAIL A All Dimensions In Inches ECN: E-229-Rev. D, -Aug- DWG: 585 Revision: -Aug- Document Number: 7268 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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