5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203. Features. General Description. Ordering Information.

Transcription

1 9-73; Rev 2; 5/98 EALUATION KIT AAILABLE 5, 8-Channel, Serial, 2-Bit ADCs General Description The are 2-bit data-acquisition systems specifically designed for use in applications with mixed +5 (analog) and +3 (digital) supply voltages. They operate with a single +5 analog supply or dual ±5 analog supplies, and combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. A 4-wire serial interface connects directly to SPI /MICROWIRE devices without external logic, and a serial strobe output allows direct connection to TMS32-family digital signal processors. The use either the internal clock or an external serial-interface clock to perform successiveapproximation analog-to-digital conversions. The serial interface operates at up to 2MHz. The MAX22 features an internal 4.96 reference, while the MAX23 requires an external reference. Both parts have a reference-buffer amplifier that simplifies gain trim. They also have a L pin that is the power supply for the digital outputs. Output logic levels (3, 3.3, or 5) are determined by the value of the voltage applied to this pin. These devices provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices. A quick turn-on time enables the to be shut down between conversions, allowing the user to optimize supply currents. By customizing powerdown between conversions, supply current can drop below µa at reduced sampling rates. The are available in 2-pin SSOP and DIP packages, and are specified for the commercial, extended, and military temperature ranges. Features 8-Channel Single-Ended or 4-Channel Differential Inputs Operates from Single +5 or Dual ±5 Supplies User-Adjustable Output Logic Levels (2.7 to 5.25) Low Power:.5mA (operating mode) 2µA (power-down mode) Internal Track/Hold, 33kHz Sampling Rate Internal 4.96 Reference (MAX22) SPI/MICROWIRE/TMS32-Compatible 4-Wire Serial Interface Software-Configurable Unipolar/Bipolar Inputs 2-Pin DIP/SSOP TOP IEW Ordering Information PART TEMP. RANGE PIN-PACKAGE INL (LSB) MAX22ACPP MAX22BCPP MAX22ACAP MAX22BCAP C to +7 C C to +7 C C to +7 C C to +7 C 2 Plastic DIP 2 Plastic DIP 2 SSOP 2 SSOP ±/2 ± ±/2 ± MAX22BC/D C to +7 C Dice* ± Ordering Information continued at end of data sheet. *Dice are specified at T A = +25 C, DC parameters only. Pin Configuration Applications CH CH DD 5/3 Mixed-Supply Systems CH2 3 8 Data Acquisition High-Accuracy Process Control CH3 CH4 4 5 MAX22 MAX SSTRB Battery-Powered Instruments CH5 6 5 Medical Instruments CH6 7 4 L CH7 8 3 GND Typical Operating Circuit appears at end of data sheet. SPI is a registered trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. SS SHDN 9 DIP/SSOP 2 REFADJ REF Maxim Integrated Products For free samples & the latest literature: or phone For small orders, phone

2 ABSOLUTE MAXIMUM RATINGS DD to GND to 6 L to ( DD +.3) SS to GND...3 to -6 DD to SS to 2 CH CH7 to GND...( SS -.3) to ( DD +.3) CH CH7 Total Input Current...±2mA REF to GND to ( DD +.3) REFADJ to GND to ( DD +.3) Digital Inputs to GND to ( DD +.3) Digital Outputs to GND to (L +.3) Digital Output Sink Current...25mA Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate.mw/ C above +7 C)...889mW SSOP (derate 8.mW/ C above +7 C)...64mW CERDIP (derate.mw C above +7 C)...889mW Operating Temperature Ranges MAX22_C_P/MAX23_C_P... C to +7 C MAX22_E_P/MAX23_E_P...-4 C to +85 C MAX22BMJP/MAX23BMJP C to +25 C Storage Temperature Range...-6 C to +5 C Lead Temperature (soldering, sec)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI ( DD = +5 ±5%, L = 2.7 to 3.6; SS = or -5 ±5%; f = 2.MHz, external clock (5% duty cycle); 5 clocks/conversion cycle (33ksps); MAX22 4.7µF capacitor at REF pin; MAX23 external reference, REF = 4.96 applied to REF pin; T A = T MIN to T MAX ; unless otherwise noted.) PARAMETER DC ACCURACY (Note ) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth SYMBOL INL DNL THD SFDR CONDITIONS MAX22A/MAX23A MAX22B/MAX23B No missing codes over temperature MAX22 (all grades) External reference, 4.96 External reference, 4.96 Channel-to-Channel ±. Offset Matching DYNAMIC SPECIFICATIONS (khz sine-wave input, 4.96p-p, 33ksps, 2.MHz external clock, bipolar-input mode) Signal-to-Noise + Distortion Ratio SINAD 7 IN = 4.96p-p, 65kHz (Note 4) -3dB rolloff MAX23A MAX23B MIN TYP MAX 2 8 ± Bits ±.5 LSB ±. ±. LSB ±3. LSB ±3 ±.5 LSB ±3 ppm/ C -8 UNITS LSB db db db db MHz khz 2

3 ELECTRICAL CHARACTERISTI (continued) ( DD = +5 ±5%, L = 2.7 to 3.6; SS = or -5 ±5%; f = 2.MHz, external clock (5% duty cycle); 5 clocks/conversion cycle (33ksps); MAX22 4.7µF capacitor at REF pin; MAX23 external reference, REF = 4.96 applied to REF pin; T A = T MIN to T MAX ; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS CONERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time t CON t ACQ Internal clock External clock, 2MHz, 2 clocks/conversion Aperture Delay Aperture Jitter Internal Clock Frequency External compensation mode, 4.7µF External Clock Frequency Range Internal compensation mode (Note 6) Used for data transfer only ANALOG INPUT Input oltage Range, Single- Unipolar, SS = Ended and Differential (Note 7) Bipolar, SS = -5 Multiplexer Leakage Current On/off leakage current, CH_ = ±5 Input Capacitance (Note 6) INTERNAL REFERENCE (MAX22 only, reference-buffer enabled) REF Output oltage T A = +25 C REF Short-Circuit Current MAX22AC REF Temperature Coefficient MAX22AE MAX22B Load Regulation (Note 8) ma to.5ma output load Capacitive Bypass at REF Internal compensation mode External compensation mode Capacitive Bypass at REFADJ REFADJ Adjustment Range EXTERNAL REFERENCE AT REF (Reference buffer disabled, REF = 4.96) Input oltage Range Input Current Input Resistance REF Input Current in Shutdown REFADJ Buffer Disable Threshold MIN TYP MAX < REF ± REF /2 ±. ± ±3 ±5 ±3 ±6 ± ± DD + 5m UNITS µs µs ns ps MHz MHz µa pf ma ppm/ C SHDN =.5 µa DD - 5m m µf µf % µa kω 3

4 ELECTRICAL CHARACTERISTI (continued) ( DD = +5 ±5%, L = 2.7 to 3.6; SS = or -5 ±5%; f = 2.MHz, external clock (5% duty cycle); 5 clocks/conversion cycle (33ksps); MAX22 4.7µF capacitor at REF pin; MAX23 external reference, REF = 4.96 applied to REF pin; T A = T MIN to T MAX ; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at REF Internal compensation mode External compensation mode 4.7 µf Reference-Buffer Gain MAX22.68 MAX23.64 / REFADJ Input Current MAX22 ±5 MAX23 ±5 µa POWER REQUIREMENTS µa Positive Supply oltage DD 5 ±5% Negative Supply oltage SS or -5 ±5% Operating mode ma Positive Supply Current Negative Supply Current Logic Supply oltage Logic Supply Current (Notes 6, ) Positive Supply Rejection (Note ) Negative Supply Rejection (Note ) Logic Supply Rejection (Note 2) I DD Fast power-down (Note 9) 3 7 Full power-down (Note 9) 2 I SS L I L PSR PSR PSR µa µa Operating mode and fast power-down 5 Full power-down µa L = DD = 5 µa DD = 5 ±5%; external reference, 4.96; full-scale input ±.6 ±.5 m SS = -5 ±5%; external reference, 4.96; full-scale input External reference, 4.96; full-scale input ±. ±.5 ±.6 ±.5 m m 4

5 ELECTRICAL CHARACTERISTI (continued) ( DD = +5 ±5%, L = 2.7 to 3.6; SS = or -5 ±5%; f = 2.MHz, external clock (5% duty cycle); 5 clocks/conversion cycle (33ksps); MAX22 4.7µF capacitor at REF pin; MAX23 external reference, REF = 4.96 applied to REF pin; T A = T MIN to T MAX ; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS:,,, SHDN,, Input High oltage IH 2.,, Input Low oltage IL.8,, Input Hysteresis HYST.5,, Input Leakage I IN IN = or DD ± µa,, Input Capacitance C IN (Note 6) 5 pf SHDN Input High oltage SH DD -.5 SHDN Input Mid-oltage SM.5 DD -.5 SHDN oltage, Floating FLT SHDN = open 2.75 SHDN Input Low oltage SHDN Input Current, High I SH SHDN = DD 4. µa SHDN Input Current, Low I SL SHDN = -4. µa SHDN Maximum Allowed Leakage, Mid-Input Output oltage Low Output oltage High Three-State Leakage Current Three-State Output Capacitance Output oltage Low Output oltage High Three-State Leakage Current Three-State Output Capacitance SL OL OH I L C OUT OL SHDN = open DIGITAL OUTPUTS:, SSTRB (L = 2.7 to 3.6) I SINK = 3mA I SINK = 6mA I SOURCE = ma = L = L (Note 6) DIGITAL OUTPUTS:, SSTRB (L = 4.75 to 5.25) OH I L C OUT I SINK = 5mA - L I SINK = 8mA.3 I SOURCE = ma = 5 ± µa = 5 (Note 6) ± na µa pf pf 5

6 TIMING CHARACTERISTI ( DD = +5 ±5%, L = 2.7 to 3.6, SS = or -5 ±5%, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER Acquisition Time to Setup to Hold Fall to Output Data alid t DO CONDITIONS Fall to Output Enable t D C LOAD = pf 24 ns Rise to Output Disable t TR C LOAD = pf 24 ns to Rise Setup t S ns to Rise Hold t H ns Pulse Width High t CH 2 ns Pulse Width Low t CL 2 ns Fall to SSTRB t SSTRB C LOAD = pf 24 ns Fall to SSTRB Output Enable (Note 6) Rise to SSTRB Output Disable (Note 6) SSTRB Rise to Rise (Note 6) SYMBOL t ACQ t DS t DH t SD t STR t SCK C LOAD = pf External-clock mode only, C LOAD = pf External-clock mode only, C LOAD = pf Internal-clock mode only MIN TYP MAX UNITS µs ns ns ns ns ns ns Note : Tested at DD = 5.; SS = ; unipolar-input mode. Note 2: Relative accuracy is the analog value s deviation (at any code) from its theoretical value after the full-scale range is calibrated. Note 3: MAX22 internal reference, offset nulled; MAX23 external reference ( REF = 4.96), offset nulled. Note 4: On-channel grounded; sine wave applied to all off-channels. Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 5% duty cycle. Note 6: Guaranteed by design. Not subject to production testing. Note 7: Common-mode range for analog inputs is from SS to DD. Note 8: External load should not change during the conversion for specified accuracy. Note 9: Shutdown supply current is measured with L at 3.3, and with all digital inputs tied to either L or GND; REFADJ = GND. Shutdown supply current is also dependent on IH (Figure 2c). Note : Logic supply current is measured with the digital outputs ( and SSTRB) disabled ( high). When the outputs are active ( low), the logic supply current depends on f, and on the static and capacitive load at and SSTRB. Note : Measured at SUPPLY + 5% and SUPPLY - 5% only. Note 2: Measured at L = 2.7 and L =

7 Typical Operating Characteristics ( DD = 5 ±5%; L = 2.7 to 3.6; SS = ; f = 2.MHz, external clock (5% duty cycle); 5 clocks/conversion cycle (33ksps); MAX22 4.7µF capacitor at REF pin; MAX23 external reference, REF = 4.96 applied to REF pin; T A = +25 C; unless otherwise noted.) SUPPLY CURRENT (ma) INL (LSB) SUPPLY CURRENT vs. SUPPLY OLTAGE MAX22 MAX SUPPLY OLTAGE () INTEGRAL NONLINEARITY vs. TEMPERATURE TEMPERATURE ( C) OFFSET-ERROR MATCHING (LSB) MAX22 TOC MAX22 TOC4 4 SUPPLY CURRENT (ma) OFFSET ERROR (LSB) CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE TEMPERATURE ( C) SUPPLY CURRENT vs. TEMPERATURE MAX22 MAX23 MAX22 TOC TEMPERATURE ( C) OFFSET ERROR vs. TEMPERATURE MAX22 TOC TEMPERATURE ( C) GAIN-ERROR MATCHING (LSB) MAX22 TOC SHUTDOWN SUPPLY CURRENT (µa) GAIN ERROR (LSB) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE REFADJ = GND FULL POWER-DOWN TEMPERATURE ( C) GAIN ERROR vs. TEMPERATURE DIFFERENTIAL SINGLE-ENDED TEMPERATURE ( C) CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE TEMPERATURE ( C) MAX22 TOC8 4 MAX22 TOC3 MAX22 TOC6 4 7

8 Typical Operating Characteristics (continued) ( DD = 5 ±5%; L = 2.7 to 3.6; SS = ; f = 2.MHz, external clock (5% duty cycle); 5 clocks/conversion cycle (33ksps); MAX22 4.7µF capacitor at REF pin; MAX23 external reference, REF = 4.96 applied to REF pin; T A = +25 C; unless otherwise noted.) INL (LSB) INTEGRAL NONLINEARITY vs. DIGITAL DIGITAL CODE 3 MAX22 TOC AMPLITUDE (db) FFT PLOT FREQUENCY (khz) SS = -5 MAX22 TOC 66.5 Pin Description PIN NAME CH CH7 SS SHDN REF REFADJ GND L SSTRB DD FUNCTION Sampling Analog Inputs Negative Supply oltage. Tie SS to -5 ±5% or to GND. Three-Level Shutdown Input. Pulling SHDN low shuts the down to µa (max) supply current; otherwise, the are fully operational. Pulling SHDN to DD puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the referencebuffer amplifier in external compensation mode. Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX22 only), the reference buffer provides a 4.96 nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to DD. Input to the Reference-Buffer Amplifier. Tie REFADJ to DD to disable the reference-buffer amplifier. Ground; IN- Input for Single-Ended Conversions Supply oltage for Digital Output Pins. oltage applied to L determines the positive output swing of the Digital Outputs (, SSTRB). 2.7 L Serial-Data Output. Data is clocked out at s falling edge. High impedance when is high. Serial-Strobe Output. In internal clock mode, SSTRB goes low when the begin the analog-to-digital conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when is high (external clock mode). Serial-Data Input. Data is clocked in at s rising edge. Active-Low Chip Select. Data is not clocked into unless is low. When is high, is high impedance. Serial-Clock Input. clocks data in and out of the serial interface. In external clock mode, also sets the conversion speed. (Duty cycle must be 4% to 6% in external clock mode.) Positive Supply oltage, +5 ±5% 8

9 +3.3 3k 3k C LOAD C LOAD GND GND a. High-Z to OH and OL to OH b. High-Z to OL and OH to OL Figure. Load Circuits for Enable Time k 3k C LOAD C LOAD GND GND SHDN CH CH CH2 CH3 CH4 CH5 CH6 CH7 GND REFADJ REF INPUT SHIFT REGISTER ANALOG INPUT MUX CONTROL LOGIC INT CLOCK T/H CLOCK IN 2-BIT SAR ADC OUT MAX22 REF MAX A.68 REFERENCE 2k (MAX22) OUTPUT SHIFT REGISTER SSTRB DD L SS a. OH to High-Z b. OL to High-Z Figure 2. Load Circuits for Disable Time Figure 3. Block Diagram Detailed Description The analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 2-bit digital output. A flexible serial interface provides easy interface to 3 microprocessors (µps). Figure 3 is the block diagram. Pseudo-Differential Input Figure 4 shows the ADC s analog comparator s sampling architecture. In single-ended mode, IN+ is internally switched to CH CH7 and IN- is switched to GND. In differential mode, IN+ and IN- are selected from pairs of CH/CH, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels using Tables 3 and 4. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential such that only the signal at IN+ is sampled. The return side (IN-) must remain stable (typically within ±.5LSB, within ±.LSB for best results) with respect to GND during a conversion. To do this, connect a.µf capacitor from IN- (of the selected analog input) to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor C HOLD. The acquisition interval spans three cycles and ends on the falling edge after the input control word s last bit is entered. The T/H switch opens at the end of the acquisition interval, retaining charge on C HOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching C HOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply GND. This unbalances node ZERO at the comparator s input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to within the limits of 2-bit resolution. This action is equivalent to transferring a charge of 6pF x [( IN +) - ( IN -)] from C HOLD to the binaryweighted capacitive DAC, which in turn forms a digital representation of the analog input signal. 9

10 Track/Hold The T/H enters tracking mode on the falling clock edge after the fifth bit of the 8-bit control word is shifted in. The T/H enters hold mode on the falling clock edge after the eighth bit of the control word is shifted in. IN- is connected to GND if the converter is set up for single-ended inputs, and the converter samples the + input. IN- connects to the - input if the converter is set up for differential inputs, and the difference of N+ - IN- is sampled. The positive input connects back to IN+, at the end of the conversion, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal s source impedance is high, acquisition time increases and more time must be allowed between conversions. The acquisition time, tacq, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by the following: tacq = 9 x (R S + R IN ) x 6pF where R IN = 9kΩ, R S = the source impedance of the input signal, and tacq is never less than.5µs. Source impedances below kω do not significantly affect the ADC s AC performance. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC s signal bandwidth. CH CH CH2 CH3 CH4 CH5 CH6 CH7 GND REF INPUT MUX 2-BIT CAPACITIE DAC C HOLD + 6pF C SWITCH TRACK T/H SWITCH ZERO 9k R IN HOLD COMPARATOR AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. SINGLE-ENDED MODE: IN+ = CHO CH7, IN- = GND. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH/CH, CH2/CH3, CH4/CH5, CH6/CH7. Figure 4. Equivalent Input Circuit +3 L DD +5 OSCILLOSCOPE.µF.µF 4.7µF GND TO 4.96 ANALOG INPUT.µF CH7 MAX22 MAX23 SS SSTRB * +3 2MHz OSCILLATOR CH CH2 CH3 CH4 SSTRB REFADJ C2.µF C 4.7µF REF SHDN N.C ** REFERENCE *FULL-SCALE ANALOG INPUT, CONERSION RESULT = $FFF (HEX). **REQUIRED FOR MAX23 ONLY. Figure 5. Quick-Look Circuit

11 Table a. Unipolar Full Scale and Zero Scale REFERENCE Internal External at REFADJ at REF ZERO SCALE *A =.68 for the MAX22,.64 for the MAX23. FULL SCALE REFADJ x A* REF Input Bandwidth The ADC s input tracking circuitry has a 4.5MHz small-signal bandwidth. Therefore it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Range and Input Protection Internal protection diodes, which clamp the analog inputs to DD and SS, allow the analog input pins to swing from (SS -.3) to (DD +.3) without damage. However, for accurate conversions near full scale, the inputs must not exceed DD by more than 5m, or be lower than SS by 5m. If the analog input exceeds 5m beyond the supplies, do not forward bias the protection diodes of off-channels more than 2mA. The full-scale input voltage depends on the voltage at REF (Tables a and b). Quick Look Use the circuit of Figure 5 to quickly evaluate the s analog performance. The require a control byte to be written to before each conversion. Tying to +3 feeds in control byte $FF hex, which triggers single-ended unipolar conversions on CH7 in external clock mode Table b. Bipolar Full Scale, Zero Scale, and Negative Full Scale REFERENCE NEGATIE FULL SCALE / 2 -/2 REFADJ x A* -/2 REF ZERO SCALE FULL SCALE Internal / 2 at +/2 REFADJ External REFADJ x A* at REF +/2 REF *A =.68 for the MAX22,.64 for the MAX23. without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the 2-bit conversion result shifts out of. arying the analog input to CH7 alters the sequence of bits from. A total of 5 clock cycles per conversion is required. All SSTRB and output transitions occur on s falling edge. How to Start a Conversion Clocking a control byte into starts conversion on the. With low, each rising edge on clocks a bit from into the MAX22/ MAX23 s internal shift register. After falls, the first logic bit defines the control byte s MSB. Until this first start bit arrives, any number of logic bits can be clocked into with no effect. Table 2 shows the control-byte format. The are fully compatible with SPI/MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = and CPHA =. MICROWIRE and SPI both transmit and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 2-bit conversion result).

12 Table 2. Control-Byte Format Bit 7 (MSB) START Bit 7 (MSB) (LSB) Bit 6 SEL 2 Name START SEL2 SEL SEL UNI/BIP SGL/DIF PD PD Bit 5 SEL Bit 4 SEL Bit 3 UNI/BIP Description Bit 2 SGL/DIF Bit PD The first logic bit after goes low defines the beginning of the control byte. These three bits select which of the eight channels is used for the conversion (Tables 3 and 4). Bit (LSB) = unipolar, = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from to REF can be converted; in bipolar mode, the signal can range from - REF / 2 to + REF / 2. = single ended, = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to GND. In differential mode, the voltage difference between two channels is measured. (Tables 3 and 4.) Selects clock and power-down modes. PD PD Mode Full power-down (I DD = 2µA, internal reference) Fast power-down (I DD = 3µA, internal reference) Internal clock mode External clock mode PD Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = ) SEL2 SEL SEL CH CH CH2 CH3 CH4 CH5 CH6 CH7 GND Table 4. Channel Selection in Differential Mode (SGL/DIF = ) SEL2 SEL SEL CH CH CH2 CH3 CH4 CH5 CH6 CH

13 Simple Software Interface Make sure the CPU s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from khz to 2MHz. ) Set up the control byte for external clock mode and call it TB. TB s format should be: XXXXX binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull on the low. 3) Transmit TB and simultaneously receive a byte and call it RB. Ignore RB. 4) Transmit a byte of all zeros ($ hex) and simultaneously receive byte RB2. 5) Transmit a byte of all zeros ($ hex) and simultaneously receive byte RB3. 6) Pull on the high. Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with one leading zero and three trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure that the total conversion time does not exceed 2µs. Digital Output In unipolar-input mode, the output is straight binary (Figure 5); for bipolar inputs, the output is two scomplement (Figure 6). Data is clocked out at s falling edge in MSB-first format. The digital output logic level is adjusted with the L pin. This allows and SSTRB to interface with 3 logic without the risk of overdrive. The s digital inputs are designed to be compatible with 5 CMOS logic as well as 3 logic. Internal and External Clock Modes The can use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the MAX22/ MAX23. The T/H acquires the input signal as the last three bits of the control byte are clocked into. Bits PD and PD of the control byte program the clock mode. Figures 7 show the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the A/D conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at on each of the next 2 falling edges (Figure 6). SSTRB and go into a high-impedance state when goes high; after the next falling edge, SSTRB outputs a logic low. Figure 8 shows SSTRB timing in external clock mode. t ACQ SSTRB START SEL2 SEL SEL UNI/ BIP SGL/ DIF PD PD RB RB2 RB3 B MSB B B9 B8 B7 B6 B5 B4 B3 B2 B B LSB FILLED WITH ZEROS ADC STATE IDLE ACQUISITION.5µs ( = 2MHz) CONERSION IDLE Figure Bit External Clock Mode Conversion Timing (MICROWIRE and SPI Compatible) 3

14 t H t S t CL t D t DS t DH t CH t DO t H t TR Figure 7. Detailed Serial-Interface Timing t SD t STR SSTRB t SSTRB t SSTRB PD CLOCKED IN Figure 8. External Clock Mode SSTRB Detailed Timing The conversion must complete in some minimum time or droop on the sample-and-hold capacitors might degrade conversion results. Use internal clock mode if the clock period exceeds µs or if serial-clock interruptions could cause the conversion interval to exceed 2µs. Internal Clock In internal clock mode, the generate their own conversion clock. This frees the µp from running the SAR conversion clock, and allows the conversion results to be read back at the processor s convenience, at any clock rate from zero to 2MHz. SSTRB goes low at the start of the conversion, then goes high when the conversion is complete. SSTRB is low for a maximum of µs, during which time should remain low for best noise performance. An internal register stores data while the conversion is in progress. clocks the data out at this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the MSB of the conversion at, followed by the remaining bits in MSB-first format (Figure 9). does not need to be held low once a 4

15 SSTRB ADC STATE START Figure 9. Internal Clock Mode Timing SEL2 SEL SEL IDLE UNI/ BIP SGL/ DIF PD PD ACQUISITION.5µs ( = 2MHz) t CON CONERSION µs MAX B MSB B B9 B2 B IDLE B LSB FILLED WITH ZEROS t H t CON t SCK t S SSTRB t SSTRB PD CLOCK IN NOTE: KEEP LOW DURING CONERSION FOR BEST NOISE PERFORMANCE. Figure. Internal Clock Mode SSTRB Detailed Timing conversion is started. Pulling high prevents data from being clocked into the and threestates, but it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when goes high. Figure shows SSTRB timing in internal clock mode. Data can be shifted in and out of the at clock rates up to 2.MHz, if t ACQ is kept above.5µs. Data Framing s falling edge does not start a conversion on the. The first logic high clocked into is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on s falling edge after the eighth bit of the control byte (the PD bit) is clocked into. The start bit is defined as one of the following: The first high bit clocked into with low anytime the converter is idle (e.g., after DD is applied). or The first high bit clocked into after bit 5 (B5) of a conversion in progress appears at. If a falling edge on forces a start bit before B5 becomes available, the current conversion is terminated and a new one started. Thus, the fastest the can run is 5 clocks/conversion. 5

16 Figure a shows the serial-interface timing necessary to perform a conversion every 5 cycles in external clock mode. If is low and is continuous, guarantee a start bit by first clocking in 6 zeros. Most microcontrollers (µcs) require that data transfers occur in multiples of eight clock cycles; 6 clocks per conversion is typically the fastest that a µc can drive the. Figure b shows the serial-interface timing necessary to perform a conversion every 6 cycles in external clock mode. Applications Information Power-On Reset When power is first applied and if SHDN is not pulled low, internal power-on reset circuitry activates the in internal clock mode, ready to convert with SSTRB = high. After the power supplies are stabilized, the internal reset time is µs. No conversions should be performed during this phase. SSTRB is high on power-up, and if is low, the first logical on is interpreted as a start bit. Until a conversion takes place, shifts out zeros. Reference-Buffer Compensation In addition to its shutdown function, SHDN also selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. Compensated or not, the minimum clock rate is khz due to droop on the sample-and-hold. Float SHDN to select external compensation. The Typical Operating Circuit uses a 4.7µF capacitor at REF. A value of 4.7µF or greater ensures stability and allows converter operation at the 2MHz full clock speed. External compensation increases power-up time (see the section Choosing Power-Down Mode, and Table 5). Internal compensation requires no external capacitor at REF, and is selected by pulling SHDN high. Internal compensation allows for the shortest power-up times, but the external clock must be limited to 4kHz during the conversion. Power-Down Choosing Power-Down Mode You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full power-down or fast power-down mode via bits and of the control byte with SHDN high or floating (Tables 2 and 6). Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits and of the control byte. Full power-down mode turns off all chip functions that draw quiescent current, reducing I DD and I SS typically to 2µA. For the MAX22, fast power-down mode turns off all circuitry except the bandgap reference. With fast power-down mode, the supply current is 3µA. Power-up time can be shortened to 5µs in internal compensation mode. Since the MAX23 does not have an internal reference, power-up times coming out of full or fast power-down are identical. IDD shutdown current can increase if any digital input (,, ) is held high in either power-down mode. The actual shutdown current depends on the state of the digital inputs, the voltage applied to the digital inputs (IH), the supply voltage (DD), and the operating temperature. Figure 2c shows the maximum IDD increase for each digital input held high in power-down mode for different operating conditions. This current is cumulative, so if all three digital inputs are held high, the additional shutdown current is three times the value shown in Figure 2c. In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Table 5 shows how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. In external compensation mode, power-up time is 2ms with a 4.7µF compensation capacitor (2ms with a 33µF capacitor) when the capacitor is initially fully discharged. From fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than /2LSB while shut down. In power-down, the capacitor has to supply the current into the reference (typically.5µa) and the transient currents at power-up. Figures 2a and 2b show the various power-down sequences in both external and internal clock modes. Software Power-Down Software power-down is activated using bits PD and PD of the control byte. As shown in Table 6, PD and PD also specify the clock mode. When software power-down is asserted, the ADC continues to operate in the last specified clock mode until the conversion is complete. The ADC then powers down into a low quiescent-current state. In internal clock mode, the interface remains active and conversion results can be clocked out even though the have already entered software power-down. The first logical on is interpreted as a start bit and powers up the. Following the start bit, the control byte also determines clock and power-down modes. For example, if the word contains PD =, the chip remains powered up. If PD =, power-down resumes after one conversion. 6

17 SSTRB 8 8 S CONTROL BYTE S CONTROL BYTE Figure a. External Clock Mode, 5 Clocks/Conversion Timing CONERSION RESULT CONERSION RESULT S CONTROL BYTE 2 B B B9 B8 B7 B6 B5 B4 B3 B2 B B B B B9 B8 B7 B6 B5 B4 B3 B2 B B S CONTROL BYTE S CONTROL BYTE B B B9 B8 B7 B6 B5 B4 B3 B2 B B B B B9 B8 B7 B6 B5 CONERSION RESULT CONERSION RESULT Figure b. External Clock Mode, 6 Clocks/Conversion Timing Hardware Power-Down The SHDN pin places the converter into full power-down mode. Unlike the software power-down modes, conversion is not completed; it stops coincidentally with SHDN being brought low. There is no power-up delay if an external reference, which is not shut down, is used. SHDN also selects internal or external reference compensation (Table 7). Power-Down Sequencing The s automatic power-down modes can save considerable power when operating at less than maximum sample rates. The following sections discuss the various power-down sequences. Lowest Power at up to 5 Conversions per Channel per Second Figure 4a depicts MAX22 power consumption for one or eight channel conversions using full power-down mode and internal reference compensation. A.µF bypass capacitor at REFADJ forms an RC filter with the internal 2kΩ reference resistor, with a.2ms time constant. To achieve full 2-bit accuracy, time constants (or 2ms in this example) are required for the reference buffer to settle. When exiting FULLPD, waiting this 2ms in FASTPD mode (instead of just exiting FULLPD mode and returning to normal operating mode) reduces power consumption by a factor of or more (Figure 3). Lowest Power at Higher Throughputs Figure 4b shows power consumption with externalreference compensation in fast power-down, with one and eight channels converted. The external 4.7µF compensation requires a 5µs wait after power-up. This circuit combines fast multichannel conversion with the lowest power consumption possible. Full power-down mode can increase power savings in applications where the are inactive for long periods of time, but where intermittent bursts of high-speed conversion are required. 7

18 CLOCK MODE SHDN MODE INTERNAL SETS EXTERNAL CLOCK MODE S X X X X X S X X X X X DATA ALID (2 DATA BITS) POWERED UP EXTERNAL Figure 2a. Timing Diagram for Power-Down Modes, External Clock SETS FAST POWER-DOWN MODE DATA ALID (2 DATA BITS) SETS EXTERNAL CLOCK MODE FAST POWER-DOWN S X X X X X POWERED UP EXTERNAL DATA INALID FULL POWER- DOWN POWERED UP Table 5. Typical Power-Up Delay Times REFERENCE BUFFER REFERENCE-BUFFER COMPENSATION MODE REF CAPACITOR (µf) POWER-DOWN MODE POWER-UP DELAY (µs) MAXIMUM SAMPLING RATE (ksps) Enabled Internal Fast 5 26 Enabled Internal Full 3 26 Enabled External 4.7 Fast/Full See Figure 4c 33 Disabled Fast 2 33 Disabled Full 2 33 Table 6. Software Shutdown and Clock Mode Table 7. Hard-Wired Shutdown and Compensation Mode PD PD DEICE MODE SHDN STATE DEICE MODE REFERENCE-BUFFER COMPENSATION Full power-down mode DD Enabled Internal compensation Fast power-down mode Floating Enabled External compensation Internal clock mode External clock mode GND Full Power-Down N/A 8

19 CLOCK MODE SSTRB MODE SETS INTERNAL CLOCK MODE DATA ALID POWERED UP Figure 2b. Timing Diagram for Power-Down Modes, Internal Clock SUPPLY CURRENT PER INPUT (µa) INTERNAL CLOCK MODE S X X X X X S X X X X X ( DD - IH ) = 2.55 ( DD - IH ) =.95 CONERSION ( DD - IH ) = 2.25 SETS FULL POWER-DOWN CONERSION DATA ALID FULL POWER-DOWN POWERED UP External and Internal References The MAX22 can be used with an internal or external reference, whereas an external reference is required for the MAX23. An external reference can be connected directly at the REF terminal, or at the REFADJ pin. An internal buffer is designed to provide 4.96 at REF for both the MAX22 and the MAX23. The MAX22 s internally trimmed 2.44 reference is buffered with a gain of.68. The MAX23 s REFADJ pin is buffered with a gain of.64, to scale an external 2.5 reference at REFADJ to 4.96 at REF. S TEMPERATURE ( C) Figure 2c. Additional I DD Shutdown Supply Current vs. IH for Each Digital Input at a Logic MAX22 Internal Reference The MAX22 s full-scale range using the internal reference is 4.96 with unipolar inputs and ±2.48 with bipolar inputs. The internal reference voltage is adjustable to ±.5% with the circuit of Figure 7. COMPLETE CONERSION SEQUENCE 2ms WAIT (ZEROS) (ZEROS) CH CH7 FULLPD FASTPD NOPD FULLPD FASTPD REFADJ REF τ = RC = 2kΩ x C REFADJ t BUFFEN 5µs Figure 3. MAX22 FULLPD/FASTPD Power-Up Sequence 9

20 AERAGE SUPPLY CURRENT (µa) FULL POWER-DOWN 2ms FASTPD WAIT 4kHz EXTERNAL CLOCK INTERNAL COMPENSATION 8 CHANNELS CHANNEL CONERSIONS PER CHANNEL PER SECOND Figure 4a. MAX22 Supply Current vs. Sample Rate/Second, FULLPD, 4kHz Clock MAX86-4A AERAGE SUPPLY CURRENT (µa), 2k 8 CHANNELS FAST POWER-DOWN 2MHz EXTERNAL CLOCK EXTERNAL COMPENSATION 5µs WAIT CHANNEL 4k 6k 8k k 2k 4k 6k 8k CONERSIONS PER CHANNEL PER SECOND Figure 4b. Supply Current vs. Sample Rate/Second, FASTPD, 2MHz Clock External Reference With both the MAX22 and MAX23, an external reference can be placed at either the input (REFADJ) or the output (REF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 2kΩ for the MAX22, and higher than kω for the MAX23, where the internal reference is omitted. At REF, the DC input resistance is a minimum of 2kΩ. During conversion, an external reference at REF must deliver up to 35µA DC load current and have an output impedance of Ω or less. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor. Using the buffered REFADJ input makes buffering of the external reference unnecessary. When connecting an external reference directly at REF, disable the internal buffer by tying REFADJ to DD. In power-down, the input bias current to REFADJ can be as much as 25µA with REFADJ tied to DD (MAX22 only). Pull REFADJ to GND to minimize the input bias current in power-down. Transfer Function and Gain Adjust Figure 5 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 6 shows the bipolar I/O transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with LSB =.m (4.96/496) for unipolar operation, and LSB =.m [(4.96/ / 2)/496] for bipolar operation. Figure 7 shows how to adjust the ADC gain in applications that use the internal reference. The circuit provides ±.5% (±65LSBs) of gain adjustment range. POWER-UP DELAY (ms) TIME IN SHUTDOWN (sec) Figure 4c. Typical Power-Up Delay vs. Time in Shutdown Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 8 shows the recommended system ground connections. Establish a single-point analog ground 2

21 OUTPUT CODE FULL-SCALE TRANSITION FS INPUT OLTAGE (LSBs) FS - 3/2LSB FS = LSB = OUTPUT CODE FS = LSB = FS INPUT OLTAGE (LSBs) +FS - LSB Figure 5. Unipolar Transfer Function, 4.96 = Full Scale Figure 6. Bipolar Transfer Function, ±4.96/2 = Full Scale ( star ground point) at GND. Connect all other analog grounds to this ground. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the power supplies can affect the ADC s high-speed comparator. Bypass these supplies to the single-point analog ground with.µf and 4.7µF bypass capacitors close to the. Minimize capacitor lead lengths for best supply-noise rejection. If the +5 power supply is very noisy, a Ω resistor can be connected as a lowpass filter, as shown in Figure MAX22 5k k REFADJ 2.µF 24k Figure 7. MAX22 Reference-Adjust Circuit 2

22 TMS32CL3x to MAX22/ MAX23 Interface Figure 9 shows an application circuit to interface the to the TMS32 in external clock mode. Figure 2 shows the timing diagram for this interface circuit. Use the following steps to initiate a conversion in the and to read the results: ) The TMS32 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS32 receive clock) as an active-high input clock. The TMS32 s CLKX and CLKR are tied together with the s input. 2) The s is driven low by the TMS32 s XF_ I/O port to enable data to be clocked into the s. 3) Write an 8-bit word (XXXXX) to the MAX22/ MAX23 to initiate a conversion and place the device into external clock mode. Refer to Table 2 to select the proper XXXXX bit values for your specific application. 4) The s SSTRB output is monitored via the TMS32 s FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the. 5) The TMS32 reads in one data bit on each of the next 6 rising edges of. These data bits represent the 2-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull high to disable the until the next conversion is initiated. SUPPLIES GND XF R* = Ω CLKX TMS32LC3x CLKR DX MAX22 MAX23 DD GND SS L +3 DGND DR MAX22 MAX23 DIGITAL CIRCUITRY FSR SSTRB *OPTIONAL Figure 8. Power-Supply Grounding Connection Figure 9. -to-tms32 Serial Interface START SEL2 SEL SEL UNI/BIP SGL/DIF PD PD SSTRB HIGH IMPEDANCE MSB B B LSB HIGH IMPEDANCE Figure 2. TMS32 Serial-Interface Timing Diagram 22

23 _Ordering Information (continued) PART MAX22AEPP MAX22BEPP MAX22AEAP MAX22BEAP MAX22BMJP MAX23ACPP MAX23BCPP MAX23ACAP TEMP. RANGE PIN-PACKAGE -4 C to +85 C 2 Plastic DIP -4 C to +85 C 2 Plastic DIP -4 C to +85 C 2 SSOP -4 C to +85 C 2 SSOP -55 C to +25 C 2 CERDIP** C to +7 C 2 Plastic DIP C to +7 C C to +7 C 2 Plastic DIP 2 SSOP MAX23BCAP C to +7 C 2 SSOP MAX23BC/D C to +7 C Dice* MAX23AEPP MAX23BEPP MAX23AEAP MAX23BEAP MAX23BMJP -4 C to +85 C 2 Plastic DIP -4 C to +85 C -4 C to +85 C 2 Plastic DIP 2 SSOP -4 C to +85 C 2 SSOP -55 C to +25 C 2 CERDIP** *Dice are specified at T A = +25 C, DC parameters only. **Contact factory for availability. INL (LSB) ±/2 ± ±/2 ± ± ±/2 ± ±/2 ± ± ±/2 ± ±/2 ± ± Typical Operating Circuit to 4.96 ANALOG INPUTS C 4.7µF C2.µF CH DD L MAX22 GND CH7 SS REF REFADJ SSTRB SHDN +5 C3.µF C4 4.7µF +3 C5.µF DD CPU I/O SCK (SK) MOSI (SO) MISO (SI) SS Chip Information TRANSISTOR COUNT: 253 SUBSTRATE CONNECTED TO SS 23

24 Package Information SSOP.EPS PDIPN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA 9486 (48) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.