INL (LSB) Maxim Integrated Products 1

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1 19-388; Rev ; 1/7 EVALUATION KIT AVAILABLE Multichannel, True-Differential, General Description The low-power, 1-bit, multichannel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H), voltage reference, and clock. The MAX11/MAX118 operate from a single +.75V to +5.5V supply, and the MAX117/MAX119 operate from a single +.7V to +3.V supply. All analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The -wire serial interface connects directly to SPI /QSPI /MICROWIRE devices without external logic. The serial strobe output () allows convenient connection to digital signal processors. The use an internal clock or an external serial-interface clock to perform successive-approximation analog-to-digital conversions. The MAX11/MAX118 include an internal +.9V reference, while the MAX117/MAX119 include an internal +.5V reference. All devices accept an external reference from 1.5V to. The provide a hardware shutdown and two software power-down modes. Using the software power-down modes allows the devices to be powered down between conversions. When powered down, accessing the serial interface automatically powers up the devices. The quick turn-on time allows power-down between all conversions. This technique reduces supply current to under 1µA for quick turn-on. The are available in a -pin TSSOP package. Applications Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Process Control Features 8-Channel Single-Ended or -Channel Differential Inputs (MAX118/MAX119) -Channel Single-Ended or -Channel Differential Inputs (MAX11/MAX117) Internal Multiplexer and T/H Single-Supply Operation.75V to 5.5V Supply (MAX11/MAX118).7V to 3.V Supply (MAX117/MAX119) Internal Reference +.9V (MAX11/MAX118) +.5V (MAX117/MAX119) 11ksps Sampling Rate Low Power 1.1mA (11ksps) 1µA (1ksps) 1µA (1ksps) 3nA (Power-Down Mode) SPI-/QSPI-/MICROWIRE Compatible -Pin TSSOP Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Ordering Information/Selector Guide PART TEMP RANGE PIN- PACKAGE INL (LSB) INPUT CHANNELS INTERNAL REFERENCE (V) PKG CODE MAX11BCUP C to +7 C TSSOP ± +.9 U-3 MAX11BEUP - C to +85 C TSSOP ± +.9 U-3 MAX117BCUP C to +7 C TSSOP ± +.5 U-3 MAX117BEUP - C to +85 C TSSOP ± +.5 U-3 MAX118BCUP C to +7 C TSSOP ± U-3 MAX118BEUP - C to +85 C TSSOP ± U-3 MAX119BCUP C to +7 C TSSOP ± U-3 MAX119BEUP - C to +85 C TSSOP ± U-3 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS to AGND, DGND...-.3V to +.V AGND to DGND...-.3V to +.3V CH CH7, COM to AGND...-.3V to ( +.3V) REF, REFADJ to AGND...-.3V to ( +.3V) Digital Inputs to DGND...-.3V to ( +.3V) Digital Outputs to DGND...-.3V to ( +.3V) Digital Output Sink Current...5mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI Continuous Power Dissipation (T A = +7 C) TSSOP (derate 1.9mW/ C above +7 C)...879mW Operating Temperature Ranges MAX11_ BC... C to +7 C MAX11_ BE...- C to +85 C Storage Temperature Range...- C to +15 C Lead Temperature (soldering, 1s)...+3 C ( = 5V (MAX11/MAX118), = 3.3V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, C REF =.µf, external +.9V reference at REF (MAX11/ MAX118), external.5v reference at REF (MAX117/MAX119), T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution 1 Bits Relative Accuracy (Note ) INL ±.7 ± LSB Differential Nonlinearity DNL No missing codes over temperature -1. ± LSB Offset Error ±1 LSB Offset Temperature Coefficient.3 ppm/ C Gain Error (Note 3) ± LSB Gain Temperature Coefficient ±.8 ppm/ C Channel-to-Channel Offset Matching ±1 LSB Channel-to-Channel Gain Matching ±1 LSB DYNAMIC SPECIFICATIONS (1kHz sine-wave input,.5vp-p, full-scale analog input, 11ksps,.1MHz external clock) Signal-to-Noise Plus Distortion Ratio SINAD db Total Harmonic Distortion THD Up to the 5th harmonic db Spurious-Free Dynamic Range SFDR 8 98 db Channel-to-Channel Crosstalk (Note ) -85 db Small-Signal Bandwidth SSBW -3dB point 3. MHz Full-Power Bandwidth FPBW SINAD > 8dB. MHz CONVERSION RATE Conversion Time (Note 5) tconv External clock,.1mhz 15 cycles 7. Internal clock 8 µs

3 ELECTRICAL CHARACTERISTI (continued) ( = 5V (MAX11/MAX118), = 3.3V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, C REF =.µf, external +.9V reference at REF (MAX11/ MAX118), external.5v reference at REF (MAX117/MAX119), T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) Throughput Rate PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS fsample Internal clock mode, 18 clocks/conversion.3 f =.1MHz clocks/conversion 51.5 External clock mode, 18 clocks/conversion 11. f =.1MHz clocks/conversion 87.5 T/H Acquisition Time tacq 1. µs Aperture Delay tad ns Aperture Jitter taj <5 ps Serial Clock Frequency f External clock mode.1.1 Internal clock mode.1 Internal Clock Frequency.1 MHz ANALOG INPUTS (CH CH7, COM) ksps MHz Input Voltage Range, Single- Unipolar, COM = VREF Ended and Differential (Note ) Bipolar, COM = VREF /, single-ended ±VREF / V Multiplexer Leakage Current On/off-leakage current, VCH_ = to VDD ±.1 ±1 µa Input Capacitance 18 pf INTERNAL REFERENCE (C REF =.µf, C REFADJ =.1µF) MAX117/MAX119, T A = +5 C REF Output Voltage V REF MAX11/MAX118, T A = +5 C REF Short-Circuit Current I REFSC REF = DGND ma V REF Tempco (Note 7) MAX11_ BC ±3 ±5 MAX11_ BE ± ± Load Regulation to.ma output load (Note 8). mv Capacitive Bypass at REF µf Capacitive Bypass at REFADJ.1 µf REFADJ Output Voltage 1.5 V REFADJ Input Range ±18 mv REFADJ Logic High Reference Buffer Voltage Gain Pull REFADJ high to disable the internal bandgap reference and reference buffer -.5V MAX117/MAX119. MAX11/MAX V ppm/ C V V/V 3

4 ELECTRICAL CHARACTERISTI (continued) ( = 5V (MAX11/MAX118), = 3.3V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, C REF =.µf, external +.9V reference at REF (MAX11/ MAX118), external.5v reference at REF (MAX117/MAX119), T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EXTERNAL REFERENCE AT REF REF Input Voltage Range V REF mV 15 5 REF Input Current I REF Shutdown.1 1 REF Input Resistance 8 kω DIGITAL INPUTS (DIN,,, SHDN) < 3.V. Input High Voltage V IH > 3.V 3. Input Low Voltage V IL.8 V Input Hysteresis V HYST. V Input Leakage I IN ±1 µa Input Capacitance C IN 1 pf DIGITAL OUTPUT (, ) Output-Voltage Low V OL I SINK = ma. V Output-Voltage High V OH I SOURCE = ma -.5 V Tri-State Leakage Current I L = ±1 µa Tri-State Output Capacitance C OUT = 1 pf POWER REQUIREMENTS MAX117/MAX Positive Supply Voltage MAX11/MAX V µa V V Supply Current (Note 8) I DD operation, fullscale Normal input Shutdown Supply Current (Note 8) External reference Internal reference at 11ksps 11ksps ksps.1 1ksps.1 Fast power-down 1 Full power-down.3 ma 1.9. ma SHDN = DGND.3 1 Power-Supply Rejection (Note 9) PSR External reference ±. mv µa

5 TIMING CHARACTERISTI ( =.75V to 5.5V (MAX11/MAX118), =.7V to 3.V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, C REF =.µf, external +.9V reference at REF for the MAX11/MAX118, external.5v reference at REF for the MAX117/MAX119, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) (Figures 1,, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIN to Setup Time t DS 5 ns DIN to Hold Time t DH ns Fall to Output Data Valid t DOV C LOAD = 5pF 1 8 ns Fall to Enable t DOE C LOAD = 5pF 1 ns Rise to Disable t DOD C LOAD = 5pF 1 ns SHDN Rise Fall to Rise Time SHDN Rise Fall to Rise Hold Time t S 5 ns t H 5 ns External clock mode.1.1 Clock Frequency f Internal clock mode.1 MHz Pulse-Width High t CH Internal clock mode 1 ns Pulse-Width Low t CL Internal clock mode 1 ns Fall to Output Enable t STE External clock mode only 1 ns Rise to Output Disable t STD External clock mode only 1 ns Rise to Rise t SCK Internal clock mode only ns Fall to Edge t ST 8 ns Pulse Width t W 1 ns Note 1: Tested at = 3.V (MAX117/MAX119) or 5.V(MAX11/MAX118); V COM = ; unipolar single-ended input mode. Note : Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset nulled. Measured with external reference. Note : On channel grounded; full-scale 1kHz sine wave applied to all off channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 5% duty cycle. (See Figures 8 11.) Note : The common-mode range for the analog inputs is from AGND to. Note 7: Digital inputs equal or DGND. Note 8: External load should not change during conversion for specified accuracy. Note 9: Measured as (V FS x 3.V) - (V FS x.7v) for the MAX117/MAX119 and (V FS x 5.5V) - (V FS x.75v) for the MAX11/MAX118. = 3.V to.7v for MAX117/MAX119 and = 5.5V to.75v for the MAX11/MAX118. 5

6 kω DGND C LOAD 5pF DGND kω C LOAD 5pF DGND a) TO V OH AND V OL TO V OH b) TO V OL AND V OH TO V OL Figure 1. Load Circuits for Enable Time t H t S t CL t CH kω DGND C LOAD 5pF DGND kω C LOAD 5pF DGND a) V OH TO b) V OL TO Figure. Load Circuits for Disable Time t W t DS f t DH t SCK DIN START SEL SEL1 SEL SGL/DIF UNI/BIP PD1 PD t DOE t ACQ t DOV t DOD D13 D1 D11 D1 D D1 D (EXTERNAL CLOCK MODE) t STE t ST t STD t ST (INTERNAL CLOCK MODE) Figure 3. Detailed Operating Characteristics

7 Typical Operating Characteristics ( = +5.V (MAX11/MAX118), = +3.3V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, external +.9V reference at REF (MAX11/MAX118), external +.5V reference at REF (MAX117/MAX119), C REF =.µf, C LOAD = 5pF, T A = +5 C, unless otherwise noted.) INL (LSB) SUPPLY CURRENT (ma) INL vs. OUTPUT CODE OUTPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX11/MAX118). 1.8 INTERNAL REFERENCE EXTERNAL REFERENCE MAX11 toc1 MAX11 toc DNL (LSB) SHUTDOWN SUPPLY CURRENT (µa) DNL vs. OUTPUT CODE OUTPUT CODE SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX117/MAX119) MAX11 toc MAX11 toc5 SUPPLY CURRENT (ma) SHUTDOWN SUPPLY CURRENT (µa) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX117/MAX119). 1.8 INTERNAL REFERENCE EXTERNAL REFERENCE SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX11/MAX118) MAX11 toc3 MAX11 toc SUPPLY CURRENT (µa) SUPPLY CURRENT vs. CONVERSION RATE FAST POWER-DOWN FULL POWER-DOWN CONVERSION RATE (ksps) MAX11 toc7 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE.5. MAX11/MAX118 INTERNAL REFERENCE MAX117/MAX119 INTERNAL REFERENCE 1.5 MAX11/MAX118 EXTERNAL REFERENCE 1. MAX117/MAX119 EXTERNAL REFERENCE TEMPERATURE ( C) MAX11 toc8 SHUTDOWN SUPPLY CURRENT (µa) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX117/MAX119 MAX11/MAX TEMPERATURE ( C) MAX11 toc9 7

8 Typical Operating Characteristics (continued) ( = +5.V (MAX11/MAX118), = +3.3V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, external +.9V reference at REF (MAX11/MAX118), external +.5V reference at REF (MAX117/MAX119), C REF =.µf, C LOAD = 5pF, T A = +5 C, unless otherwise noted.) REFERENCE VOLTAGE (V) REFERENCE VOLTAGE vs. SUPPLY VOLTAGE (MAX11/MAX118) MAX11 toc1 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE vs. SUPPLY VOLTAGE (MAX117/MAX119) MAX11 toc11 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE vs. TEMPERATURE (MAX11/MAX118) TEMPERATURE ( C) MAX11 toc1 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE vs. TEMPERATURE (MAX117/MAX119) MAX11 toc13 DELAY (µs) REFERENCE BUFFER POWER-UP DELAY vs. TIME IN SHUTDOWN C REF =.7µF C REFADJ =.1µF MAX11 toc1 AMPLITUDE (db) TEMPERATURE ( C) FFT PLOT 3 FREQUENCY (Hz) f IN = 1kHz f SAMPLE = 11ksps = 5V/3V 5 MAX11 toc15 EFFECTIVE NUMBER OF BITS TIME IN SHUTDOWN (s) EFFECTIVE NUMBER OF BITS vs. FREQUENCY FREQUENCY (khz) MAX11 toc1 8

9 Typical Operating Characteristics (continued) ( = +5.V (MAX11/MAX118), = +3.3V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, external +.9V reference at REF (MAX11/MAX118), external +.5V reference at REF (MAX117/MAX119), C REF =.µf, C LOAD = 5pF, T A = +5 C, unless otherwise noted.) OFFSET ERROR (LSB) - - OFFSET ERROR vs. SUPPLY VOLTAGE (MAX117/MAX119) MAX11 toc17 OFFSET ERROR (LSB) OFFSET ERROR vs. SUPPLY VOLTAGE (MAX11/MAX118) MAX11 toc18 GAIN ERROR vs. SUPPLY VOLTAGE (MAX117/MAX119) MAX11 toc19 GAIN ERROR vs. SUPPLY VOLTAGE (MAX11/MAX118) MAX11 toc GAIN ERROR (LSB) - GAIN ERROR (LSB) CHANNEL-TO-CHANNEL GAIN MATCHING vs. SUPPLY VOLTAGE (MAX117/MAX119) MAX11 toc1 CHANNEL-TO-CHANNEL GAIN MATCHING vs. SUPPLY VOLTAGE (MAX11/MAX118) XMAX11 toc GAIN MATCHING (LSB) - GAIN MATCHING (LSB)

10 Typical Operating Characteristics (continued) ( = +5.V (MAX11/MAX118), = +3.3V (MAX117/MAX119), SHDN =, V COM =, f =.1MHz, external clock (5% duty cycle), 18 clocks/conversion (11ksps), V REFADJ =, external +.9V reference at REF (MAX11/MAX118), external +.5V reference at REF (MAX117/MAX119), C REF =.µf, C LOAD = 5pF, T A = +5 C, unless otherwise noted.) GAIN MATCHING (LSB) - - CHANNEL-TO-CHANNEL GAIN MATCHING vs. TEMPERATURE TEMPERATURE ( C) MAX11 toc3 OFFSET MATCHING (LSB) CHANNEL-TO-CHANNEL OFFSET MATCHING vs. SUPPLY VOLTAGE (MAX117/MAX119) MAX11 toc CHANNEL-TO-CHANNEL OFFSET MATCHING vs. SUPPLY VOLTAGE (MAX11/MAX118) MAX11 toc5 CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEMPERATURE MAX11 toc OFFSET MATCHING (LSB) - OFFSET MATCHING (LSB) TEMPERATURE ( C) GAIN ERROR vs. TEMPERATURE MAX11 toc7 OFFSET ERROR vs. TEMPERATURE MAX11 toc8 GAIN ERROR (LSB) - OFFSET ERROR (LSB) TEMPERATURE ( C) TEMPERATURE ( C) 1

11 MAX118 MAX119 PIN MAX11 MAX117 NAME 1 1 CH CH1 3 3 CH CH3 5 CH CH5 7 CH 8 CH7 9 9 COM 1 1 SHDN Analog Inputs FUNCTION Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in unipolar and bipolar mode. Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current to.µa. Driving shutdown high enables the devices REF Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the MAX11/MAX118 V REF is +.9V, and the MAX117/MAX119 V REF is +.5V. 1 1 REFADJ Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a.1µf capacitor. Connect REFADJ to to disable the internal bandgap reference and referencebuffer amplifier AGND Analog Ground 1 1 DGND Digital Ground DIN Pin Description Serial Data Output. Data is clocked out at the falling edge of when is low. is high impedance when is high. Serial Strobe Output. In internal clock mode, goes low when the ADC conversion begins, and goes high when the conversion is finished. In external clock mode, pulses high for two clock periods before the MSB decision. is high impedance when is high (external clock mode). Serial Data Input. Data is clocked in at the rising edge of when is low. DIN is high impedance when is high. Active-Low Chip Select. Data is not clocked into DIN unless is low. When is high, is high impedance Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed in external clock mode. (Duty cycle must be % to %.) Positive Supply Voltage. Bypass to AGND with a.1µf capacitor. 5 8 N.C. No Connection. Not internally connected. 11

12 Detailed Description The ADCs use a successiveapproximation conversion technique and input T/H circuitry to convert an analog signal to a 1-bit digital output. A flexible serial interface provides easy interface to microprocessors (µps). Figure shows the typical application circuit and Figure 5 shows a functional diagram of the MAX118/MAX119. True-Differential Analog Input and Track/Hold The analog input architecture contains an analog input multiplexer (MUX), two T/H capacitors, T/H switches, a comparator, and two switched capacitor digital-to-analog converters (DACs) (Figure ). ANALOG INPUTS.µF CH CH1 CH CH3 CH CH5 CH CH7 REF MAX118 MAX119 SHDN DIN.1µF COM REFADJ AGND DGND.1µF Figure. Typical Application Circuit DIN SHDN CH CH1 CH CH3 CH CH5 CH CH7 COM REFADJ REF INPUT SHIFT REGISTER ANALOG INPUT MUX +1.5V BANDGAP REFERENCE CONTROL LOGIC T/H kω Figure 5. Functional Diagram IN INTERNAL CLOCK A V =.V/V CLOCK SAR ADC REF 1Ω.7µF OUTPUT SHIFT REGISTER OUT MAX119 I/O SCK I/O MOSI I/O MISO µp V SS DGND AGND In single-ended mode, the analog input MUX connects IN+ to the selected input channel and IN- to COM. In differential mode, IN+ and IN- are connected to the selected analog input pairs such as CH/CH1. Select the analog input channels according to Tables 1 5. The analog input multiplexer switches to the selected channel on the control byte s fifth falling edge. At this time, the T/H switches are in the track position and C T/H+ and C T/H- track the analog input signal. At the control byte s eighth falling edge, the MUX opens and the T/H switches move to the hold position, retaining the charge on C T/H+ and C T/H- as a sample of the input signal. See Figures 8 11 for input MUX and T/H switch positioning. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator-input voltage to within the limits of 1-bit resolution. This action requires 15 conversion clock cycles and is equivalent to transferring a charge of 18pF (V IN+ - V IN- ) from C T/H+ and C T/H- to the binary-weighted capacitive DAC, forming a digital representation of the analog input signal. After conversion, the T/H switches move from the hold position to the track position and the MUX switches back to the last specified position. In internal clock mode, the conversion is complete on the rising edge of. In external clock mode, the conversion is complete on the eighteenth falling edge. The time required for the T/H to acquire an input signal is a function of the analog input source impedance. If the input signal source impedance is high, the acquisition time lengthens. The provide three cycles (t ACQ ) in which the T/H capacitance must acquire a charge representing the input signal, typically the last three s of the control word. The input source impedance (R SOURCE ) should be minimized to allow the T/H capacitance to charge within this allotted time. t ACQ = 11.5 (R SOURCE + R IN ) C IN where R SOURCE is the analog input source impedance, R IN is.kω (which is the sum of the analog input MUX and T/H switch resistances), and C IN is 18pF (which is the sum of C T/H+, C T/H-, and input stray capacitance). To minimize sampling errors with higher source impedances, connect a 1pF capacitor from the analog input to AGND. This input capacitor reduces the input s AC impedance but forms an RC filter with the source impedance, limiting the analog input bandwidth. For larger source impedance, use a buffer amplifier such as the MAX3 to maintain analog input signal integrity. 1

13 CH CH1 CH CH3 CH CH5 CH ANALOG INPUT MUX IN+ HOLD IN- C T/H+ HOLD HOLD TRACK TRACK TRACK REF MAX118 MAX119 1-BIT CAPACITIVE DAC 1-BIT CAPACITIVE DAC C T/H- CH7 REF COM Figure. Equivalent Input Circuit Input Bandwidth The feature input tracking circuitry with a 3.MHz small-signal bandwidth. The 3.MHz input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques. To avoid high frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes clamp the analog input to and AGND. These diodes allow the analog inputs to swing from (AGND -.3V) to ( +.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 5mV below AGND or above. Note: If the analog input exceeds 5mV beyond the supply rails, limit the current to ma. Quick Look Use the circuit of Figure 7 to quickly evaluate the MAX118/MAX119. The MAX118/MAX119 require a control byte to be written to DIN using before each conversion. Connecting DIN to and clocking feeds in a control byte of $FF HEX (see Table 1). Trigger single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the output pulses high for two clock periods before the MSB of the 1-bit conversion result is shifted out of. Varying the analog input to CH7 alters the sequence of bits from. A total of 18 clock cycles are required per conversion (Figure 1). All transitions of the and outputs occur on the falling edge of. 13

14 A IN V REF 1Ω.1µF.1µF.µF CH7 REFADJ REF MAX119 V REF = +.5V MAX118 V REF = +.9V MAX118 MAX119 DIN SHDN COM DGND AGND V COM A IN V REF.1µF OSCILLOSCOPE 1Ω.7µF EXTERNAL CLOCK CH1 CH CH3 CH *FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF HEX * Figure 7. Quick-Look Circuit Table 1. Control Byte Format BIT NAME DESCRIPTION 7 (MSB) START Start bit. The first logic 1 bit after goes low defines the beginning of the control byte. SEL 5 SEL1 SEL 3 SGL/DIF UNI/BIP 1 PD1 (LSB) PD *The start bit resets power-down modes. Channel-select bits. The channel-select bits select which of the eight channels are used for the conversion (Tables, 3,, and 5). 1 = single ended, = differential. Selects single-ended or differential conversions. In single-ended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured. 1 = unipolar, = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, connect COM to AGND to perform conversion from to V REF. In bipolar mode, connect COM to V REF / to perform conversion from to V REF. See Table 7. Selects clock and power-down modes. PD1 = and PD = selects full power-down mode*. PD1 = and PD = 1 selects fast power-down mode*. PD1 = 1 and PD = selects internal clock mode. PD1 = 1 and PD = 1 selects external clock mode. 1

15 Table. MAX118/MAX119 Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL SEL1 SEL CH CH1 CH CH3 CH CH5 CH CH7 COM Table 3. MAX118/MAX119 Channel Selection in Differential Mode (SGL/DIF = ) SEL SEL1 SEL CH CH1 CH CH3 CH CH5 CH CH Table. MAX11/MAX117 Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL SEL1 SEL CH CH1 CH CH3 COM Power-On Reset When power is first applied, internal power-on reset circuitry activates the in internal clock mode, making the ready to convert with high. No conversions should be performed until the power supply is stable. The first logical 1 on DIN with low is interpreted as a start bit. Until a conversion takes place, shifts out zeros. Starting a Conversion Start a conversion by clocking a control byte into DIN. With low, a rising edge on latches a bit from DIN into the internal shift register. After falls, the first logic 1 bit defines the control Table 5. MAX11/MAX117 Channel Selection in Differential Mode (SGL/DIF = ) SEL SEL1 SEL CH CH1 CH CH byte s MSB. Until this start bit arrives, any number of logic bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers. Set CPOL = and CPHA =. MICROWIRE, SPI, and QSPI transmit a byte and receive a byte at the same time. Using the Typical Application Circuit (Figure ), the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 1-bit conversion result). 15

16 Digital Output In unipolar input mode, the digital output is straight binary (Figure 1). For bipolar input mode, the digital output is two s complement binary (Figure 15). Data is clocked out on the falling edge of in MSB-first format. Clock Modes The can use either the external serial clock or the internal clock to drive the successive-approximation conversion. The external clock shifts data in and out of the. External clock mode allows the fastest throughput rate (11ksps) and serial clock frequencies from.1mhz to.1mhz. Internal clock mode provides the best noise performance because the digital interface can be idle during conversion. The internal clock mode serial clock frequency can range from to.1mhz. Internal clock mode allows the CPU to request a conversion and clock back the results. Bits PD1 and PD of the control byte program the clock and power-down modes. The power up in internal clock mode with all circuits activated. Figures 8 11 illustrate the available clocking modes. External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the analog-todigital conversion. pulses high for two clock periods after the last bit of the control byte. Successiveapproximation bit decisions are made and the results appear at on each of the next 1 falling edges (Figures 8 and1). and go into a high-impedance state when is high. Use internal clock mode if the serial clock frequency is less than 1kHz or if serial clock interruptions could cause the conversion interval to exceed 1µs. The conversion must complete in 1µs, or droop on the T/H capacitors can degrade conversion results. Internal Clock When configured for internal clock mode, the generate an internal conversion clock. This frees the µp from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor s convenience, at any clock rate up to.1mhz. goes low at the start of the conversion and then goes high when the conversion is complete. is low for a maximum of 8.µs, during which time should remain low for best noise performance. An internal register stores data when the conversion is in progress. clocks the data out of this register at any time after the conversion is complete. After goes high, the second falling clock edge produces the MSB of the conversion at, followed by the remaining bits in MSB-first format (Figures 9 and 11). For the most accurate conversion, the MAX11 MAX119 digital I/O should remain inactive during the internal clock conversion interval (t CONV ). Do not pull high during conversion. Pulling high aborts the current conversion. To ensure that the next start bit is recognized, clock in 18 zeros at DIN. When internal clock mode is selected, does not go into a highimpedance state when goes high. A rising edge on indicates that the have finished the conversion. The µp can then read the conversion results at its convenience CB1 DIN START SEL SEL1 SEL SGL/DIF UNI/BIP PD1 PD t ACQ t CONV D13 D1 D11 D1 D9 D8 D7 D D5 D D3 D D1 D INPUT MUX SET ACCORDING TO PREVIOUS CONTROL BYTE SET TO CB1 OPEN RESET TO CB1 INPUT T/H TRACK HOLD TRACK Figure 8. External Clock Mode Clocks/Conversion Timing 1

17 DIN START SEL SEL1 SEL SGL/DIF UNI/BIP PD1 PD INPUT MUX SET ACCORDING TO PREVIOUS CONTROL BYTE INPUT T/H TRACK CB1 t ACQ SET TO CB1 t CONV OPEN RESET TO CB1 Figure 9. Internal Clock Mode Timing Clocks/Conversion Timing D13 D1 D11 D1 D9 D8 D7 D D5 D D3 D D1 D HOLD TRACK CB1 DIN START SEL SEL1 SEL SGL/DIF UNI/BIP PD1 PD CB START SEL SEL1 SEL SGL/DIF UNI/BIP PD1 PD START SEL SEL1 SEL SGL/DIF UNI/BIP t ACQ t CONV t ACQ D13 D1 D5 D D3 D D1 D D13 D1 D5 D D3 D D1 D SET ACCORDING TO PREVIOUS CONTROL BYTE INPUT MUX SET TO CB1 SET TO CB INPUT T/H HOLD TRACK HOLD TRACK HOLD Figure 1. External Clock Mode 18 Clocks/Conversion Timing Applications Information Idle Mode The device is considered idle when all the bits have been clocked out or 18 zeros have been clocked in on DIN. Start Bit The falling edge of alone does not start a conversion. The first logic high clocked into DIN with low is interpreted as a start bit and defines the first bit of the control byte. The device begins to track on the fifth falling edge of after a start bit has been recognized. A conversion starts on the eighth falling edge of as the last bit of the control byte is being clocked in. The start bit is defined as follows: 1) The first high bit clocked into DIN with low any time the converter is idle. or ) The first high bit clocked into DIN after bit 5 of a conversion in progress is clocked onto (Figures 1 and 11). Toggling before the current conversion is complete aborts the conversion and clears the output register. The fastest the can run with held low between conversions is 18 clocks per conversion. Figures 1 and 11 show the serial-interface timing necessary to perform a conversion every 18 cycles. 17

18 DIN START SEL SEL1 SEL SGL/DIFUNI/BIP PD1 PD SET ACCORDING TO PREVIOUS CONTROL BYTE INPUT MUX INPUT T/H 1 8 CB1 TRACK Shutdown and Power-Down Modes The provide a hardware shutdown and two software power-down modes. Pulling SHDN low places the converter in hardware shutdown. The conversion is immediately terminated and the supply current is reduced to 3nA. Allow ms for the device to power-up when the internal reference buffer is used with C REFADJ =.1µF and C REF =.µf. Larger capacitors on C REFADJ and C REF increase the power-up time (Table ). No wake-up time is needed for the device to power-up from fast powerdown when using an external reference. Select a software power-down mode through the PD1 and PD bits of the control byte (Table 1). When the conversion in progress is complete, software powerdown is initiated. The serial interface remains active and the last conversion result can be clocked out. In full power-down mode, only the serial interface remains operational and the supply current is reduced to 3nA. In fast power-down mode, only the bandgap reference and the serial interface remain operational, and the supply current is reduced to µa. t ACQ SET TO CB1 t CONV HOLD 1 D13 RESET TO CB1 Figure 11. Internal Clock Mode 18 Clocks/Conversion Timing Table. Internal Reference Buffer Power- Up Times vs. Bypass Capacitors C REFADJ * C REF POWER-UP TIMES FROM AN EXTENDED POWER-DOWN OPEN.1µF.7µF ms.1µf 1µF 5ms *Power-up times are dominated by C REFADJ. D D5 D D3 D D1 D TRACK CB START SEL SEL1 SEL SGL/DIF UNI/BIP PD1 PD t ACQ SET TO CB t CONV OPEN HOLD 1 The automatically wake up from software power-down when they receive the control byte s start bit (Table 1). Allow ms for the device to power-up when the internal reference buffer is used with C REFADJ =.1µF and C REF =.µf. Larger capacitors on C REFADJ and C REF increase the powerup time (Table ). No wake-up time is needed for the device to power-up from fast power-down when using an external reference. Reference Voltage The can be used with an internal or external reference voltage. The reference voltage determines the ADC input range. The reference determines the full-scale output value (Table 7). Internal Reference The contain an internal 1.5V bandgap reference. This bandgap reference is connected to REFADJ through a kω resistor. Bypass REFADJ with a.1µf capacitor to AGND. The MAX11/ MAX118 reference buffer has a 3.77V/V gain to provide +.9V at REF. The MAX117/MAX119 reference buffer has a.v/v gain to provide +.5V at REF. Bypass REF with a minimum.µf capacitor to AGND when using the internal reference. External Reference An external reference can be applied to the in two ways: 1) Disable the internal reference buffer by connecting REFADJ to and apply the external reference to REF (Figure 1). ) Utilize the internal reference buffer by applying an external reference to REFADJ (Figure 13). D13 RESET TO CB TRACK D1 1 START SEL D5 11 D 18

19 MAX11 MAX119 SAR ADC REF REFERENCE BUFFER DISABLED kω 1.5V BANDGAP REFERENCE REF DGND AGND REFADJ 3.V MAX13 OUT.1µF.1µF Figure 1. External Reference Applied to REF Method 1 allows the direct application of an external reference from 1.5V to + 5mV. The REF input impedance is typically 1kΩ. During conversion, an external reference at REF must deliver up to 1µA and have an output impedance less than 1Ω. Bypass REF with a.1µf capacitor to AGND to improve its output impedance. Method utilizes the internal reference buffer to reduce the external reference load. The REFADJ input impedance is typically kω. During a conversion, an external reference at REFADJ must deliver at least 1µA and have an output impedance less than 1Ω. The MAX11/MAX118 reference buffer has a 3.77V/V gain and the MAX117/MAX119 has a gain of.v/v. The external reference voltage at REFADJ multiplied by the reference buffer gain is the SAR ADC reference voltage. This reference appears at REF and must be from 1.5V to + 5mV. Bypass REFADJ UNIPOLAR MODE INPUT AND OUTPUT MODES ZERO SCALE FULL SCALE +5V Table 7. Full Scale and Zero Scale +5V IN GND kω 1kΩ +3.3V 51kΩ.7µF Figure 13. Reference Adjust Circuit MAX11 MAX119 REFADJ with a.1µf capacitor and bypass REF with a.µf capacitor to AGND. Transfer Function Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. Output data coding for the is binary in unipolar mode and two s complement binary in bipolar mode with 1 LSB = (V REF / N ), where N is the number of bits (1). Code transitions occur halfway between successive-integer LSB values. Figure 1 and Figure 15 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. Serial Interfaces The feature a serial interface that is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is available, establish the CPU s serial interface as a master, so that the CPU generates the serial clock for the ADCs. Select a clock frequency up to.1mhz. SPI and MICROWIRE Interface When using an SPI (Figure 1a) or MICROWIRE interface (Figure 1b), set CPOL = CPHA =. Two 8-bit readings are necessary to obtain the entire 1-bit result from the ADC. data transitions on the serial clock s falling NEGATIVE FULL SCALE BIPOLAR MODE ZERO SCALE POSITIVE FULL SCALE V Single-Ended Mode V COM V REF + V REF COM + VCOM V COM + VREF + VCOM V Differential Mode V IN- V REF + V IN- REF + V IN V IN- + VREF + V IN Note: The common mode range for the analog inputs is from AGND to. 19

20 BINARY OUTPUT CODE (LSB) V REF 1 LSB = V REF INPUT VOLTAGE (LSB) Figure 1. Unipolar Transfer Function VREF TWO'S COMPLEMENT BINARY OUTPUT CODE (LSB) V REF INPUT VOLTAGE (LSB) Figure 15. Bipolar Transfer Function 1 LSB = V REF 138 VREF edge and is clocked into the µp on s rising edge. The first 8-bit data stream contains the first 8-bits of starting with the MSB. The second 8-bit data stream contains the remaining result bits. QSPI Interface Using the high-speed QSPI interface (Figure 17) with CPOL = and CPHA =, the support a maximum f of.1mhz. One 1-bit reading is necessary to obtain the entire 1-bit result from the ADC. data transitions on the serial clock s falling edge and is clocked into the µp on s rising edge. The first 1 bits are the data. PIC1/PIC17 SSP Module Interface The are compatible with a PIC1/PIC17 microcontroller (µc), using the synchronous serial-port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 18 and configure the PIC1/PIC17 as system master. Initialize the synchronous serial-port control register (SSPCON) and synchronous serial-port status register (SSPSTAT) to the bit patterns shown in Tables 8 and 9. In SPI mode, the PIC1/PIC17 µcs allow 8 bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings are necessary to obtain the entire 1-bit result from the ADC. data transitions on the serial clock s falling edge and is clocked into the µc on s rising edge. The first 8- bit data stream contains the first 8 data bits starting with the MSB. The second data stream contains the remaining bits, D5 through D. SPI I/O SCK MISO I/O SK SI MICROWIRE SS MAX11 MAX119 MAX11 MAX119 Figure 1a. SPI Connections Figure 1b. MICROWIRE Connections

21 QSPI SCK MISO SS Figure 17. QSPI Connections MAX11 MAX119 Table 8. Detailed SSPCON Register Content CONTROL BIT PICI/PICI7 SETTINGS WCOL Bit 7 X Write collision detection bit. SSPOV Bit X Receive overflow detect bit. SSPEN Bit 5 1 MAX11 MAX119 GND SCK SDI I/O PIC1/PIC17 Figure 18. SPI Interface Connection for a PIC1/PIC17 Controller SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Synchronous serial port enable bit: : Disables serial port and configures these pins as I/O port pins. 1: E nab l es ser i al p or t and confi g ur es S C K, S D O, and S C I p i ns as ser i al - p or t p i ns. CKP Bit Clock polarity select bit. CKP = for SPI master mode selection. SSPM3 Bit 3 SSPM Bit SSPM1 Bit 1 SSPM Bit 1 Synchronous serial port mode select bit. Sets SPI master mode and selects F CLK = f OSC / 1. GND Table 9. Detailed SSPSTAT Register Content CONTROL BIT SETTINGS SMP Bit 7 SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT) SPI data input sample phase. Input data is sampled at the middle of the data output time. CKE Bit 1 SPI clock edge select bit. Data is transmitted on the rising edge of the serial clock. D/A Bit 5 X Data address bit. P Bit X Stop bit. S Bit 3 X Start bit. R/W Bit X Read/write bit information. UA Bit 1 X Update address. BF Bit X Buffer full status bit. 1

22 TMS3OLC3x Interface Figure 19 shows an application circuit to interface the to the TMS3 in external clock mode. The timing diagram for this interface circuit is shown in Figure. Use the following steps to initiate a conversion in the and to read the results: 1) The TMS3 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS3 receive clock) as an active-high input clock. CLKX and CLKR on the TMS3 are connected together with the input. ) Drive the of the low through the XF_ I/O port of the TMS3 to clock data into the DIN. 3) Write an 8-bit word (1XXXXX11) to the to initiate a conversion and place the device into external clock mode. Refer to Table 1 to select the proper XXXXX bit values for your specific application. ) The output is monitored by the FSR input of the TMS3. A falling edge on the output indicates that the conversion is in progress and data is ready to be received from the. 5) The TMS3 reads in one data bit on each of the next 1 rising edges of. These data bits represent the 1-bit conversion result followed by trailing bits, which should be ignored. ) Pull high to disable the until the next conversion is initiated. Layout, Grounding, and Bypassing Careful PC board layout is essential for best system performance. Boards should have separate analog and digital ground planes. Ensure that digital and analog signals are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the device package. Figure shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all analog grounds to the star analog ground. Connect the digital grounds to the star digital ground. Connect the digital ground point to the analog ground point directly at the device. For lowest noise operation, the ground return to the star ground s power supply should be low impedance and as short as possible. TMS3LC3x XF CLKX CLKR DX DR FSR DIN MAX11 MAX119 Figure 19. -to-tms3 Serial Interface DIN START SEL SEL1 SEL SGL/DIF UNI/BIP PD1 PD MSB B1 B1 LSB Figure. TMS3 Serial-Interface Timing Diagram

23 High-frequency noise in the power supply degrades the device s high-speed performance. Bypass the supply to the digital ground with.1µf and.7µf capacitors. Minimize capacitor lead lengths for best supply-noise rejection. Connect a 1Ω resistor in series with the.1µf capacitor to form a lowpass filter when the power supply is noisy. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the are measured using the end-point method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Aperture Definitions Aperture jitter (t AJ ) is the sample-to-sample variation in the time between the samples. Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the ADC s resolution (N bits): SNR = (. x N + 1.7)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency s RMS amplitude to RMS equivalent of all other ADC output signals. SINAD(dB) = x log (SignalRMS / NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows: ENOB = (SINAD - 1.7) /. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD V + V + V + V = log 3 5 V 1 where V 1 is the fundamental amplitude, and V through V 5 are the amplitudes of the nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Chip Information TRANSISTOR COUNT: 5589 PROCESS: BiCMOS Revision History Pages changed at Rev : 1,, 3, 5. 3

24 Multichannel, True-Differential, DIN CH3 CH1 CH TOP VIEW DGND AGND N.C. N.C. N.C. N.C REFADJ REF COM MAX11 MAX117 TSSOP SHDN DIN CH3 CH CH1 CH DGND AGND CH7 CH CH5 CH REFADJ REF COM MAX118 MAX119 TSSOP SHDN CH Pin Configurations

25 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to TSSOP.mm.EPS PACKAGE OUTLINE, TSSOP.mm BODY 1 1- I 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products.