Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters

Transcription

1 ; Rev 1; 8/7 Multichannel, 14-Bit, 2ksps Analog-to-Digital General Description The low-power, multichannel, 14- bit analog-to-digital converters (ADCs) feature a successive-approximation ADC, integrated +4.96V reference, a reference buffer, an internal oscillator, automatic power-down, and a high-speed SPI / QSPI /MICROWIRE -compatible interface. The operate with a single +5V analog supply and feature a separate digital supply, allowing direct interfacing with +2.7V to +5.5V digital logic. The consume only 3.6mA (AV DD = DV DD = +5V) at 2ksps when using an external reference. AutoShutdown reduces the supply current to 185µA at 1ksps and to less than 1µA at reduced sampling rates. The MA167 includes a 4-channel input multiplexer, and the MA168 accepts up to eight analog inputs. In addition, digital signal processor (DSP)-initiated conversions are simplified with the DSP frame-sync input and output featured in the MA168. The MA168 includes a data-bit transfer input to select between 8-bit-wide or 16- bit-wide data-transfer modes. Both devices feature a scan mode that converts each channel sequentially or one channel continuously. Excellent dynamic performance and low power, combined with ease of use and an integrated reference, make the ideal for control and dataacquisition operations or for other applications with demanding power consumption and space requirements. The MA167 is available in a 16-pin QSOP package, and the MA168 is available in a 24-pin QSOP package. Both devices are guaranteed over the commercial ( C to +7 C) and extended (-4 C to +85 C) temperature ranges. Use the MA1168 evaluation kit to evaluate the MA168. Motor Control Industrial Process Control Industrial I/O Modules Data-Acquisition Systems Thermocouple Measurements Accelerometer Measurements Applications SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. AutoShutdown is a trademark of Maxim Integrated Products, Inc. 14-Bit Resolution, ±.5 INL and ±1 DNL (max) +5V Single-Supply Operation Adjustable Logic Level (+2.7V to +5.25V) Input Voltage Range: to V REF Features Internal (+4.96V) or External (+3.8V to AV DD ) Reference Internal Track/Hold, 4MHz Input Bandwidth Internal or External Clock SPI/QSPI/MICROWIRE-Compatible Serial Interface, MA168 Performs DSP-Initiated Conversions 8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode (MA168 Only) 4-Channel (MA167) or 8-Channel (MA168) Input Mux Scan Mode Sequentially Converts Multiple Channels or One Channel Continuously Low Power 3.6mA at 2ksps 1.85mA at 1ksps 185µA at 1ksps.6µA in Full Power-Down Mode Small Package Size 16-Pin QSOP (MA167) 24-Pin QSOP (MA168) PART Ordering Information TEMP RANGE PIN- PACKAGE INL () MA167ACEE C to +7 C 16 QSOP ±.5 MA167BCEE C to +7 C 16 QSOP ±1 MA167CCEE C to +7 C 16 QSOP ±2 MA167AEEE -4 C to +85 C 16 QSOP ±.5 MA167BEEE -4 C to +85 C 16 QSOP ±1 MA167CEEE -4 C to +85 C 16 QSOP ±2 Ordering Information continued at end of data sheet. Pin Configurations appear at end of data sheet. Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAIMUM RATINGS AV DD to AGND...-.3V to +6V DV DD to DGND...-.3V to +6V DGND to AGND...-.3V to +.3V AIN_, REF, REFCAP to AGND...-.3V to (AV DD +.3V),, DSEL, DSPR, to DGND...-.3V to +6V, DSP, EOC to DGND...-.3V to (DV DD +.3V) Maximum Current into Any Pin...5mA Continuous Power Dissipation (T A = +7 C) 16-Pin QSOP (derate 8.3mW/ C above +7 C)...667mW 24-Pin QSOP (derate 9.5mW/ C above +7 C)...762mW Operating Temperature Ranges MA16 CE_... C to +7 C MA16 EE_...-4 C to +85 C Maximum Junction Temperature C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI (AV DD = DV DD = +4.75V to +5.25V, f = 4.8MHz external clock (5% duty cycle), 24 clocks/conversion (2ksps), external V REF = +4.96V, T A = T MIN to T MA, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS DC ACCURACY (Note 1) Resolution 14 Bits Relative Accuracy (Note 2) Differential Nonlinearity Transition Noise INL DNL MA16_A ±.5 ±1 MA16_B ±1. ±2 MA16_C ±1.5 ±3 No missing codes over temperature RMS noise MA16_A ±1 MA16_B MA16_C External reference.33 Internal reference.35 Offset Error ±.1 ±1 mv RMS Gain Error (Note 3) ±.1 ±.2 %FSR Offset Drift 1 ppm/ C Gain Drift (Note 3) ±1.2 ppm/ C DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.96V P-P ) (Note 1) Signal-to-Noise Plus Distortion SINAD db Signal-to-Noise Ratio SNR db Total Harmonic Distortion THD db Spurious-Free Dynamic Range SFDR db Full-Power Bandwidth -3dB point 4 MHz Full-Linear Bandwidth SINAD > 81dB 1 khz Channel-to-Channel Isolation (Note 4) 85 db CONVERSION RATE Internal clock, no data transfer, Conversion Time t CONV single conversion (Note 5) External clock 3.75 µs 2

3 ELECTRICAL CHARACTERISTI (continued) (AV DD = DV DD = +4.75V to +5.25V, f = 4.8MHz external clock (5% duty cycle), 24 clocks/conversion (2ksps), external V REF = +4.96V, T A = T MIN to T MA, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Acquisition Time t ACQ (Note 6) 729 ns External clock, data transfer and conversion Serial Clock Frequency f External clock, data transfer only 9 Internal Clock Frequency f INTCLK Internal clock MHz Aperture Delay t AD 15 ns Aperture Jitter t AJ <5 ps Sample Rate (Note 7) f S 8-bit-wide data-transfer mode bit-wide data-transfer mode Internal clock, single conversion, 8-bit-wide data-transfer mode Internal clock, single conversion, 16-bitwide data-transfer mode MHz ksps Internal clock, scan mode, 8-bit-wide datatransfer mode (four conversions) External clock, scan mode, 16-bit-wide data-transfer mode (four conversions) Duty Cycle % ANALOG INPUT (AIN_) Input Range V AIN _ V REF V Input Capacitance C AIN _ 45 pf ETERNAL REFERENCE Input Voltage Range V REF (Note 8) 3.8 AV DD.2 V V AIN _ = 34 Input Current I REF idle.1 = DV DD, idle.1 µa INTERNAL REFERENCE Reference Voltage V REFIN V Reference Short-Circuit Current I REFSC 13 ma Reference Temperature Coefficient ±25 ppm/ C Reference Wake-Up Time t RWAKE V REF = 5 ms 3

4 ELECTRICAL CHARACTERISTI (continued) (AV DD = DV DD = +4.75V to +5.25V, f = 4.8MHz external clock (5% duty cycle), 24 clocks/conversion (2ksps), external V REF = +4.96V, T A = T MIN to T MA, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS DIGITAL INPUTS (,, DSEL, DSPR, ) (DV DD = +2.7V to +5.25V) Input High Voltage V IH.7 DV DD Input Low Voltage V IL.3 DV DD Input Leakage Current I IN Digital inputs = to DV DD ±.1 ±1 µa Input Hysteresis V HYST.2 V Input Capacitance C IN 15 pf DIGITAL OUTPUT (, DSP, EOC) (DV DD = +2.7V to +5.25V) Output High Voltage V OH I SOURCE =.5mA DV DD -.4 I SINK = 1mA, DV DD = +4.75V to +5.25V.8 Output Low Voltage V OL I SINK = 1.6mA, DV DD = +2.7V to +5.25V.4 V V V V Tri-State Output Leakage Current I L = DV DD ±.1 ±1 µa Tri-State Output Capacitance C OUT = DV DD 15 pf POWER SUPPLIES Analog Supply AV DD V Digital Supply DV DD V Analog Supply Current (Note 9) I AVDD 2ksps 1ksps 1ksps 1ksps Digital Supply Current I DVDD = all zeros External reference Internal reference External reference 1.4 Internal reference 2.7 External reference.14 Internal reference 1.8 External reference.14 Internal reference 1.7 2ksps ksps.45 1ksps.45 1ksps.5 ma ma Power-Down Supply Current I AVDD + I DVDD = DV DD, =, =, DSPR = DV DD Internal reference and reference buffer on between conversions Internal reference on, reference buffer off between conversions.66.2 ma 4

5 ELECTRICAL CHARACTERISTI (continued) (AV DD = DV DD = +4.75V to +5.25V, f = 4.8MHz external clock (5% duty cycle), 24 clocks/conversion (2ksps), external V REF = +4.96V, T A = T MIN to T MA, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Shutdown Supply Current Power-Supply Rejection Ratio I AVDD + = DV DD, =, =, I DVDD DSPR = DV DD, full power-down PSRR AV DD = DV DD = 4.75V to 5.25V, full-scale input (Note 1) TIMING CHARACTERISTI (Figures 1, 2, 8, and 16).6 1 µa 63 db (AV DD = DV DD = +4.75V to +5.25V, f = 4.8MHz external clock (5% duty cycle), 24 clocks/conversion (2ksps), external V REF = +4.96V, T A = T MIN to T MA, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Acquisition Time t ACQ External clock (Note 6) 729 ns to Valid t DO C = 3pF 5 ns Fall to Enable t DV C = 3pF 8 ns Rise to Disable t TR C = 3pF 8 ns Pulse Width t W 1 ns rise to Setup t S fall (DSP) 1 ns rise to Hold t H fall (DSP) ns High Pulse Width t CH Duty cycle 45% to 55% Low Pulse Width t CL Duty cycle 45% to 55% Conversion 93 Data transfer 5 Conversion 93 Data transfer 5 Period t CP 29 ns rise to Setup t DS fall (DSP) ns ns 5 ns rise to Hold t DH fall (DSP) ns Falling to DSPR Rising t DF 1 ns DSPR to Falling Setup t FSS 1 ns DSPR to Falling Hold t FSH ns 5

6 TIMING CHARACTERISTI (Figures 1, 2, 8, and 16) (AV DD = +4.75V to +5.25V, DV DD = +2.7V to +5.25V, f = 4.8MHz external clock (5% duty cycle), 24 clocks/conversion (2ksps), external V REF = +4.96V, T A = T MIN to T MA, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Acquisition Time t ACQ External clock (Note 6) 729 ns to Valid t DO C = 3pF 1 ns Fall to Enable t DV C = 3pF 1 ns Rise to Disable t TR C = 3pF 8 ns Pulse Width t W 1 ns rise to Setup t S fall (DSP) rise to Hold t H fall (DSP) High Pulse Width t CH Duty cycle 45% to 55% Low Pulse Width t CL Duty cycle 45% to 55% Conversion 93 Data transfer 93 Conversion 93 Data transfer 93 1 ns ns Period t CP 29 ns rise to Setup t DS fall (DSP) ns ns 1 ns rise to Hold t DH fall (DSP) ns Falling to DSPR Rising t DF 1 ns DSPR to Falling Setup t FSS 1 ns DSPR to Falling Hold t FSH ns Note 1: Note 2: Note 3: Note 4: Note 5: AV DD = DV DD = +5.V. Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been calibrated. Offset and reference errors nulled. DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels. Conversion time is measured from the rising edge of the 8th external pulse to EOC transition minus t ACQ in 8-bit data-transfer mode. Note 6: See Figures 1 and 17. Note 7: f = 4.8MHz, f INTCLK = 4.MHz. Sample rate is calculated with the formula f s = n 1 (n 2 / f + n 3 / f INTCLK )-1 where: n 1 = number of scans, n 2 = number of cycles, and n 3 = number of internal clock cycles (see Figures 11 14). Note 8: Guaranteed by design, not production tested. Note 9: Internal reference and buffer are left on between conversions. Note 1: Defined as the change in the positive full scale caused by a ±5% variation in the nominal supply voltage. 6

7 Typical Operating Characteristics (AV DD = DV DD = +5V, f = 4.8MHz, C = 3pF, external V REF = +4.96V, T A = +25 C, unless otherwise noted.) INL () INL vs. CODE ,288 16,384 CODE MA167/68 toc1 DNL () DNL vs. CODE ,288 16,384 CODE MA167/68 toc2 AMPLITUDE (db) FFT AT f AIN = 1kHz FREQUENCY (khz) MA167/68 toc SINAD vs. FREQUENCY MA167/68 toc SFDR vs. FREQUENCY MA167/68 toc5-2 THD vs. FREQUENCY f SAMPLE = 2kbps MA167/68 toc SINAD (db) 5 4 SFDR (db) 6 THD (db) f SAMPLE = 2kbps 2 f SAMPLE = 2ksps FREQUENCY (khz) FREQUENCY (khz) FREQUENCY (khz) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. CONVERSION RATE (ETERNAL CLOCK) DV DD = AV DD = +5V D OUT = ALL ZEROS ETERNAL CLOCK SPI MODE.5 I AVDD, INT REF I AVDD, ET REF I DVDD CONVERSION RATE (ksps) MA167/68 toc7 IAVDD (ma) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (INTERNAL REFERENCE) DV DD = +5V f S = 2ksps T A = +85 C T A = +7 C T A = +25 C T A = C T A = -4 C AV DD (V) MA167/68 toc8 IAVDD (ma) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (ETERNAL REFERENCE) DV DD = +5V f S = 2ksps T A = +85 C T A = +7 C T A = +25 C T A = C T A = -4 C AV DD (V) MA167/68 toc9 7

8 IDVDD (ma) Typical Operating Characteristics (continued) (AV DD = DV DD = +5V, f = 4.8MHz, C = 3pF, external V REF = +4.96V, T A = +25 C, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE AV DD = +5V V IL = f S = 2ksps = = DV DD (V) MA167/68 toc1 IDVDD (µa) SHUTDOWN SUPPLY CURRENT vs. AV DD SUPPLY VOLTAGE (ETERNAL REFERENCE) DV DD = +5V POWER-DOWN SUPPLY CURRENT vs. AV DD SUPPLY VOLTAGE (INTERNAL REFERENCE) DV DD = +5V I DVDD MA167/68 toc11 I AVDD AV DD (V) MA167/68 toc IAVDD (ma) IDVDD (µa) POWER-DOWN SUPPLY CURRENT vs. DV DD SUPPLY VOLTAGE (INTERNAL REFERENCE) DV AV DD = +5V I DVDD MA167/68 toc12 I AVDD DV DD (V) SHUTDOWN SUPPLY CURRENT vs. DV DD SUPPLY VOLTAGE (ETERNAL REFERENCE) DV AV DD = +5V MA167/68 toc IAVDD (ma) IDVDD (µa) I DVDD I AVDD IAVDD (na) IDVDD (µa) I AVDD IAVDD (na) I DVDD AV DD (V) DV DD (V) IDVDD (µa) POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE (INTERNAL REFERENCE) MA167/68 toc DV DD = AV DD = +5V I AVDD I DVDD IAVDD (ma) IDVDD (µa) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (ETERNAL REFERENCE) MA167/68 toc DV DD = AV DD = +5V I AVDD I DVDD IAVDD (na) TEMPERATURE ( C) TEMPERATURE ( C) 8

9 Typical Operating Characteristics (continued) (AV DD = DV DD = +5V, f = 4.8MHz, C = 3pF, external V REF = +4.96V, T A = +25 C, unless otherwise noted.) OFFSET ERROR (µv) OFFSET ERROR vs. SUPPLY VOLTAGE AV DD (V) V REF = +4.96V MA167/68 toc17 GAIN ERROR (%FSR) GAIN ERROR vs. SUPPLY VOLTAGE AV DD (V) V REF = +4.96V MA167/68 toc18 OFFSET ERROR (µv) OFFSET ERROR vs. TEMPERATURE TEMPERATURE ( C) V REF = +4.96V MA167/68 toc19 GAIN ERROR (%FSR) GAIN ERROR vs. TEMPERATURE V REF = +4.96V MA167/68 toc2 ISOLATION (db) CHANNEL-TO-CHANNEL ISOLATION vs. FREQUENCY V REF = +4.96V MA167/68 toc21 VREF (V) INTERNAL +4.96V REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 4.14 DV DD = +5V T A = +85 C T A = +7 C T A = +25 C T A = C T A = -4 C MA167/68 toc TEMPERATURE ( C) FREQUENCY (khz) AV DD (V) IREF (µa) ETERNAL REFERENCE INPUT CURRENT vs. ETERNAL REFERENCE VOLTAGE V AIN = f = 4.8MHz AV DD = DV DD = +5V 199ksps, ETERNAL CLOCK 87.19ksps, INTERNAL CLOCK V REF (V) MA167/68 toc23 VREF (V) INTERNAL REFERENCE VOLTAGE vs. REF LOAD f = INTERNAL REFERENCE MODE LOAD APPLIED TO REF C REF = 1µF I REF (ma) MA167/68 toc24 tconv(ms) INTERNAL CLOCK CONVERSION TIME (8th RISING TO FALLING EOC) 8-BIT DATA-TRANSFER MODE 16-BIT DATA-TRANSFER MODE f = 4.8MHz NUMBER OF SCAN-MODE CONVERSIONS 6 MA167/68 toc25 9

10 MA167 PIN MA168 NAME EOC 5 7 AIN Analog Input 6 8 AIN1 Analog Input 1 FUNCTION Pin Description Serial Data Output. Data changes state on s falling edge in SPI/QSPI/MICROWIRE mode and on s rising edge in DSP mode (MA168 only). is high impedance when is high. Serial Clock Input. drives the conversion process in external clock mode and clocks data out. Serial Data Input. Use to communicate with the command/configuration/control register. In SPI/QSPI/MICROWIRE mode, the rising edge of clocks in data at. In DSP mode, the falling edge of clocks in data at. End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a conversion with the result available at. In external clock mode, EOC remains high. 7 9 AIN2 Analog Input AIN3 Analog Input REF 1 16 REFCAP Reference Voltage Input/Output. V REF sets the analog voltage range. Bypass to AGND with a 1µF capacitor. Bypass with a 1µF (min) capacitor when using the internal reference. Refer ence Byp ass C ap aci tor C onnecti on. Byp ass to AG N D w i th a.1µf cap aci tor w hen usi ng i nter nal r efer ence. Inter nal r efer ence and b uffer shut d ow n i n exter nal r efer ence m od e AGND Analog Ground. Connect to pin 18 (MA168) or pin 12 (MA167) AGND Primary Analog Ground (Star Ground). Power return for AV DD AV DD Analog Supply Voltage. Bypass to AGND with a.1µf capacitor Active-Low Chip-Select Input. Forcing high places the in shutdown with a typical supply current of.6µa. In SPI/QSPI/MICROWIRE mode, a high-to-low transition on activates normal operating mode. In DSP mode, after the initial transition from high to low, can remain low for the entire conversion process (see the Operating Modes section) DGND Digital Ground DV DD Digital Supply Voltage. Bypass to DGND with a.1µf capacitor. 1 DSPR 2 DSEL DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode. Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide datatransfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not leave DSEL unconnected. 11 AIN4 Analog Input 4 12 AIN5 Analog Input 5 1

11 MA167 PIN MA168 NAME 13 AIN6 Analog Input 6 14 AIN7 Analog Input 7 23 DSP Pin Description (continued) FUNCTION DSP Frame-Sync Transmit Output. A frame-sync pulse at DSP notifies the DSP that the data is available at. Leave DSP unconnected when not in DSP mode. 24 N.C. No Connection. Not internally connected. 1mA C LOAD = 3pF 1mA DV DD C LOAD = 3pF 1mA C LOAD = 3pF 1mA DV DD C LOAD = 3pF DGND DGND DGND DGND a) V OL TO V OH b) HIGH-Z TO VOL AND V OH TO V OL a) V OH TO HIGH-Z b) V OL TO HIGH-Z Figure 1. Load Circuits for Enable Time and -to- Delay Time Detailed Description The low-power, multichannel, 14- bit ADCs feature a successive-approximation ADC, automatic power-down, integrated +4.96V reference, and a high-speed SPI/QSPI/MICROWIRE-compatible interface. A DSPR input and DSP output allow the MA168 to communicate with DSPs with no external glue logic. The operate with a single +5V analog supply and feature a separate digital supply allowing direct interfacing with +2.7V to +5.5V digital logic. Figures 3 and 4 show the functional diagrams of the, and Figures 5 and 6 show the in a typical operating circuit. The serial interface simplifies communication with microprocessors (µps). In external reference mode, the have two power modes: normal mode and shutdown mode. Driving high places the in shutdown mode, reducing the supply current to.6µa (typ). Pull low to place the MA167/ MA168 in normal operating mode. The internal reference mode offers software-programmable, power-down options as shown in Table 5. In SPI/QSPI/MICROWIRE mode, a falling edge on wakes the analog circuitry and allows to clock in Figure 2. Load Circuits for Disable Time data. Acquisition and conversion are initiated by. The conversion result is available at in unipolar serial format. is held low until data becomes available ( first) on the 8th falling edge of when in 8-bit transfer mode, and on the 16th falling edge when in 16-bit transfer mode. See the Operating Modes section. Figure 8 shows the detailed SPI/QSPI/ MICROWIRE serial-interface timing diagram. In external clock mode, the MA168 also interfaces with DSPs. In DSP mode, a frame-sync pulse from the DSP initiates a conversion that is driven by. The MA168 formats a frame-sync pulse to notify the DSP that the conversion results are available at in -first, unipolar, serial-data format. Figure 16 shows the detailed DSP serial-interface timing diagram (see the Operating Modes section). Analog Input Figure 7 illustrates the input-sampling architecture of the ADC. The voltage applied at REF or the internal +4.96V reference sets the full-scale input voltage. Track/Hold (T/H) In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open and the capacitive digital-to-analog converter (DAC) samples the analog input. 11

12 REF AGND AIN AIN1 AIN2 AIN3 REFERENCE ANALOG-INPUT MULTIPLEER BIAS REFCAP AV DD DV DD AZ RAIL BUFFER DAC MA167 COMPARATOR ANALOG-SWITCH FINE TIMING OSCILLATOR MULTIPLEER SUCCESSIVE-APPROIMATION REGISTER OUTPUT ACCUMULATOR CONTROL EOC MEMORY INPUT REGISTER AGND DGND Figure 3. MA167 Functional Diagram During the acquisition, the analog input (AIN_) charges capacitor C DAC. At the end of the acquisition interval the T/H switches open. The retained charge on C DAC represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to zero within the limits of 14-bit resolution. At the end of the conversion, force high and then low to reset the T/H switches back to track mode (AIN_), where C DAC charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (t ACQ ) is the maximum time the device takes to acquire the signal. Use the following formula to calculate acquisition time: t ACQ = 11(R S + R IN + R DS(ON) ) 45pF +.3µs where R IN = 34Ω, R S = the input signal s source impedance, R DS(ON) = 6Ω, and t ACQ is never less than 729ns. A source impedance less than 2Ω does not significantly affect the ADC s performance. The MA168 features a 16-bit-wide data-transfer mode 12

13 REF AGND AIN AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 REFERENCE ANALOG-INPUT MULTIPLEER BIAS REFCAP AV DD DV DD AZ RAIL BUFFER DAC MA168 COMPARATOR ANALOG-SWITCH FINE TIMING OSCILLATOR MULTIPLEER SUCCESSIVE-APPROIMATION REGISTER OUTPUT ACCUMULATOR DSEL CONTROL EOC DSP DSPR MEMORY INPUT REGISTER AGND DGND Figure 4. MA168 Functional Diagram that includes a longer acquisition time (11.5 clock cycles). Longer acquisition times are useful in applications with input source resistances greater than 1kΩ. Noise increases when using large source resistances. To improve the input signal bandwidth under AC conditions, drive AIN_ with a wideband buffer (>1MHz) that can drive the ADC s input capacitance and settle quickly. Input Bandwidth The ADC s input-tracking circuitry has a 4MHz smallsignal bandwidth, making possible the digitization of high-speed transient events and the measurement of periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques. To avoid aliasing of unwanted, high-frequency signals into the frequency band of interest, use anti-alias filtering. Analog Input Protection Internal protection diodes, which clamp the analog input to AV DD or AGND, allow the input to swing from (AGND -.3V) to (AV DD +.3V) without damaging the device. If the analog input exceeds 3mV beyond the supplies, limit the input current to 1mA. 13

14 ANALOG INPUTS +5V +5V 1µF.1µF.1µF AIN AIN1 AIN2 AIN3 REF AV DD DV DD MA167 GND Figure 5. MA167 Typical Operating Circuit EOC AGND AGND DGND REFCAP EOC.1µF ANALOG INPUTS V +5V 1µF.1µF.1µF AIN AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 DSEL DSPR REF AV DD DV DD MA168 GND DSP EOC AGND AGND DGND REFCAP Figure 6. MA168 Typical Operating Circuit DSP EOC.1µF AIN_ R DSON MU C MU TRACK HOLD C SWITCH REF Figure 7. Equivalent Input Circuit CAPACITIVE DAC AUTO-ZERO RAIL Digital Interface The feature an SPI/QSPI/ MICROWIRE-compatible 3-wire serial interface. The MA167 digital interface consists of digital inputs,, and ; and outputs and EOC. The MA167 operates in the following modes: C DAC AGND HOLD ZERO TRACK SPI interface with external clock SPI interface with internal clock SPI interface with internal clock and scan mode Table 1. Command/Configuration/Control Register R IN In addition to the standard 3-wire serial interface modes, the MA168 includes a DSPR input and a DSP output for communicating with DSPs in external clock mode and a DSEL input to determine 8-bit-wide or 16-bit-wide data-transfer mode. When not using the MA168 in the DSP interface mode, connect DSPR to DVDD and leave DSP unconnected. Command/Configuration/Control Register Table 1 shows the contents of the command/configuration/control register and the state of each bit after initial power-up. Tables 2 6 define the control and configuration of the device for each bit. Cycling the power supplies resets the command/configuration/control register to the power-on-reset default state. Initialization After Power-Up A logic high on places the in the shutdown mode chosen by the power-down bits, and places in a high-impedance state. Drive low to power-up and enable the before starting a conversion. In internal reference mode, allow 5ms for the shutdown internal reference and/or buffer to wake and stabilize before starting a conversion. In external reference mode (or if the internal reference is already on), no reference settling time is needed after power-up. COMMAND POWER-UP STATE BIT7 () BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT () CH SEL2 CH SEL1 CH SEL SCAN1 SCAN REF/PD_SEL1 REF/PD SEL INT/ET CLK

15 Table 2. Channel Select BIT7 BIT6 BIT5 CHANNEL CH SEL2 CH SEL1 CH SEL AIN_ Table 4. MA168 Scan Mode, Internal Clock Only (Not for DSP Mode) ACTION BIT4 SCAN1 BIT3 SCAN Single channel, no scan Sequentially scan channels through N (N 7) Sequentially scan channels 4 through N (4 N 7) 1 1 Scan channel N 8 times 1 1 Table 3. MA167 Scan Mode, Internal Clock Only ACTION BIT4 SCAN1 BIT3 SCAN Single channel, no scan Sequentially scan channels through N (N 3) Sequentially scan channels 2 through N (2 N 3) 1 1 Scan channel N 4 times 1 1 Table 5. Power-Down Modes BIT2 REF/PD_ SEL1 BIT1 REF/PD SEL REFERENCE Internal 1 Internal 1 Internal REFERENCE MODE (INTERNAL REFERENCE) Internal reference and reference buffer stay on between conversions Internal reference and reference buffer off between conversions Internal reference on, reference buffer off between conversions TYPICAL SUPPLY CURRENT 1mA.6µA.43mA TYPICAL WAKE- UP TIME (C REF = 1µF) 1 1 External Internal reference and buffer always off.6µa NA NA 5ms 5ms Table 6. Clock Modes BIT INT/ET CLK CLOCK MODE External clock 1 Internal clock 15

16 t W t DV t S t DS t DH t CL t CH t CP t DO t H t TR Figure 8. Detailed SPI Interface Timing COMPLETE CONVERSION SEQUENCE CONVERSION CONVERSION 1 POWERED UP POWERED DOWN Figure 9. Shutdown Sequence POWERED UP Power-Down Modes Table 5 shows the power-down modes. Three internal reference modes and one external reference mode are available. Select power-down modes by writing to bits 2 and 1 in the command/configuration/control register. The enter the selected power-down mode on the rising edge of. The internal reference stays on when is pulled high, if bits 2 and 1 are set to zero. This mode allows for the fastest turn-on time. Setting bit 2 = and bit 1 = 1 turns both the reference and reference buffer off when is brought high. This mode achieves the lowest supply current. The reference and buffer wake up on the falling edge of when in SPI/QSPI/MICROWIRE mode and on the falling edge of DSPR when in DSP mode. Allow 5ms for the internal reference to rise and settle when powering up from a complete shutdown (V REF =, C REF = 1µF). The internal reference stays on and the buffer is shut off on the rising edge of when bit 2 = 1 and bit 1 =. The enter this mode on the rising edge of. The buffer wakes up on the falling edge of when in SPI/QSPI/MICROWIRE mode and on the falling edge of DSPR when in DSP mode. Allow 5ms for VREF to settle when powering up from a complete shutdown (VREF =, CREF = 1µF). VREFCAP is always equal to +4.96V in this mode. Set both bit 2 and bit 1 to 1 to turn off the reference and reference buffer to allow connection of an external reference. Using an external reference requires no extra wake-up time. Operating Modes External Clock 8-Bit-Wide Data-Transfer Mode (MA167 and MA168) Force DSPR high and DSEL low (MA168) for SPI/ QSPI/MICROWIRE-interface mode. The falling edge of wakes the analog circuitry and allows to clock in data. Ensure the duty cycle on is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure the 16

17 DSPR* DSEL* ADC STATE *MA168 ONLY t ACQ t CONV S1 S IDLE Figure 1. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing minimum high and low times are at least 93ns. External clock-mode conversions with rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. changes from high-z to logic low after is brought low. Input data latches on the rising edge of. The first rising edge begins loading data into the command/configuration/control register from. The devices select the proper channel for conversion on the rising edge of the 3rd cycle. Acquisition begins immediately thereafter and ends on the falling edge of the 6th clock cycle. The sample the input and begin conversion on the falling edge of the 6th clock cycle. Setup and configuration of the complete on the rising edge of the 8th clock cycle. The conversion result is available ( first) at on the falling edge of the 8th cycle. To read the entire conversion result, 16 cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of, cause zeros to be clocked out of. The external clock 8-bit-wide data-transfer mode requires 24 cycles for completion (Figure 1). Force high after the conversion result is read. For maximum throughput, force low again to initiate the next conversion immediately after the specified minimum time (t W ). Forcing high in the middle of a conversion immediately aborts the conversion and places the in shutdown. External Clock 16-Bit-Wide Data-Transfer Mode (MA168 Only) Force DSPR high and DSEL high for SPI/QSPI/ MICROWIRE-interface mode. Logic high at DSEL allows the MA168 to transfer data in 16-bit-wide words. The acquisition time is extended an extra eight cycles in the 16-bit-wide data-transfer mode. The falling edge of wakes the analog circuitry and allows to clock in data. Ensure the duty cycle on is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure that the minimum high and low times are at least 93ns. External-clock-mode conversions with rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. changes from high-z to logic low after is brought low. Input data latches on the rising edge of. The first rising edge begins loading data into the command/configuration/control register from. The devices select the proper channel for conversion and begin acquisition on the rising edge of the 3rd cycle. Setup and configuration of the MA168 completes on the rising edge of the 8th clock cycle. Acquisition ends on the falling edge of the 14th cycle. The MA168 samples the input and begins conversion on the falling edge of the 14th clock cycle. The conversion result is available ( first) at on the falling edge of the 16th cycle. To read the entire conversion result, 16 cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and 17

18 DSPR DSEL ADC STATE 1 8 = DON, T CARE t ACQ Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MA168 Only) t CONV S1 S IDLE INTERNAL CLK S1 S EOC ADC STATE = DON, T CARE DSPR = DV DD, DSEL = GND (MA168 ONLY) t ACQ t CONV IDLE POWER-DOWN Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing prior to the rising edge of, cause zeros to be clocked out of. The MA168 external clock 16- bit-wide data-transfer mode requires 32 cycles for completion (Figure 11). Force high after the conversion result is read. For maximum throughput, force low again to initiate the next conversion immediately after the specified minimum time (t W ). Forcing high in the middle of a conversion immediately aborts the conversion and places the MA168 in shutdown. Internal Clock 8-Bit-Wide Data-Transfer and Scan Mode (MA167 and MA168) Force DSPR high and DSEL low (MA168) for the SPI/ QSPI/MICROWIRE-interface mode. The falling edge of wakes the analog circuitry and allows to clock in data (Figure 12). changes from high-z to logic low after is brought low. Input data latches on the rising edge of. The command/configuration/control register begins reading on the first rising edge and ends on the rising edge of the 8th cycle. The select the proper channel for conversion on the rising edge of the 3rd cycle. The internal oscillator activates 125ns after the rising edge of the 8th cycle. Turn off the external clock while the internal clock is on. Turning off ensures the lowest noise performance during acquisition. Acquisition begins on the 2nd rising edge of the internal clock and ends on the falling edge of the 6th internal clock cycle. Each bit of the conversion result shifts into memory as it becomes available. The conversion result is available ( first) at on the falling edge of EOC. The internal oscillator and analog circuitry are shut down on the high-to-low EOC tran- 18

19 INTERNAL CLK EOC ADC STATE DATA CONFIGURATION = DON, T CARE DSPR = DSEL = DV DD t ACQ t CONV POWER-DOWN Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MA168 Only) S1 S INTERNAL CLK S1 S EOC ADC STATE CONFIGURATION = DON, T CARE DSPR = DV DD, DSEL = GND (MA168 ONLY) t ACQ t CONV t ACQ t CONV POWER-DOWN Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing sition. Use the EOC high-to-low transition as the signal to restart the external clock (). To read the entire conversion result, 16 cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of, cause the conversion result to be shifted out again. The internal clock 8-bit-wide datatransfer mode requires 24 external clock cycles and 25 internal clock cycles for completion. Force high after the conversion result is read. For maximum throughput, force low again to initiate the next conversion immediately after the specified minimum time (t W ). Forcing high in the middle of a conversion immediately aborts the conversion and places the in shutdown. Scan mode allows multiple channels to be scanned consecutively or one channel to be scanned eight times. Scan mode can only be enabled when using the in the internal clock mode. Enable scanning by setting bits 4 and 3 in the command/configuration/control register (see Tables 3 and 4). In scan mode, conversion results are stored in memory until the completion of the last conversion in the sequence. Upon completion of the last conversion in the sequence, EOC transitions from high to low to indicate the end of the conversion and shuts down the internal oscillator. Use the EOC high-to-low transition as the signal to restart the external clock (). provides the conversion results in the same order as the channel conversion process. The of the first conversion is available at on the falling edge of EOC (Figure 14). 19

20 Internal Clock 16-Bit-Wide Data-Transfer and Scan Mode (MA168 Only) Force DSPR high and DSEL low for the SPI/QSPI/ MICROWIRE-interface mode. The falling edge of wakes the analog circuitry and allows to clock in data (see Figure 13). changes from high-z to logic low after is brought low. Input data latches on the rising edge of. The command/configuration/control register begins reading on the first rising edge and ends on the rising edge of the 8th cycle. The MA168 selects the proper channel for conversion on the rising edge of the 3rd cycle. The internal oscillator activates 125ns after the rising edge of the 16th cycle. Turn off the external clock while the internal clock is on. Turning off ensures lowest noise performance during acquisition. Acquisition begins on the 2nd rising edge of the internal clock and ends on the falling edge of the 18th internal clock cycle. Each bit of the conversion result shifts into memory as it becomes available. The conversion result is available ( first) at on the falling edge of EOC. The internal oscillator and analog circuitry are shut down on the EOC high-to-low transition. Use the EOC high-to-low transition as the signal to restart the external clock (). To read the entire conversion result, 16 cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of, cause the conversion result to be shifted out again. The MA168 internal-clock 16-bit-wide data-transfer mode requires 32 external clock cycles and 32 internal clock cycles for completion. Force high after the conversion result is read. For maximum throughput, force low again to initiate the next conversion immediately after the specified minimum time (t W ). Forcing high in the middle of a conversion immediately aborts the conversion and places the MA168 in shutdown. Scan mode allows multiple channels to be scanned consecutively or one channel to be scanned eight times. Scan mode can only be enabled when using the MA168 in internal clock mode. Enable scanning by setting bits 4 and 3 in the command/configuration/control register (see Tables 3 and 4). In scan mode, conversion results are stored in memory until the completion of the last conversion in the sequence. Upon completion of the last conversion in the sequence, EOC transitions from high to low to indicate the end of the conversion and shuts down the internal oscillator. Use the EOC high-to-low transition as the signal to restart the external clock (). provides the conversion results in the same order as the channel conversion process. The of the first conversion is available at on the falling edge of EOC. Figure 15 shows the timing diagram for 16-bit-wide data transfer in scan mode INTERNAL CLK DATA S1 S EOC ADC STATE t ACQ t CONV t ACQ t CONV POWER-DOWN = DON, T CARE Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MA168 Only) 2

21 DSP 8-Bit-Wide Data-Transfer Mode (External Clock Mode, MA168 Only) Figure 16 shows the DSP-interface timing diagram. Logic low at DSPR on the falling edge of enables DSP interface mode. After the MA168 enters DSP mode, can remain low for the duration of the conversion process and each subsequent conversion. Drive DSEL low to select the 8-bit data-transfer mode. A sync pulse from the DSP at DSPR wakes the analog circuitry and allows to clock in data (Figure 17). The frame sync pulse alerts the MA168 that incoming data is about to be sent to. Ensure the duty cycle on is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure the minimum high and low times are at least 93ns. External clock mode conversions with rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. The input data latches on the falling edge of. The command/configuration/control register starts reading data in on the falling edge of the first cycle immediately following the falling edge of the frame sync pulse and ends on the falling edge of the 8th cycle. The MA168 selects the proper channel for conversion on the falling edge of the 3rd clock cycle and begins acquisition. Acquisition continues until the rising edge of the 7th clock cycle. The MA168 samples the input on the rising edge of the 7th clock cycle. On the rising edge of the 8th clock cycle, the MA168 outputs a frame sync pulse at DSP. The frame sync pulse alerts the DSP that the conversion results are about to be output at ( first) starting on the rising edge of the 9th clock pulse. To read the entire conversion results, 16 cycles are needed. Extra clock pulses, occuring after the conversion result has been clocked out, and prior to the next rising edge of DSPR, cause zeros to be clocked out of. The MA168 external-clock, DSP 8-bit-wide data-transfer mode requires 24 clock cycles to complete. Begin a new conversion by sending a new frame sync pulse to DSPR followed by new configuration data. Send the new DSPR pulse immediately after reading the conversion result to realize maximum throughput. Sending a new frame sync pulse in the middle of a conversion immediately aborts the current conversion and begins a new one. A rising edge on in the middle of a conversion aborts the current conversion and places the MA168 in shutdown. DSP 16-Bit-Wide Data-Transfer Mode (External Clock Mode, MA168 Only) Figure 16 shows the DSP-interface timing diagram. Logic low at DSPR on the falling edge of enables DSP interface mode. After the MA168 enters DSP mode, can remain low for the duration of the conversion process and each subsequent conversion. The acquisition time is extended an extra eight cycles in the 16-bit-wide data-transfer mode. Drive DSEL high to select the 16-bit-wide data-transfer mode. A sync pulse from the DSP at DSPR wakes the analog circuitry and allows to clock in data (Figure 18). The frame sync pulse also alerts the MA168 that incoming data is about to be sent to. Ensure the duty cycle on is between 45% and 55% when operating at t W... t DF DSPR t FSS... t FSH t S t CL t CH t H... t CP t DS t DH... t DV t DO t TR... Figure 16. Detailed DSP-Interface Timing (MA168 Only) 21

22 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure the minimum high and low times are at least 93ns. External-clock-mode conversions with rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. The input data latches on the falling edge of. The command/configuration/control register starts reading data in on the falling edge of the first cycle immediately following the falling edge of the frame sync pulse and ends on the falling edge of the 16th cycle. The MA168 selects the proper channel for conversion on the falling edge of the 3rd clock cycle and begins acquisition. Acquisition continues until the rising edge of the 15th clock cycle. The MA168 samples the input on the rising edge of the 15th clock cycle. On the rising edge of the 16th clock cycle, the MA168 outputs a frame sync pulse at DSP. The frame sync pulse alerts the DSP that the conversion results are about to be output at ( first) starting on the rising edge of the 17th clock pulse. To read the entire conversion result, 16 cycles are needed. Extra clock pulses, occuring after the conversion result has been clocked out and prior to the next rising edge of DSPR, cause zeros to be clocked out of. The MA168 external clock, DSP 16-bit-wide data-transfer mode requires 32 clock cycles to complete. Begin a new conversion by sending a new frame sync pulse to DSPR followed by new configuration data. Send the new DSPR pulse immediately after reading the conversion result to realize maximum throughput. Sending a new frame sync pulse in the middle of a conversion immediately aborts the current conversion and begins a new one. A rising edge on in the middle of a conversion aborts the current conversion and places the MA168 in shutdown. DSPR S1 S DSP ADC STATE t ACQ t CONV IDLE Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MA168 Only) DSPR S1 S DSP ADC STATE = DON, T CARE t ACQ t CONV IDLE Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MA168 Only) 22

23 Output Coding and Transfer Function The data output from the is straight binary. Figure 19 shows the nominal transfer function. Code transitions occur halfway between successive integer values (VREF = +4.96V, and 1 = +25µV or 4.96V / 16,384V). Applications Information Internal Reference The internal bandgap reference provides a buffered +4.96V. Bypass REFCAP with a.1µf capacitor to AGND and REF with a 1µF capacitor to AGND. For best results, use low-esr, 5R/7R ceramic capacitors. Allow 5ms for the reference and buffer to wake up from full power-down (see Table 5). External Reference The accept an external reference with a voltage range between +3.8V and AV DD. Connect the external reference directly to REF. Bypass REF to AGND with a 1µF capacitor. When not using a low-esr bypass capacitor, use a.1µf ceramic capacitor in parallel with the 1µF capacitor. Noise on the reference degrades conversion accuracy. The input impedance at REF is 37kΩ for DC currents. During a conversion, the external reference at REF must deliver 118µA of DC load current and have an output impedance of 1Ω or less. For optimal performance, buffer the reference through an op amp and bypass the REF input. Consider the equivalent input noise (82µV RMS ) of the MA167/ MA168 when choosing a reference. Internal/External Oscillator Select either an external (.1MHz to 4.8MHz) or the internal 4MHz (typ) clock to perform conversions (Table 6). The external clock shifts data in and out of the in either clock mode. When using the internal clock mode, the internal oscillator controls the acquisition and conversion processes, while the external oscillator shifts data in and out of the. Turn off the external clock () when the internal clock is on to realize lowest noise performance. The internal clock remains off in external clock mode. OUTPUT CODE FULL-SCALE TRANSITION FS INPUT VOLTAGE () FS - 3/2 FS = V REF 1 = V REF 16,384 Figure 19. Unipolar Transfer Function, Full Scale (FS) = V REF, Zero Scale (ZS) = GND Input Buffer Most applications require an input-buffer amplifier to achieve 14-bit accuracy. The input amplifier must have a slew rate of at least 2V/µs and a unity-gain bandwidth of at least 1MHz to complete the required output-voltage change before the end of the acquisition time. At the beginning of the acquisition, the internal sampling capacitor array connects to AIN_ (the amplifier input), causing some disturbance on the output of the buffer. Ensure the sampled voltage has settled before the end of the acquisition time. Digital Noise Digital noise can couple to AIN_ and REF. The conversion clock () and other digital signals active during input acquisition contribute noise to the conversion result. Noise signals, synchronous with the sampling interval, result in an effective input offset. Asynchronous signals produce random noise on the input, whose highfrequency components can be aliased into the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at the inputs. This requires bypassing AIN_ to AGND, or buffering the input with an amplifier that has a small-signal bandwidth of several megahertz (doing both is preferable). AIN has a typical bandwidth of 4MHz. 23

24 Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the total harmonic distortion of the at the frequencies of interest (THD = -98db at 1kHz). If the chosen amplifier has insufficient common-mode rejection, which results in degraded THD performance, use the inverting configuration (positive input grounded) to eliminate errors from this source. Low-temperature-coefficient, gain-setting resistors reduce linearity errors caused by resistance changes due to self-heating. To reduce linearity errors due to finite amplifier gain, use amplifier circuits with sufficient loop gain at the frequencies of interest.. DC Accuracy To improve DC accuracy, choose a buffer with an offset much less than the s offset (±1mV max for +5V supply), or whose offset can be trimmed while maintaining stability over the required temperature range. Serial Interfaces SPI and MICROWIRE Interfaces When using the SPI (Figure 2a) or MICROWIRE (Figure 2b) interfaces, set CPOL = and CPHA =. Drive low to power on the before starting a conversion (Figure 2c). Three consecutive 8-bit-wide readings are necessary to obtain the entire 14-bit result from the ADC. data transitions on the serial clock s falling edge. The first 8-bit-wide data stream contains all leading zeros. The 2nd 8-bit-wide data stream contains the through D6. The 3rd 8-bit-wide data stream contains D5 through D followed by S1 and S. SPI I/O SCK MISO V DD I/O SK SI MICROWIRE SS MA167 MA168 MA167 MA168 Figure 2a. SPI Connections Figure 2b. MICROWIRE Connections 1ST BYTE READ 2ND BYTE READ * D13 D12 D11 D1 D9 D8 D7 D6 D5 *WHEN IS HIGH, = HIGH-Z 3RD BYTE READ 2 24 D5 D4 D3 D2 D1 D S1 S HIGH-Z Figure 2c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = ) 24

25 QSPI Interface Using the high-speed QSPI interface with CPOL = and CPHA =, the support a maximum f of 4.8MHz. Figure 21a shows the connected to a QSPI master and Figure 21b shows the associated interface timing. QSPI SCK MISO SS Figure 21a. QSPI Connections V DD MA167 MA168 PIC16 with SSP Module and PIC17 Interface The are compatible with a PIC16/ PIC17 controller (µc), using the synchronous serial-port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 22a and configure the PIC16/PIC17 as system master by initializing its synchronous serialport control register (SSPCON) and synchronous serialport status register (SSPSTAT) to the bit patterns shown in Tables 7 and 8. In SPI mode, the PIC16/PIC17 µcs allow 8 bits of data to be synchronously transmitted and received simultaneously. Three consecutive 8-bit-wide readings (Figure 22b) are necessary to obtain the entire 14-bit result from the ADC. data transitions on the serial clock s falling edge and is clocked into the µc on s rising edge. The first 8-bit-wide data stream contains all zeros. The 2nd 8-bit-wide data stream contains the through D6. The 3rd 8-bit-wide data stream contains bits D5 through D followed by S1 and S * SAMPLING INSTANT D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D S1 S HIGH-Z *WHEN IS HIGH, = HIGH-Z Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = ) Table 7. Detailed SSPCON Register Contents CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) WCOL BIT7 Write Collision Detection Bit SSPOV BIT6 Receive Overflow Detection Bit SSPEN BIT5 1 Synchronous Serial-Port Enable Bit: : Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. CKP BIT4 Clock Polarity Select Bit. CKP = for SPI master-mode selection. SSPM3 BIT3 SSPM2 BIT2 SSPM1 BIT1 SSPM BIT 1 Synchronous Serial-Port Mode Select Bit. Sets SPI master-mode and selects f CLK = f OSC / 16. = Don t care. 25