7809ALP 16-Bit Latchup Protected Analog to Digital Converter
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1 789ALP 6-Bit Latchup Protected Analog to Digital Converter R/C CS POWER DOWN Successive Approimation Register and Control Logic Clock 2 k CDAC R IN k BUSY R2 IN R3 IN 5 k 2 k Comparator Serial Data Out Data Clock Serial Data CAP REF Buffer 4 k Internal +2.5V Ref. FEATURES: Logic Diagram DESCRIPTION: RAD-PAK radiation-hardened against natural space radiation Total dose hardness: - > krad (Si), depending upon space mission Latch-up Protection Technology (LPT TM ) SEL converted into a reset - Rate based on cross section and mission Package: 24 pin RAD-PAK flat package khz min sampling rate ± V and V to 5 V input range DNL: 5-bits No Missing Codes 83 db min SINAD with 2 khz input Single +5 V supply operation Utilizes internal or eternal reference Serial output Power dissipation: 32 mw ma Mawell Technologies 789ALP high-speed 6-bit analog to digital converter features a greater than kilorad (Si) total dose tolerance depending upon space mission. Using Mawell s radiation-hardened RAD-PAK packaging technology is latchup protected by Mawell Technologies Latchup Protection Technology (LPT TM ). It is a 24 pin, 6-bit sampling analogto-digital converter using state-of-the-art CMOS structures. The 789ALP contains a 6-bit capacitor based SAR A/D with S/H, reference, clock, interface for microprocessor use, and serial output drivers. The 789ALP is specified at a khz sampling rate, and guaranteed over the full temperature range. Laser-trimmed scaling resistors provide various input ranges include ± V and to 5 V, while the innovative design allows operation from a single +5 V supply, with power dissipation of under 32 mw. Mawell Technologies' patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for bo shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 5 krad (Si) radiation dose tolerance. This product is available with screening up to Mawell Technologies self-defined Class K Rev (858) Fa: (858) Mawell Technologies
2 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE. 789ALP PIN DESCRIPTION PIN SYMBOL LPT PROTECTION DESCRIPTION RIN Not Protected Analog Input. 2 AGND N/A Analog Ground. Used internally as ground reference point. 3 R2IN Not Protected Analog Input. 4 R3IN Not Protected Analog Input. 5 CAP Not Protected Reference Buffer Capacitor. 2.2 µf tantalum to ground. 6 REF Not Protected Reference Input/Output. 2.2 µf tantalum capacitor to ground. 7 AGND2 N/A Analog Ground. 8 SB/BTC Not Protected Select Straight Binary or Binary Two s Complement data output format. If HIGH, data will be output in a Straight Binary format. If LOW, data will be output in a Binary Two s Complement format. 9 EXT/INT Not Protected Select Eternal or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 6 clock pulses output on DATACLK. DGND N/A Digital Ground. LPBIT Not Protected Built In test function of the latchup protection. Drive LOW during normal operation. 2 LPSTATUS Not Protected Latchup Protection Status Output. LPSTATUS when HIGH indicates latchup protection is active and output data is invalid. 3 VDIG Protected Digital Supply Input. Nominally 5V. 4 VANA Protected Analog Supply Input. Nominally 5V. 5 SYNC Not Protected Sync Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a pulse on SYNC synchronized to the eternal DATACLK. 6 DATACLK Protected Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW, DATACLK will transmit 6 pulses after each conversion, and then remain LOW between conversions. 7 DATA Not Protected Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the eternal clock mode, after 6-bits of data, the 789LOPO will output the level input of TAG as long as CS is LOW and R/C is HIGH. If EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the level of the TAG input when the conversion was started. 8 TAG Protected Tag input for use in eternal clock mode. If EXT/INT is HIGH, the digital data input on TAG will be output on DATA with a delay of 6 DATACLK pulses as long as CS is LOW and R/C is HIGH Rev 2 24 Mawell Technologies
3 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE. 789ALP PIN DESCRIPTION PIN SYMBOL LPT PROTECTION DESCRIPTION 9 R/C Protected Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of data from the previous conversion. 2 CS Protected Chip Select. Internally OR ed with R/C. 2 BUSY Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition. 22 PWRD Protected Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversions are maintained in the output shift register. 23 LPVANA Protected Latchup Protected Analog Supply. 24 LPVDIG Protected Latchup Protected Digital Supply. TABLE ALP ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNIT Analog Inputs R IN R2 IN R3 IN CAP REF V ANA AGND2 -.3 Ground Voltage Differences: DGND, AGND V V ANA 7 V V DIG 7 V V DIG to V ANA.3 V Digital Inputs -.3 V DIG +.3 V Weight 7.8 Grams Thermal Resistance T JC 7.3 C/W Operating Temperature 2 T OPE C Storage Temperature T STG C V V V V. Indefinite short to AGND2, momentarily short to V ANA. 2. Minimum Temperature is -4 C when using with an eternal reference Rev 3 24 Mawell Technologies
4 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE ALP DC ACCURACY SPECIFICATIONS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Integral Linearity Error, 2, 3 ±7 LSB Differential Linearity Error -35 to 85 C (Internal Reference); -4 to 85 C (Eternal Reference 2, 3-2, 3 -, 6 LSB LSB No Missing Codes 2 Transition Noise 3 Full Scale Error 4,5 5 Bits.3 LSB, 2, 3 ±.8 % Full Scale Error 4,5 (using et. 2.5 V ref ), 2, 3 ±.8 % Full Scale Error Drift ±7 ppm/ C Full Scale Error Drift (using et. 2.5 V ref ), 2, 3 ±2 ppm/ C Bipolar Zero Error 4, 2, 3 ±2 mv Bipolar Zero Error Drift ±2 ppm/ C Unipolar Zero Error 4-35 to 85 C (Internal Reference); -4 to 85 C (Eternal Reference Unipolar Zero Error Drift ±2 ppm/ C Recovery to Rated Accuracy after Power Down ( uf Capacitor ms to CAP) 2, 3 ±3 ±6 mv mv Power Supply Sensitivity (V DIG = V ANA = V D ) 4.75 V < V D < 5.2 V -35 to 85 C (Internal Reference); -4 to 85 C (Eternal Reference 2, 3 ±8 ±32 LSB LSB. LSB stands for Least Significant Bit. One LSB is equal to 35 µv. 2. Not tested. 3. Typical rms noise at worst case transitions and temperatures. 4. Measured with various fied resistors. 5. For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last scale code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error. TABLE 4. DELTA LIMITS PARAMETER VARIATION I CC +/- % Rev 4 24 Mawell Technologies
5 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE ALP ANALOG INPUT AND THROUGHPUT SPEED (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Voltage Ranges, 2, 3 V, V to 5 V, etc. Impedance, 2, 3 See Table 2. Capacitance 35 pf Conversion Time 9,, µs Complete Cycle (Acquire and Convert) 9,, µs Throughput Rate 2 9,, khz. Guarenteed by design. 2. Tested by application of signal. TABLE ALP AC ACCURACY SPECIFICATIONS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Spurious-Free Dynamic Range, f IN = 2 khz 4, 5, 6 9 db 2 Total Harmonic Distortion, f IN = 2 khz 4, 5, db Signal-to-Noise (Noise + Distortion) f IN = 2 khz -6 db Input 4, 5, 6 Signal-to-Noise, f IN = 2 khz db Full-Power Bandwidth,3 25 khz db. Guaranteed by design. 2. All specifications in db are referred to a full-scale ± V input. 3. Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 6 db. TABLE ALP SAMPLING DYNAMICS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Aperture Delay 4 ns Aperture Jitter 9,, Sufficient to meet AC specification Transient Response FS Step 2 us Overvoltage Recovery. Recovers to specified performance after 2 X FS input overvoltage. 5 ns Rev 5 24 Mawell Technologies
6 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE ALP REFERENCE (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER CONDITIONS MIN TYP MAX UNIT Internal Reference Voltage No Load V Internal Reference Source Current (Must be µa et. buffer) Eternal Reference Voltage Range for Specified Linearity V Eternal Reference Current Drain Et. 2.5V Ref 75 µa. Tested from -35C to +85C 2. Tested by application of signal. TABLE ALP DIGITAL OUTPUTS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER SUBGROUPS CONDITIONS MIN TYP MAX UNIT Data Format Data Coding Pipeline Delay Data Clock Internal (Output Only When Transmitting Data) Eternal (Can Run Continually) Serial 6-bits Binary Two s Complement or Straight Binary Conversion results only available after completed conversion Selectable for internal or eternal data clock 9,, EXT/INT Low EXT/INT High V OL, 2, 3 I SINK =.6 ma V OH I SOURCE = 5 µa ±6 µa Leakage Current High-Z State, V OUT = V to V DIG Output Capacitance High-Z State 5 pf ) Not Tested MHz V TABLE. 789ALP POWER SUPPLIES (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER SUBGROUPS CONDITIONS MIN TYP MAX UNIT V DIG, 2, 3 Must be < V ANA V V ANA, 2, V I DIG.3 ma I ANA 6 ma Icc, 2, 3 IDIG KHz 26.4 ma Rev 6 24 Mawell Technologies
7 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE. 789ALP POWER SUPPLIES (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) PARAMETER SUBGROUPS CONDITIONS MIN TYP MAX UNIT Power Dissipation PWRD LOW PWRD HIGH, 2, 3 V ANA = V DIG = 5V f s = khz 32 mw ) Not Tested TABLE. 789ALP CONTROL LINE FUNCTIONS FOR READ AND CONVERT SPECIFIC FUNCTION CS R/C BUSY EXT/INT DATACL K PWRD SB/BTC OPERATION Initiate Conversion and Output Data using Internal Clock Initiate Conversion and Output Data using Eternal Clock Incorrect Conversions > > > > > > > Output Output Input Input Input Input Input Initiates conversion n. Data from conversion n- clocked out on DATA synchronized to 6 clock pulses output on DATA- CLK Initiates conversion n. Data from conversion n- clocked out on DATA synchronized to 6 clock pulses output on DATA- CLK Initiates conversion n Initiates conversion n Outputs a pulse on SYNC followed by data from conversion n clocked out synchronized to eternal DATACLK. Outputs a pules on SYNC followed by data from conversion n- clocked out synchronized to eternal DATACLK. Conversion n in process. Outputs a pulse on SYNC followed by data from conversion n- clocked out synchronized to eternal DATACLK. Conversion n in process. > CS or R/C must be HIGH or a new conversion will be initiated without time for acquisition Rev 7 24 Mawell Technologies
8 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE. 789ALP CONTROL LINE FUNCTIONS FOR READ AND CONVERT SPECIFIC FUNCTION CS R/C BUSY EXT/INT Power Down Selecting Output Format DATACL K PWRD SB/BTC OPERATION Analog circuitry powered. Conversion will be initiated without time for acquisition Analog circuitry disabled. Data from previous conversion maintained in output registers Serial data is output in Binary Two s Complement format. Serial data is output in Straight Binary format.. See Figure 4 for constraints on previous data valid during conversion. ANALOG INPUT RANGE TABLE ALP INPUT RANGE CONNECTION CONNECT R IN VIA 2 TO CONNECT R2 IN VIA TO CONNECT R3 IN TO IMPEDANCE 2 ±V V IN AGND CAP 22.9 k ±5V AGND V IN CAP 3.3 k ±3.3V V IN V IN CAP.7 k V to V AGND V IN AGND 3.3k V to 5V AGND AGND V IN. k V to 4V V IN AGND V IN.7 k ) Not Tested 2) Guarenteed by Design TABLE ALP CONVERSION AND DATA TIMING (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) SYMBOL DESCRIPTION SUBGROUPS MIN TYP MAX UNIT t Convert Pulse Width 9,, 4 6 ns t2 BUSY Delay 9,, 8 ns t3 BUSY LOW 9,, 8 µs t4 BUSY Delay after End of Conversion 9,, 22 ns t5 Aperture Delay 9,, 4 ns t6 Conversion Time 9,, µs t7 Acquisition Time 9,, 2 µs t6 + t7 Throughput Time 9,, 9 µs Rev 8 24 Mawell Technologies
9 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE ALP CONVERSION AND DATA TIMING (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE; -35 TO +85 C USING INTERNAL REFERENCE) SYMBOL DESCRIPTION SUBGROUPS MIN TYP MAX UNIT t8 R/C Low to DATACLK Delay 9,, 45 ns t9 DATACLK Period 9,, 44 ns t Data Valid to DATACLK HIGH Delay 9,, 2 75 ns t Data Valid after DATACLK LOW Delay 9,, 25 ns t2 Eternal DATACLK 9,, ns t3 Eternal DATACLK HIGH 9,, 2 ns t4 Eternal DATACLK LOW 9,, 3 ns t5 DATACLK HIGH Setup Time 9,, 2 t2 + 5 ns t6 R/C to CS Setup Time 9,, ns t7 SYNC Delay After DATACLK High 9,, 5 45 ns t8 Data Valid Delay 9,, 25 7 ns t9 CS to Rising Edge Delay 9,, 25 ns t2 Data Available after CS LOW 9,, 6 µs TABLE ALP OUTPUT CODES AND IDEAL INPUT VOLTAGES DIGITAL OUTPUT DESCRIPTION ANALOG INPUT BINARY TWO S COMPLEMENT (SB/BTC LOW) STRAIGHT BINARY (SB/BTC HIGH) BINARY CODE HEX CODE BINARY CODE HEX CODE Full Scale Range ± ±5 ±3.33V V to V V to 5V V to 4V Least Significant Bit (LSB) 35 µv 53 µv 2 µv 53 µv 76 µv 6 µv + Full Scale (FS - LSB) V V V V V V 7FFF FFFF Midscale V V V 5V 2.5V 2V 8 One LSB Below Midscale -35 µv -53 µv -2 µv V V V FFFF 7FFF -Full Scale -V -5V V V V V Rev 9 24 Mawell Technologies
10 6-Bit Latchup Protected Analog to Digital Converter 789ALP TABLE 5. LPT TM OPERATING CHARACTERISTICS PARAMETER SYMBOL TYPICAL UNIT Supply Threshold ITHR 75 ma Protection Time TPT us Supply Recovery Time TSR 5 us Functional Recoverty Time TFR 75 us 8-Bit Accuracy Recovery Time T8R 8 us Full Scale Recovery Time TFAR 5 ms FIGURE. CONVERSION TIMING FIGURE 2. SERIAL DATA TIMING USING INTERNAL CLOCK (CS, EXT/INT AND TAG TIED LOW) Rev 24 Mawell Technologies
11 6-Bit Latchup Protected Analog to Digital Converter 789ALP FIGURE 3. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ AFTER CONVERSION FIGURE 4. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ DURING CONVERSION Rev 24 Mawell Technologies
12 6-Bit Latchup Protected Analog to Digital Converter 789ALP FIGURE 5. OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES Rev 2 24 Mawell Technologies
13 6-Bit Latchup Protected Analog to Digital Converter 789ALP FIGURE 6. OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES Rev 3 24 Mawell Technologies
14 6-Bit Latchup Protected Analog to Digital Converter 789LP Figure 7. LPT TM Timing Diagram Rev # 2 Mawell Technologies
15 6-Bit Latchup Protected Analog to Digital Converter 789ALP 24-PIN RAD-PAK FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A b c.6.8. D E E.44 E E e.5 BSC L Q S.6.4 N 24 Note: All dimensions in inches Top and Bottom of package internally connected to ground Rev 5 24 Mawell Technologies
16 6-Bit Latchup Protected Analog to Digital Converter Important Notice: 789ALP These data sheets are created using the chip manufacturers published specifications. Mawell Technologies verifies functionality by testing key parameters either by % testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Mawell Technologies assumes no responsibility for the use of this information. Mawell Technologies products are not authorized for use as critical components in life support devices or systems without epress written approval from Mawell Technologies. Any claim against Mawell Technologies must be made within 9 days from the date of shipment from Mawell Technologies. Mawell Technologies liability shall be limited to replacement of defective parts Rev 6 24 Mawell Technologies
17 6-Bit Latchup Protected Analog to Digital Converter 789ALP Product Ordering Options Model Number 789ALP RP F X Feature Option Details Screening Flow Multi Chip Module (MCM) K = Mawell Self-Defined Class K H = Mawell Self-Defined Class H I = Industrial -4 C, +25 C, +85 C) E = Engineering +25 C Package F = Flat Pack Radiation Feature RP = RAD-PAK package Base Product Nomenclature 6-Bit Latchup Protected Analog to Digital Converter ) Products are manufactured and screened to Mawell Technologies self-defined Class H and Class K flows Rev 7 24 Mawell Technologies
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