ANALOG INPUTS. Maxim Integrated Products 7-169

Transcription

1 9-4782; Rev ; 3/99 EVALUATION KIT MANUAL FOLLOWS DATA SHEET Multirange, +5V, 8-Channel, Serial 2-Bit ADCs General Description The MAX27/MAX27 are multirange, 2-bit dataacquisition systems (DAS) that require only a single +5V supply for operation, yet accept signals at their analog inputs that may span above the power-supply rail and below ground. These systems provide eight analog input channels that are independently software programmable for a variety of ranges: ±V, ±5V, to +V, to +5V for the MAX27; ±V REF, ±V REF /2, to V REF, to V REF /2 for the MAX27. This range switching increases the effective dynamic range to 4 bits and provides the flexibility to interface 4 2mA, ±2V, and ±5V powered sensors directly to a single +5V system. In addition, these converters are fault protected to ±6.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, softwareselectable internal/external clock, ksps throughput rate, and internal 4.96V or external reference operation. The MAX27/MAX27 serial interface directly connects to SPI /QSPI and MICROWIRE devices without external logic. A hardware shutdown input (SHDN) and two softwareprogrammable power-down modes, standby (STBYPD) or full power-down (FULLPD), are provided for low-current shutdown between conversions. In standby mode, the reference buffer remains active, eliminating start-up delays. The MAX27/MAX27 are available in 24-pin narrow DIP or space-saving 28-pin SSOP packages. Industrial Control Systems Data-Acquisition Systems Robotics Automatic Testing Battery-Powered Instruments Medical Instruments PART TEMP. RANGE Applications Ordering Information PIN-PACKAGE INL () MAX27ACNG MAX27BCNG MAX27ACAI C to +7 C C to +7 C C to +7 C 24 Narrow Plastic DIP 24 Narrow Plastic DIP 28 SSOP ±/2 ± ±/2 MAX27BCAI C to +7 C 28 SSOP ± Ordering Information continued at end of data sheet. Features 2-Bit Resolution, /2 Linearity +5V Single-Supply Operation SPI/QSPI and MICROWIRE-Compatible 3-Wire Interface Four Software-Selectable Input Ranges MAX27: to +V, to +5V, ±V, ±5V MAX27: to V REF, to V REF /2, ±V REF, ±V REF /2 Eight Analog Input Channels ksps Sampling Rate ±6.5V Overvoltage-Tolerant Input Multiplexer Internal 4.96V or External Reference Two Power-Down Modes Internal or External Clock 24-Pin Narrow DIP or 28-Pin SSOP Packages 4.7µF ANALOG INPUTS Typical Operating Circuit.µF CH CH CH2 CH3 CH4 CH5 CH6 CH7.µF REF REFADJ MAX27 MAX27 DGND AGND +5V V DD SHDN DIN Pin Configurations appear at end of data sheet. MC68HCXX I/O SCK MOSI MISO SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. MAX27/MAX27 Maxim Integrated Products 7-69 For free samples & the latest literature: or phone For small orders, phone

2 Serial 2-Bit ADCs MAX27/MAX27 ABSOLUTE MAXIMUM RATINGS V DD to AGND...-.3V to +6V AGND to DGND...-.3V to +.3V CH CH7 to AGND... ±6.5V REF, REFADJ to AGND...-.3V to (V DD +.3V), to DGND...-.3V to (V DD +.3V) SHDN,, DIN, to DGND...-.3V to +6V Max Current into Any Pin...5mA Continuous Power Dissipation (T A = +7 C) 24-Pin Narrow DIP (derate 3.33mW/ C above +7 C)..67mW 28-Pin SSOP (derate 9.52mW/ C above +7 C)...762mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI Operating Temperature Ranges MAX27_C... C to +7 C MAX27_E...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C (V DD = +5.V ±5%; unipolar/bipolar range; external reference mode, V REF = +4.96V; 4.7µF at REF; external clock, f CLK = 2.MHz (5% duty cycle), 8 clock/conversion cycle, ksps; T A = T MIN to T MAX ; unless otherwise noted. Typical values are T A = +25 C.) PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY (Note ) Resolution 2 bits Integral Nonlinearity INL MAX27_A ±.5 MAX27_B ±. Differential Nonlinearity DNL No missing codes over temperature ± Offset Error Unipolar MAX27_A ±3 MAX27_B ±5 Bipolar MAX27_A ±5 MAX27_B ± Channel-to-Channel Offset Unipolar ±. Error Matching Bipolar ±.3 MAX27_A ±7 Unipolar Gain Error MAX27_B ± (Note 2) MAX27_A ±7 Bipolar MAX27_B ± Gain Error Temperature Unipolar, external reference ±3 Coefficient (Note 2) Bipolar, external reference ±5 ppm/ C DYNAMIC SPECIFICATIONS (khz sine-wave input, ±Vp-p (MAX27), or ±4.96Vp-p (MAX27), f SAMPLE = ksps) Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay Aperture Jitter SINAD THD SFDR Up to the 5th harmonic 5kHz (Note 3) DC, V IN = ±6.5V External clock mode External clock mode Internal clock mode <5 db db db db db ns ps ns 7-7

3 Serial 2-Bit ADCs ELECTRICAL CHARACTERISTI (continued) (V DD = +5.V ±5%; unipolar/bipolar range; external reference mode, V REF = +4.96V; 4.7µF at REF; external clock, f CLK = 2.MHz (5% duty cycle), 8 clock/conversion cycle, ksps; T A = T MIN to T MAX ; unless otherwise noted. Typical values are T A = +25 C.) PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Track/Hold Acquisition Time t ACQ f CLK = 2.MHz 3 µs ±V or ±V REF range 5 Small-Signal Bandwidth -3dB ±5V or ±V REF / 2 range 2.5 rolloff to V or to V REF range 2.5 MHz to 5V or to V REF / 2 range.25 Input Voltage Range V IN RNG = Unipolar MAX27 RNG = 5 (BIP = ), Table 3 RNG = V REF MAX27 RNG = V REF /2 RNG = - Bipolar MAX27 RNG = -5 5 (BIP = ), Table 3 RNG = -V REF V REF MAX27 RNG = -V REF /2 V REF /2 V to V range - 72 MAX27 Unipolar to 5V range - 36 MAX27 -. Input Current I IN ±V range µa MAX27 ±5V range Bipolar ±V REF range -2 MAX27 ±V REF /2 range -6 Dynamic Resistance V IN / I IN Unipolar 2 Bipolar 6 kω Input Capacitance (Note 4) 4 pf INTERNAL REFERENCE REF Output Voltage V REF T A = +25 C V REF Output Tempco TC V REF MAX27_C/MAX27_C ±5 MAX27_E/MAX27_E ±3 ppm/ C Output Short Circuit Current 3 ma Load Regulation (Note 5) to.5ma output current mv Capacitive Bypass at REF 4.7 µf Capacitive Bypass at REFADJ. µf REFADJ Output Voltage V REFADJ Adjustment Range Figure ±.5 % Buffer Voltage Gain.638 V/V REFERENCE INPUT (Reference buffer disabled, reference input applied to REF) Input Voltage Range V Input Current V REF = 4.8V Normal or STBYPD 4 FULLPD µa MAX27/MAX27 7-7

4 Serial 2-Bit ADCs MAX27/MAX27 ELECTRICAL CHARACTERISTI (continued) (V DD = +5.V ±5%; unipolar/bipolar range; external reference mode, V REF = +4.96V; 4.7µF at REF; external clock, f CLK = 2.MHz (5% duty cycle), 8 clock/conversion cycle, ksps; T A = T MIN to T MAX ; unless otherwise noted. Typical values are T A = +25 C.) PARAMETERS Input Resistance REFADJ Threshold for Buffer Disable POWER REQUIREMENT Bandgap Reference Start-Up Time (Note 9) Reference Buffer Settling Time SYMBOL CONDITIONS MIN TYP MAX UNITS Normal or STBYPD kω V REF = 4.8V FULLPD 4.8 MΩ Supply Voltage V DD V Bipolar range 8 Normal ma Unipolar range 6 Supply Current I DD STBYPD power down mode (Note 6) 7 85 µa FULLPD power down mode 2 22 Power-Supply Rejection External reference = 4.96V ±. ±.5 PSRR Ratio (Note 7) Internal reference ±.5 TIMING External Clock Frequency Range Acquisition Phase Power-up C REF = 4.7µF C REF = 33µF V DD -.5 f CLK. 2. MHz External clock mode (Note 8) Internal clock mode, Figure Conversion Time t CONV External clock mode (Note 8) 6 Internal clock mode, Figure Throughput Rate External clock mode Internal clock mode 43 To.mV, REF bypass capacitor fully discharged 2 µs DIGITAL INPUTS: DIN,,, SHDN Input High Threshold Voltage V IH 2.4 V Input Low Threshold Voltage V IL.8 V Input Hysteresis V HYS.2 V Input Leakage Current I IN V IN = to V DD - µa Input Capacitance C IN (Note 4) 5 pf DIGITAL OUTPUTS:, Output Voltage Low V OL I SINK = 5mA.4 I SINK = 6mA.4 V Output Voltage High V OH I SOURCE =.5mA V DD -.5 V Three-State Leakage Current I L = V DD - µa Three-State Output Capacitance C OUT = V DD (Note 4) 5 pf V µs µs ksps ms 7-72

5 Serial 2-Bit ADCs TIMING CHARACTERISTI (V DD = +4.75V to +5.25; unipolar/bipolar range; external reference mode, V REF = +4.96V; 4.7µF at REF; external clock, f CLK = 2MHz; T A = T MIN to T MAX, unless otherwise noted. Typical values are T A = +25 C.) (Figures 2, 5, 7, ) PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS DIN to Setup t DS ns DIN to Hold t DH ns Fall to Output Data Valid t DO C LOAD = pf 2 7 ns Fall to Output Enable t DV C LOAD = pf 2 ns Rise to Output Disable t TR C LOAD = pf ns to Rise Setup t S ns to Rise Hold t H ns Pulse Width High t CH 2 ns Pulse Width Low t CL 2 ns Fall to t C LOAD = pf 2 ns to Output Enable t SDV C LOAD = pf External clock mode only 2 ns MAX27/MAX27 to Output Disable t STR C LOAD = pf External clock mode only 2 ns Rise to Rise (Note 4) t SCK Internal clock mode only ns Note : Accuracy specifications tested at V DD = +5.V. Performance at power-supply tolerance limit is guaranteed by Power-Supply Rejection test. Note 2: External reference: V REF = 4.96V, offset error nulled. Ideal last-code transition = FS - 3/2. Note 3: Ground on channel; sine wave applied to all off channels. V IN = ±5V (MAX27), V IN = ±4V (MAX27). Note 4: Guaranteed by design, not production tested. Note 5: Use static external loads during conversion for specified accuracy. Note 6: Tested using internal reference. Note 7: PSRR measured at full scale. Tested for the ±V (MAX27) and ±4.96V (MAX27) input ranges. Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 5% duty cycle (Figure 6). Note 9: Not production tested. Provided for design guidance only. 7-73

6 Serial 2-Bit ADCs MAX27/MAX27 Typical Operating Characteristics (Typical Operating Circuit, V DD = +5V; external reference mode, V REF = +4.96V; 4.7µF at REF; external clock, f CLK = 2MHz; ksps; T A = +25 C; unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) MAX27/ toc SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) MAX27/ toc2 STANDBY SUPPLY CURRENT (µa) STANDBY SUPPLY CURRENT vs. TEMPERATURE INTERNAL REFERENCE EXTERNAL REFERENCE TEMPERATURE ( C) MAX27/ toc3 FULL POWER-DOWN SUPPLY CURRENT (µa) FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE EXTERNAL REFERENCE INTERNAL REFERENCE TEMPERATURE ( C) MAX27/ toc4 NORMALIZED REFERENCE VOLTAGE NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE TEMPERATURE ( C) MAX27/ toc5 CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING () CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE BIPOLAR MODE UNIPOLAR MODE TEMPERATURE ( C) MAX27/ toc6 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING () CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE UNIPOLAR MODE BIPOLAR MODE TEMPERATURE ( C) MAX27/ toc7 INTEGRAL NONLINEARITY () INTEGRAL NONLINEARITY vs. DIGITAL CODE DIGITAL CODE MAX27/ toc8 AMPLITUDE (db) FTT PLOT k 2k 3k 4k 5k FREQUENCY (Hz) f IN = khz f SAMPLE = ksps MAX27/ toc9 7-74

7 Serial 2-Bit ADCs Typical Operating Characteristics (continued) (Typical Operating Circuit, V DD = +5V; external reference mode, V REF = +4.96V; 4.7µF at REF; external clock, f CLK = 2MHz; ksps; T A = +25 C; unless otherwise noted.) DIP 2, 4 3, 9, 22, AVERAGE SUPPLY CURRENT (ma) PIN SSOP 2, 3 4, 7, 8,, 22, 24, 25, , AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING STANDBY) V DD = 5V, INTERNAL REFERENCE, f CLK = 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. V CH_ =. CONVERSION RATE (ksps) NAME V DD DGND N.C. DIN SHDN AGND CH CH7 REFADJ MAX27-toc AVERAGE SUPPLY CURRENT (ma) FUNCTION +5V Supply. Bypass with a.µf capacitor to AGND. Digital Ground No Connect. No internal connection. AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FULLPD) V DD = 5V, INTERNAL REFERENCE, f CLK = 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. V CH_ =. CONVERSION RATE (ksps) MAX27-toc Pin Description Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, also sets the conversion speed. Active-Low Chip-Select Input. Data is not clocked into DIN unless is low. When is high, is high impedance. Serial Data Input. Data is clocked in on the rising edge of. Serial Strobe Output. In internal clock mode, goes low after the falling edge of the eighth and returns high when conversion is done. In external clock mode, pulses high for one clock period before the MSB decision. High impedance when is high in external clock mode. Serial Data Output. Data is clocked out on the falling edge of. High impedance when is high. Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation. Analog Ground Analog Input Channels Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a.µf capacitor to AGND. Connect to V DD when using an external reference at REF. MAX27/MAX REF Reference-Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.96V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to V DD and applying the external reference to REF. 7-75

8 Serial 2-Bit ADCs MAX27/MAX27 k 24k +5V 5k.µF Figure. Reference-Adjust Circuit MAX27 MAX27 REFADJ Detailed Description Converter Operation The MAX27/MAX27 multirange, fault-tolerant ADCs use successive approximation and internal track/hold (T/H) circuitry to convert an analog signal to a 2-bit digital output. Figure 3 shows the block diagram of the MAX27/MAX27. Analog-Input Track/Hold The T/H enters tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word, and enters hold/conversion mode when the timed acquisition interval (six clock cycles, 3µs minimum) ends. In internal clock mode, the acquisition is timed by two external clock cycles and four internal clock cycles. When operating in bipolar (MAX27 and MAX27) or OR.5mA C LOAD a) TO V OH, V OL TO V OH, AND V OH TO OR unipolar mode (MAX27) the signal applied at the input channel is rescaled through the resistor-divider network formed by R, R2, and R3 (Figure 4); a lowimpedance (<4Ω) input source is recommended to minimize gain error. When the MAX27 is configured for unipolar mode, the channel input resistance (R IN ) becomes a fixed 5.2kΩ (typ). Source impedances below 5kΩ ( to V REF ) and 5kΩ ( to V REF /2) do not significantly affect the AC performance of the ADC. The acquisition time (t ACQ ) is a function of the source output resistance, the channel input resistance, and the T/H capacitance. Higher source impedances can be used if an input capacitor is connected between the analog inputs and AGND. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC s signal bandwidth. 5mA +5V C LOAD b) TO V OH, V OL TO V OH, AND V OH TO Figure 2. Output Load Circuit for Timing Characteristics DIN SHDN CH CH CH2 CH3 CH4 CH5 CH6 CH7 REF REFADJ ANALOG INPUT MUX AND SIGNAL CONDITIONING 2.5V REFERENCE k Av =.638 SERIAL INTERFACE LOGIC OUT T/H IN REF +4.96V 2-BIT SAR ADC MAX27 MAX27 CLOCK INT CLOCK V DD AGND DGND Figure 3. Block Diagram 7-76

9 Serial 2-Bit ADCs Input Bandwidth The ADC s input small-signal bandwidth depends on the selected input range and varies from.5mhz to 5MHz (see Electrical Characteristics). The MAX27/ MAX27 maximum sampling rate is ksps. By using undersampling techniques, it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate. To avoid high-frequency signals being aliased into the frequency band of interest, anti-aliasing filtering is recommended. Input Range and Protection The MAX27/MAX27 have software-selectable input ranges. Each analog input channel can be independently programmed to one of four ranges by setting the appropriate control bits (RNG, BIP) in the control byte (Table ). The MAX27 has selectable input ranges extending to ±V (±V REF 2.44), while the MAX27 has selectable input ranges extending to ±V REF. Figure 4 shows the equivalent input circuit. A resistor network on each analog input provides ±6.5V fault protection for all channels. Whether or not the channel is on, this circuit limits the current going into or out of the pin to less than 2mA. This provides an added layer of protection when momentary overvoltages occur at the selected input channel, when a negative signal is applied to the input, and when the device is configured for unipolar mode. The overvoltage protection is active even if the device is in power-down mode or if V DD =. Digital Interface The MAX27/MAX27 feature a serial interface that is fully compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, set CPOL =, CPHA = in the SPI control registers of the microcontroller. Figure 5 shows detailed serial interface timing information. Refer to Table for programming the input control byte. CH_ R R3 5.2k S S2 R2 HOLD S = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH Figure 4. Equivalent Input Circuit BIPOLAR UNIPOLAR OFF ON S3 C HOLD TRACK TRACK S4 R = 2.5kΩ (MAX27) or 5.2kΩ (MAX27) R2 = 8.67kΩ (MAX27) or (MAX27) VOLTAGE REFERENCE T/H OUT HOLD MAX27/MAX27 t H t S t CL t CH t H t DS t DH DIN t DV t DO t TR Figure 5. Detailed Serial-Interface Timing 7-77

10 Serial 2-Bit ADCs MAX27/MAX27 Table. Control-Byte Format Bit 7 (MSB) START BIT 7 (MSB) 6, 5, 4 3 2, () SEL2 NAME START SEL2, SEL, SEL RNG BIP PD, PD Table 2. Channel Selection SEL2 Bit 6 SEL Bit 5 SEL Bit 4 SEL Bit 3 RNG DESCRIPTION First logic after goes low defines the beginning of the control byte. These three bits select the desired on channel (Table 2). Selects the full-scale input voltage range (Table 3). Selects unipolar or bipolar conversion mode (Table 3). Select clock and power-down modes (Table 4). SEL CHANNEL CH CH CH2 CH3 CH4 CH5 CH6 CH7 Bit 2 BIP Bit PD Bit () PD Table 4. Power Down and Clock Selection PD PD MODE Normal Operation (always on), Internal Clock Mode Normal Operation (always on), External Clock Mode Standby Power-Down Mode (STBYPD), Clock Mode Unaffected Full Power-Down Mode (FULLPD), Clock Mode Unaffected Table 3. Range and Polarity Selection for MAX27/MAX27 Range RANGE and AND Polarity POLARITY SELECTION FOR MAX27 INPUT RANGE RNG BIP Range RANGE and AND Polarity POLARITY SELECTION FOR MAX27 NEGATIVE FULL SCALE ZERO SCALE (V) FULL SCALE to 5V V REF.227 to V V REF ±5V -V REF.227 V REF.227 ±V -V REF V REF INPUT RANGE RNG BIP NEGATIVE FULL SCALE ZERO SCALE (V) FULL SCALE to V REF /2 V REF /2 to V REF V REF ±V REF /2 -V REF /2 V REF /2 ±V REF -V REF V REF 7-78

11 Serial 2-Bit ADCs Input Data Format Input data (control byte) is clocked in at DIN at the rising edge of. enables communication with the MAX27/MAX27. After falls, the first arriving logic bit represents the start bit (MSB) of the input control byte. The start bit is defined as: The first high bit clocked into DIN with low anytime the converter is idle; e.g., after V DD is applied. OR The first high bit clocked into DIN after bit 6 (D6) of a conversion in progress is clocked onto. Output Data Format Output data is clocked out on the falling edge of at, MSB first (D). In unipolar mode, the output is straight binary. For bipolar mode, the output is two scomplement binary. For output binary codes, refer to the Transfer Function section. How to Start a Conversion The MAX27/MAX27 use either an external serial clock or the internal clock to complete an acquisition and perform a conversion. In both clock modes, the external clock shifts data in and out. Refer to Table 4 for programming clock modes. The falling edge of does not start a conversion on the MAX27/MAX27; a control byte is required for each conversion. Acquisition starts after the sixth bit is programmed in the input control byte. Conversion starts when the acquisition time, six clock cycles, expires. Keep low during successive conversions. If a startbit is received after transitions from high to low, but before the output bit 6 (D6) becomes available, the current conversion will terminate and a new conversion will begin. External Clock Mode (PD =, PD = ) In external clock mode, the clock shifts data in and out of the MAX27/MAX27 and controls the acquisition and conversion timings. When acquisition is done, pulses high for one clock cycle and conversion begins. Successive-approximation bit decisions appear at on each of the next 2 falling edges (Figure 6). Additional falling edges will result in zeros appearing at. Figure 7 shows the timing in external clock mode. and go into a high-impedance state when goes high; after the next falling edge, and will output a logic low. The conversion must be completed in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the clock period exceeds µs, or if serial-clock interruptions could cause the conversion interval to exceed 2µs. The fastest the MAX27/MAX27 can run is 8 clocks per conversion in external clock mode, and with a clock rate of 2MHz, the maximum sampling rate is ksps (Figure 8). In order to achieve maximum throughput, keep low, use external clock mode with a continuous, and start the following control byte after bit 6 (D6) of the conversion in progress is clocked onto. If is low and is continuous, guarantee a start bit by first clocking in 8 zeros. MAX27/MAX DIN START SEL2 SEL SEL RNG BIP PD PD MSB D MSB D D9 D D FILLED WITH ZEROS A/D STATE ACQUISITION 6 CONVERSION 2 Figure 6. External Clock Mode, 25 Clocks/Conversion Timing 7-79

12 Serial 2-Bit ADCs MAX27/MAX27 t SDV t t 2 Figure 7. External Clock Mode Detailed Timing t STR DIN MSB CONTROL BYTE Ø START SEL2 SEL SEL RNG BIP PD PD START SEL2 SEL SEL CONTROL BYTE CONTROL BYTE 2 RNG BIP PD PD START SEL2 8 MSB RESULT Ø D D D9 D8 D7 D6 D5 D4 D3 D2 D D RESULT D D D9 D8 D7 D6 D5 8 A/D STATE ACQUISITION 6 CONVERSION 2 ACQUISITION 6 CONVERSION 2 Figure 8. External Clock Mode, 8 Clocks/Conversion Timing Internal Clock Mode (PD =, PD = ) In internal clock mode, the MAX27/MAX27 generate their conversion clock internally. This frees the microprocessor from the burden of running the acquisition and the SAR conversion clock, and allows the conversion results to be read back at the processor s convenience, at any clock rate from to typically MHz. goes low after the falling edge of the last bit (PD) of the control byte has been shifted in, and returns high when the conversion is complete. Acquisition is completed and conversion begins on the falling edge of the 4th internal clock pulse after the control byte; conversion ends on the falling edge of the 6th internal clock pulse (2 internal clock cycle pulses are used for conversion). will remain low for a maximum of 5µs, during which time should remain low for best noise performance. An internal register stores data while the conversion is in progress. The MSB of the result byte (D) is present at starting at the falling edge of the last internal clock of conversion. Successive falling edges of will shift the remaining data out of this register (Figure 9). Additional edges will result in zeros on. When internal clock mode is selected, does not go into a high-impedance state when goes high. Pulling high prevents data from being clocked in and three-states, but does not adversely affect a 7-8

13 Serial 2-Bit ADCs DIN START SEL2 SEL SEL RNG BIP PD PD MSB D D D D FILLED WITH ZEROS A/D STATE 6 INT CLK ACQUISITION CONVERSION 2 EXT +4 INT CLK Figure 9. Internal Clock Mode, 2 /Conversion Timing 2 INT CLK MSB MAX27/MAX27 t H t SCK t S t #8 NOTE: FOR BEST NOISE PERFORMANCE, KEEP LOW DURING CONVERSION. Figure. Internal Clock Mode Detailed Timing conversion in progress. Figure shows the timing in internal clock mode. Internal clock mode conversions can be completed with 3 external clocks per conversion but require a waiting period of 5µs for the conversion to be completed (Figure ). Most microcontrollers require that conversions occur in multiples of 8 clock cycles; 6 clock cycles per conversion, as shown in Figure 2, will typically be the most convenient way for a microcontroller to drive the MAX27/MAX27. Applications Information Power-On Reset The MAX27/MAX27 power up in normal operation (all internal circuitry active) and internal clock mode, waiting for a start bit. The contents of the output data register are cleared at power-up. Internal or External Reference The MAX27/MAX27 operate with either an internal or external reference. An external reference is connected to either REF or REFADJ (Figure 3). The REFADJ internal buffer gain is trimmed to.638v to provide 4.96V at REF from a 2.5V reference. 7-8

14 Serial 2-Bit ADCs MAX27/MAX27 DIN A/D STATE CONTROL BYTE Ø START SEL2 SEL SEL RNG BIP PD PD 3 START SEL2 SEL SEL RNG BIP PD PD START SEL2 SEL SEL RESULT Ø Figure. Internal Clock Mode, 3 Clocks/Conversion Timing D D D9 D8 D7 D6 D5 D4 D3 D2 D D CONTROL BYTE CONTROL BYTE 2 3 ACQUISITION CONVERSION ACQUISITION CONVERSION RESULT D D D9 D8 D7 D6 D5 D4 D CONTROL BYTE Ø CONTROL BYTE CB 2 DIN START SEL2 SEL SEL RNG BIP PD PD START SEL2 SEL SEL RNG BIP PD PD START 6 RESULT Ø D D D9 D8 D7 D6 D5 D4 D3 D2 D D RESULT D D D9 D8 D7 D6 D5 D4 D3 A/D STATE IDLE 6 ACQUISITION CONVERSION ACQUISITION CONVERSION Figure 2. Internal Clock Mode, 6 Clocks/Conversion Timing Internal Reference The internally trimmed 2.5V reference is amplified through the REFADJ buffer to provide 4.96V at REF. Bypass REF with a 4.7µF capacitor to AGND and REFADJ with a.µf capacitor to AGND (Figure 3a). The internal reference voltage is adjustable to ±.5% (±65 s) with the reference-adjust circuit of Figure. External Reference To use the REF input directly, disable the internal buffer by tying REFADJ to V DD (Figure 3b). Using the REFADJ input eliminates the need to buffer the reference externally. When a reference is applied at REFADJ, bypass REFADJ with a.µf capacitor to AGND. Note that when an external reference is applied at REFADJ, the voltage at REF is given by: V REF =.6384 V REFADJ (2.4 < V REF < 4.8) (Figure 3c). At REF and REFADJ, the input impedance is a minimum of kω for DC currents. During conversions, an external reference at REF must be able to deliver 4µA DC load currents and must have an output impedance of Ω or less. If the reference has higher output impedance or is noisy, bypass REF with a 4.7µF capacitor to AGND as close to the chip as possible. With an external reference voltage of less than 4.96V at REF or less than 2.5V at REFADJ, the increase in the ratio of RMS noise to the value (full-scale / 496) results in performance degradation (loss of effective bits). 7-82

15 Serial 2-Bit ADCs MAX27 MAX27 2.5V A V =.638 k Figure 3a. Internal Reference MAX27 MAX27 2.5V A V =.638 k REF REFADJ REF REFADJ Figure 3b. External Reference, Reference at REF MAX27 MAX27 A V =.638 REF 4.7µF C REF.µF 4.96V 4.7µF C REF V DD 4.7µF C REF Power-Down Mode To save power, configure the converter into low-current shutdown mode between conversions. Two programmable power-down modes are available in addition to a hardware shutdown. Select STBYPD or FULLPD by programming PD and PD in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the end of conversion. For example, if the control byte contains PD =, then the chip will remain powered up. If PD =, then the chip will power-down at the end of conversion. In all powerdown modes, the interface remains active and conversion results may be read. Input overvoltage protection is active in all power-down modes. The first logical on DIN after falls is interpreted as a start condition, and powers up the MAX27/ MAX27 from a software selected STBYPD or FULLPD condition. For hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown is asserted, it becomes effective immediately, and any conversion in progress is aborted. Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7µF capacitor at REF. This is a DC state that does not degrade after power-down of any duration. In FULLPD mode, only the bandgap reference is active. Connect a 33µF capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-up. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an ), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 8mV/ms slew rate, and add 5µs for settling time. MAX27/MAX27 2.5V k REFADJ 2.5V.µF Auto-Shutdown Selecting STBYPD on every conversion automatically shuts down the MAX27/MAX27 after each conversion without requiring any start-up time on the next conversion. Figure 3c. External Reference, Reference at REFADJ 7-83

16 Serial 2-Bit ADCs MAX27/MAX27 OUTPUT CODE FULL-SCALE TRANSITION = FS INPUT VOLTAGE () FS - 3/ 2 FS 496 OUTPUT CODE FS INPUT VOLTAGE () = +FS - 2 FS 496 Figure 4a. Unipolar Transfer Function Transfer Function Output data coding for the MAX27/MAX27 is binary in unipolar mode with = (FS / 496) and two s complement binary in bipolar mode with = [(2 FS ) / 496]. Code transitions occur halfway between successive-integer values. Figures 4a and 4b show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale values, refer to Table 3. Layout, Grounding, and Bypassing Careful printed circuit board layout is essential for best system performance. Use a ground plane for best performance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass V DD with.µf and 4.7µF capacitors to AGND to minimize highand low-frequency fluctuations. If the supply is excessively noisy, connect a 5Ω resistor between the supply and V DD, as shown in Figure 5. Figure 4b. Bipolar Transfer Function R* = 5Ω +5V V DD 4.7µF.µF AGND MAX27 MAX27 SUPPLY ** DGND +5V GND DGND DIGITAL CIRCUITRY * OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE. Figure 5. Power-Supply Grounding Connections 7-84

17 Serial 2-Bit ADCs V DD DGND N.C. DGND DIN N.C MAX27 MAX N.C. REF N.C. REFADJ CH7 CH6 CH5 CH4 CH3 CH2 TOP VIEW V DD DGND DGND N.C. N.C. N.C. DIN N.C Pin Configurations MAX27 MAX27 28 N.C. 27 REF 26 REFADJ 25 N.C. 24 N.C. 23 CH7 22 N.C. 2 CH6 2 CH5 9 CH4 8 CH3 MAX27/MAX27 SHDN 4 CH 2 7 CH2 AGND 2 3 CH SHDN 3 6 CH DIP AGND 4 SSOP 5 CH Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE INL () MAX27AENG MAX27BENG MAX27AEAI -4 C to +85 C -4 C to +85 C -4 C to +85 C 24 Narrow Plastic DIP 24 Narrow Plastic DIP 28 SSOP ±/2 ± ±/2 MAX27BEAI -4 C to +85 C 28 SSOP ± MAX27ACNG C to +7 C 24 Narrow Plastic DIP ±/2 MAX27BCNG C to +7 C 24 Narrow Plastic DIP ± MAX27ACAI C to +7 C 28 SSOP ±/2 MAX27BCAI C to +7 C 28 SSOP ± MAX27AENG -4 C to +85 C 24 Narrow Plastic DIP ±/2 MAX27BENG MAX27AEAI -4 C to +85 C -4 C to +85 C 24 Narrow Plastic DIP 28 SSOP ± ±/2 MAX27BEAI -4 C to +85 C 28 SSOP ± TRANSISTOR COUNT: 429 SUBSTRATE CONNECTED TO AGND Chip Information 7-85

18 Serial 2-Bit ADCs MAX27/MAX27 Package Information PDIPN.EPS 7-86

19 Serial 2-Bit ADCs Package Information (continued) SSOP.EPS MAX27/MAX

20 Serial 2-Bit ADCs MAX27/MAX27 NOTES 7-88