PART MAX1107EUB MAX1107CUB CONVST SCLK SHDN IN+ IN- REFOUT REFIN

Transcription

1 9-432; Rev ; 3/99 Single-Supply, Low-Power, General Description The low-power, 8-bit, single-channel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H), voltage reference, clock, and serial interface. The MAX6 is specified from +2.7 to +3.6 and coumes only 96. The MAX7 is specified from +4.5 to +5.5 and coumes only 7. The analog inputs are pin-configurable, allowing unipolar and singleended or differential operation. The full-scale analog input range is determined by the internal reference of (MAX6) or (MAX7), or by an externally applied reference ranging from to DD. The also feature a pin-selectable power-down mode that reduces power coumption to.5 when the device is not in use. The 3-wire serial interface directly connects to SPI, QSPI, and MICROWIRE devices without external logic. Conversio up to 25ksps are performed using the internal clock. The are available in a -pin µmax package with a footprint that is just 2% of an 8-pin plastic DIP. Portable Data Logging Hand-Held Measurement Devices Medical Itruments System Diagnostics Solar-Powered Remote Systems 4 2mA-Powered Remote Systems Receive-Signal-Strength Indicators Applicatio Features Single Supply: +2.7 to +3.6 (MAX6) +4.5 to +5.5 (MAX7) Low Power: 96 at +3 and 25ksps.5 in Power-Down Mode Pin-Programmable Configuration to Input oltage Range Internal Track/Hold Internal Reference: (MAX6) (MAX7) to Reference Input Range SPI/QSPI/MICROWIRE-Compatible Serial Interface Small -Pin µmax Package PART MAX6CUB MAX6EUB MAX7CUB MAX7EUB CONST Ordering Information TEMP. RANGE C to +7 C -4 C to +85 C PIN-PACKAGE µmax µmax C to +7 C µmax -4 C to +85 C µmax Functional Diagram Pin Configuration SHDN MAX6 MAX7 OUTPUT SHIFT REGISTER TOP IEW MAX6 MAX7 µmax SHDN CONST REFIN IN+ IN- REFOUT IN+ IN- REFOUT REFIN ANALOG INPUT MUX CONTROL LOGIC INTERNAL REFERENCE T/H INTERNAL OSCILLATOR CHARGE REDISTRIBUTION DAC SAR SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Maxim Integrated Products For free samples & the latest literature: or phone For small orders, phone

2 ABSOLUTE MAXIMUM RATINGS to to +6 IN+, IN-, REFIN, REFOUT, to to ( +.3) SHDN,, CONST to to +6 Continuous Power Dissipation (T A = +7 C) -pin µmax (derate 5.6mW/ C above +7 C)...444mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS MAX6 Operating Temperature Ranges MAX_CUB... C to +7 C MAX_EUB...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C ( = +2.7 to +3.6; IN- to ; f = 2MHz; 25ksps conversion rate; µf capacitor at REFOUT; external reference at REFIN; T A = T MIN to T MAX ; unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Bits Relative Accuracy (Note ) INL = 2.7 to 3.6 ±.5 ±.5 = 5.5 (Note 2) ±.2 LSB Differential Nonlinearity DNL No missing codes over temperature ± LSB Offset Error = 2.7 to 3.6 ±.2 ± = 5.5 (Note 2) ±.5 LSB Gain Error (Note 3) ± LSB Gain Temperature Coefficient ±.8 ppm/ C Total Unadjusted Error TUE T A = +25 C ± T A = T MIN to T MAX ±.5 LSB DYNAMIC PERFORMANCE (khz sine-wave input, 2.48p-p, 25ksps conversion rate) Signal-to-Noise Plus Distortion SINAD 49 db Total Harmonic Distortion (up to the 5th harmonic) THD -7 db Spurious-Free Dynamic Range SFDR 68 db Small-Signal Bandwidth BW -3dB -3dB rolloff.5 MHz Full-Power Bandwidth.8 MHz ANALOG INPUTS Input oltage Range (Note 4) IN_ IN+ to IN- REFIN Input Leakage Current On/off-leakage current, IN+ or IN- = or ±. ± Input Capacitance C IN 8 pf 2

3 ELECTRICAL CHARACTERISTICS MAX6 (continued) ( = +2.7 to +3.6; IN- to ; f = 2MHz; 25ksps conversion rate; µf capacitor at REFOUT; external reference at REFIN; T A = T MIN to T MAX ; unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRACK/HOLD Conversion Time t CON Figure 7 35 Track/Hold Acquisition Time t ACQ Aperture Delay Aperture Jitter <5 ps Internal Clock Frequency 4 khz External Clock Frequency Range For data trafer only 2 MHz INTERNAL REFERENCE Output oltage REFOUT REF Short-Circuit Current I REFSC (Note 5) 5 REF Tempco ±5 ppm/ C Load Regulation to.5ma (Note 6) 4 m Capacitive Bypass at REFOUT µf EXTERNAL REFERENCE Input oltage Range REFIN. +.5 Input Current at REFIN, full scale 2 POWER REQUIREMENTS Supply oltage = 3.6, C L = pf Supply Current (Notes 2, 7) I DD = 5.5, C L = pf 5 Power-Supply Rejection (Note 8) PSR Power down, = 3.6 Full-scale input, = 2.7 to 3.6 DIGITAL INPUTS (SHDN,, and CONST) Threshold oltage High IH 3.6 > 3.6 Threshold oltage Low IL Input Hysteresis HYST Input Current High I IH Input Current Low I IL Input Capacitance C IN ±.4 ± ± ± 5 m pf 3

4 ELECTRICAL CHARACTERISTICS MAX6 (continued) ( = +2.7 to +3.6; IN- to ; f = 2MHz; 25ksps conversion rate; µf capacitor at REFOUT; external reference at REFIN; T A = T MIN to T MAX ; unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER DIGITAL OUTPUT () Output High oltage Output Low oltage Three-State Leakage Current Three-State Output Capacitance Acquisition Time CONST Pulse Width High CONST Fall to Output Data alid CONST Rise to Output Enable Fall to Output Data alid Pulse Width High Pulse Width Low Low to Output Disable Low to CONST Rise SHDN Fall to Output Disable Wake-Up Time SYMBOL OH OL I L C OUT TIMING CHARACTERISTICS (Figures 6 and 7) t ACQ t CSPW t CON t D t DO t CH t CL t TR t SCC t SHDN t WAKE I SOURCE =.5mA I SINK = 5mA I SINK = 6mA Figure 6, High-Z Figure 6, High-Z CONDITIONS Figure, C LOAD = pf Figure, C LOAD = pf Figure 2, C LOAD = pf Figure 2, C LOAD = pf External reference Internal reference (Note 9) MIN TYP MAX ±. ± UNITS pf ms 4

5 ELECTRICAL CHARACTERISTICS MAX7 ( = +4.5 to +5.5; IN- = ; f = 2MHz; 25ksps conversion rate; µf capacitor at REFOUT; external reference at REFIN; T A = T MIN to T MAX ; unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Bits Relative Accuracy (Note ) INL ±.5 ±.5 LSB Differential Nonlinearity DNL No missing codes over temperature ± LSB Offset Error ±.2 ± LSB Gain Error (Note 3) ± LSB Gain Temperature Coefficient ±.8 ppm/ C Total Unadjusted Error TUE T A = +25 C ± T A = T MIN to T MAX ±.5 LSB DYNAMIC PERFORMANCE (khz sine-wave input, 4.96p-p, 25ksps conversion rate) Signal-to-Noise Plus Distortion SINAD 49 db Total Harmonic Distortion (up to the 5th harmonic) THD -7 db Spurious-Free Dynamic Range SFDR 68 db Small-Signal Bandwidth BW -3dB -3dB rolloff.5 MHz Full-Power Bandwidth.8 MHz ANALOG INPUTS Input oltage Range (Note 4) IN_ IN+ to IN- REFIN Input Leakage Current On/off-leakage current, IN+ or IN- = or ±. ± Input Capacitance C IN 8 pf TRACK/HOLD Conversion Time t CON Figure 7 35 Track/Hold Acquisition Time t ACQ Aperture Delay Aperture Jitter <5 ps Internal Clock Frequency 4 khz External Clock Frequency Range For data trafer only 2 MHz INTERNAL REFERENCE Output oltage REFOUT REF Short-Circuit Current I REFSC 5 ma REF Tempco ±5 ppm/ C Load Regulation to.5ma (Note 6) 4 m Capacitive Bypass at REFOUT µf 5

6 ELECTRICAL CHARACTERISTICS MAX7 (continued) ( = +4.5 to +5.5; IN- = ; f = 2MHz; 25ksps conversion rate; µf capacitor at REFOUT; external reference at REFIN; T A = T MIN to T MAX ; unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER EXTERNAL REFERENCE Input oltage Range Input Current POWER REQUIREMENTS Supply oltage Supply Current (Notes 2, 7) Power-Supply Rejection (Note 8) SYMBOL REFIN PSR CONDITIONS = 5.5, C L = pf, full-scale input DIGITAL INPUTS (SHDN,, and CONST) Threshold oltage High IH Threshold oltage Low IL Input Hysteresis HYST Input Current High I IH Input Current Low I IL Input Capacitance C IN DIGITAL OUTPUT () Output High oltage OH I SOURCE =.5mA Output Low oltage OL I SINK = 5mA I SINK = 6mA Three-State Leakage Current I L Figure 6, High-Z Three-State Output Capacitance C OUT Figure 6, High-Z TIMING CHARACTERISTICS (Figures 6 and 7) Acquisition Time t ACQ CONST Pulse Width High t CSPW I DD MIN TYP MAX Power down, = 4.5 to External reference = 4.96, full-scale input, = 4.5 to ±.4 ±4.2 3 UNITS at REFIN, full scale 2 5 ± ± ±. ± 5 m pf pf CONST Fall to Output Data alid t CON 35 CONST Rise to Output Enable t D Figure, C LOAD = pf 24 Fall to Output Data alid t DO Figure, C LOAD = pf 2 2 Pulse Width High t CH 2 6

7 ELECTRICAL CHARACTERISTICS MAX7 (continued) ( = +4.5 to +5.5; IN- = ; f = 2MHz; 25ksps conversion rate; µf capacitor at REFOUT; external reference at REFIN; T A = T MIN to T MAX ; unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER Pulse Width Low Low to Output Disable Low to CONST Rise SHDN Fall to Output Disable Wake-Up Time SYMBOL t CL t TR t SCC t SHDN t WAKE CONDITIONS Figure 2, C LOAD = pf Figure 2, C LOAD = pf External reference Internal reference (Note 9) MIN TYP MAX Note : Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 2: See Typical Operating Characteristics. Note 3: REFOUT = (MAX6), REFOUT = (MAX7), offset nulled. Note 4: Common-mode range (IN+, IN-) to. Note 5: REFOUT supplies typically 2.5mA under normal operating conditio. Note 6: External load should not change during the conversion for specified accuracy. Note 7: Power coumption with CMOS levels. Note 8: Measured as FS (2.7) - FS (3.6) for MAX6, and measured as FS (4.5) - FS (5.5) for MAX7. Note 9: µf at REFOUT, internal reference settling to.5lsb UNITS ms Typical Operating Characteristics ( = +3. (MAX6), = +5. (MAX7); f = 2MHz; 25ksps conversion rate; external reference; µf at REFOUT; T A = +25 C; unless otherwise noted.) SUPPLY CURRENT () SUPPLY CURRENT vs. SUPPLY OLTAGE MAX6 ( = 2.7 TO 5.5) MAX7 ( = 4.5 TO 5.5) INTERNAL REFERENCE C LOAD = pf = C LOAD = pf = SUPPLY OLTAGE () C LOAD = 47pF = MAX6/7- SUPPLY CURRENT () SUPPLY CURRENT vs. TEMPERATURE = C LOAD = pf INTERNAL REFERENCE MAX7, = 5. MAX6, = TEMPERATURE ( C) MAX6/7-2 SHUTDOWN SUPPLY CURRENT () SHUTDOWN SUPPLY CURRENT vs. SUPPLY OLTAGE SUPPLY OLTAGE () MAX6/7-3 7

8 Typical Operating Characteristics (continued) ( = +3. (MAX6), = +5. (MAX7); f = 2MHz; 25ksps conversion rate; external reference; µf at REFOUT; T A = +25 C; unless otherwise noted.) OFFSET ERROR (LSB) OFFSET ERROR vs. SUPPLY OLTAGE SUPPLY OLTAGE () MAX6/7-4 OFFSET ERROR (LSB) OFFSET ERROR vs. TEMPERATURE TEMPERATURE ( C) MAX6/7-5 OFFSET ERROR (LSB) OFFSET ERROR vs. REFERENCE OLTAGE REFERENCE OLTAGE () MAX6/ GAIN ERROR vs. SUPPLY OLTAGE MAX6/ GAIN ERROR vs. TEMPERATURE MAX6/ GAIN ERROR vs. REFERENCE OLTAGE MAX6/7-9 GAIN ERROR (LSB) GAIN ERROR (LSB) GAIN ERROR (LSB) SUPPLY OLTAGE () TEMPERATURE ( C) REFERENCE OLTAGE ().3.2 INTEGRAL NONLINEARITY vs. SUPPLY OLTAGE MAX6/ DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE MAX6/ DIFFERENTIAL NONLINEARITY vs. SUPPLY OLTAGE MAX6/7-2 INL (LSB). -. DNL (LSB) DNL (LSB) SUPPLY OLTAGE () DIGITAL CODE SUPPLY OLTAGE () 8

9 Typical Operating Characteristics (continued) ( = +3. (MAX6), = +5. (MAX7); f = 2MHz; 25ksps conversion rate; external reference; µf at REFOUT; T A = +25 C; unless otherwise noted.) INL (LSB) PIN INTEGRAL NONLINEARITY vs. DIGITAL CODE DIGITAL CODE CONERSION TIME () NAME IN+ IN- REFOUT REFIN CONST SHDN MAX6/7-3 AMPLITUDE (db) CONERSION TIME vs. TEMPERATURE = 3 = TEMPERATURE ( C) FFT PLOT f IN+ =.34kHz, 2p-p f SAMPLE = 2588Hz MAX6/7-6 FREQUENCY (khz) MAX6/7-4 CONERSION TIME () CONERSION TIME vs. SUPPLY OLTAGE SUPPLY OLTAGE () NORMALIZED REFERENCE OLTAGE vs. TEMPERATURE Pin Description FUNCTION Positive Supply oltage Positive Analog Input. Sampled. Input range from to. Negative Analog Input. Input range from to. Ground. Internal Reference Output. Bypass with µf to ground for MAX6, 4.96 for MAX7. Reference oltage Input. Reference voltage for analog-to-digital conversion. Connect REFOUT to REFIN for internal reference. Input range from to. Conversion Start Input. Toggle CONST high for minimum and then low to start internal conversion. Data is not clocked out unless CONST is low. Active-Low Shutdown. Connect to for normal operation. Serial Data Output. Data is clocked out on the falling edge of. is high impedance in shutdown or after all data is clocked out. Serial Clock Input. Clocks data out of serial interface. NORMALIZED REFERENCE OLTAGE TEMPERATURE ( C) MAX6/7-7 MAX6/7-5 9

10 3k C LOAD Detailed Description The analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to an 8-bit digital output. A simple serial interface provides easy interface to microprocessors (µps). No external hold capacitors are required. All of the operating modes are pin configurable: internal or external reference, single-ended or pseudo-differential unipolar conversion, and power down. Figure 3 shows the typical operating circuit. Analog Inputs Track/Hold The input architecture of the ADCs is illustrated in Figure 4 s equivalent-input circuit of and is composed of the T/H, the input multiplexer, the input comparator, the switched capacitor DAC, and the auto-zero rail. The device is in acquisition mode most of the time. During the acquisition interval, the positive input (IN+) is tracked and is connected to the holding capacitor (CHOLD). The acquisition interval ends with the falling edge of CONST. At this point the T/H switch ope and CHOLD is connected to the negative input (IN-), retaining charge on CHOLD as a sample of the signal at IN+. Once conversion is complete the T/H retur immediately to its tracking mode. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal s source impedance is high, the acquisition time lengthe, and more time must be allowed between conversio. The acquisition time, tacq, is the minimum time needed for the signal to be acquired. It is calculated by: tacq = 6(RS + RIN)8pF DD 3k C LOAD a) OL to OH b) High-Z to OL and OH to OL Figure. Load Circuits for Enable Time 3k C LOAD 3k C LOAD a) OH to High-Z b) OL to High-Z Figure 2. Load Circuits for Disable Time ANALOG INPUTS µf IN+ REFOUT REFIN SHDN CONST Figure 3. Typical Operating Circuit REFIN IN+ MAX6 MAX7 IN- IN- CAPACITIE DAC C HOLD 8pF HOLD.µF µf R IN 6.5k TRACK ON OFF CPU I/O SCK (SK) MISO (SI) COMPARATOR AUTOZERO RAIL Figure 4. Equivalent Input Circuit

11 where RIN = 6.5kΩ, RS = the source impedance of the input signal, and tacq must never be less than. This is easily achieved by respecting the minimum CONST high interval required and the time required to clock the data out. Pseudo-Differential Input The input configuration is pseudodifferential to the extent that only the signal at the sampled input (IN+) is stored in the holding capacitor (CHOLD). IN- must remain stable within ±.5LSB (±.LSB for best results) in relation to during a conversion. If a varying signal is applied at the IN- input, its amplitude and frequency need to be limited. The following equatio determine the relatiohip between the maximum signal amplitude and its frequency to maintain ±.5LSB accuracy: Assuming a sinusoidal signal at the IN- input, under the maximum voltage variation is determined by υ IN- υ max IN- t 2 π f IN- = ( IN- ) sin(2πft) LSB tcon = ( ) = REFIN 8 2 t CON a 6Hz signal at IN- with an amplitude of.2 will generate ±.5LSB of error. This is with a 35 conversion time (maximum tcon) and a reference voltage of When a DC reference voltage is used at IN-, connect a.µf capacitor from IN_ to to minimize noise at the input. The common-mode input range of IN+ and IN- is to +DD. Full-scale is achieved when (IN- - IN+) = REFIN. IN+ must be higher than IN-. Conversion Process The comparator negative input is connected to the autozero rail. Since the device requires only a single supply, the ZERO node at the input of the comparator equals DD/2. The capacitive DAC restores node ZERO to have difference at the comparator inputs within the limits of 8-bit resolution. This action is equivalent to traferring a charge of 8pF( IN+ - IN- ) from CHOLD to the binary-weighted capacitive DAC which, in turn, forms a digital representation of the analog-input signal. Input oltage Range Internal protection diodes that clamp the analog input to DD and allow the input pi (IN+ and IN-) to swing from ( -.3) to (DD +.3) without damage. However, for accurate conversio, the inputs must not exceed (DD + 5m) or be less than ( - 5m). The input range is from to DD. The output code is invalid (code zero) when a negative input voltage (or a negative differential input voltage) is applied. The reference input-voltage range at REFIN is from to (DD + 5m). Input Bandwidth The ADC s input tracking circuitry has a.5mhz smallsignal bandwidth, so it is possible to digitize highspeed traient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Serial Interface The have a 3-wire serial interface. The CONST and inputs are used to control the device, while the three-state pin is used to access the result of conversion. The serial interface provides easy connection to microcontrollers with SPI, QSPI, and MICROWIRE serial interfaces at clock rates up to 2MHz. For SPI and QSPI, set CPOL = CPHA = in the SPI control registers of the microcontroller. Figure 5 shows the common serial-interface connectio. Digital Inputs and Outputs The logic levels of the digital inputs are set to accept voltage levels from both 3 and 5 systems regardless of the supply voltages. A conversion is started by toggling CONST. CONST idles low and needs to be set high for at least to perform the autozero adjustment. CONST must remain low during conversion and until the result of conversion has been clocked out. After CONST is set low, allow 35 for the conversion to be completed. While the internal conversion is in progress is low. Conversion is controlled by an internal 4kHz oscillator. The MSB is present at the pin immediately after conversion is completed. The conversion result is clocked out at the pin and is coded in straight binary (Figure 9). Data is clocked out at s falling edge in MSB-first format at rates up to 2MHz. Once all data bits are clocked out, goes high impedance at the falling edge of the eighth pulse.

12 a) SPI b) QSPI c) MICROWIRE I/O SCK MISO SS CS SCK MISO SS I/O SK SI CONST CONST CONST Figure 5. Common Serial-Interface Connectio MAX6 MAX7 MAX6 MAX7 MAX6 MAX7 Starting before conversion is complete corrupts the conversion in progress, and the data clocked out at does not represent the input signal. Bringing CONST high at anytime during a conversion or while the data is clocked out will result in an incorrect conversion. A new conversion can be restarted only if all eight data bits of conversion have been clocked out. Toggle CONST after all data is clocked out to restart a new conversion. SHDN is used to place the in lowpower mode (see Power-Down section). In this mode is high impedance and any conversion in progress is stopped immediately. If a conversion is stopped by SHDN going low, the device must be reset by waiting 35 and clearing the output register with eight s before the next conversion. How to Perform a Conversion The converts an input signal using the internal clock. This frees the µp from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the µp s convenience at any clock rate up to 2MHz. Figures 6 and 7 show the serial interface timing characteristics. CONST idles low. Toggle CONST high for at least to perform the autozero adjustment. After CONST goes low, conversion starts immediately. Allow 35 for the internal conversion to complete and issue the MSB of the conversion at. CONST needs to be held low once a conversion is started, while should remain low during conversion for best noise performance. An internal register stores data when the conversion is in progress. clocks the CONST t CSPW (MIN) (MAX) 8 HIGH-Z MSB D7 LSB D6 D5 D4 D3 D2 D D HIGH-Z A/D STATE ACQ CONERSION t CON = 35 (MAX) ACQUISITION Figure 6. Conversion Timing Diagram 2

13 t CSPW CONST t D Figure 7. Detailed Serial Interface Timing t CON t CH t CL # #8 t DO t SCC t TR t D data out of this register at any time after the conversion is complete. After the eighth data-bit has clocked out, goes high impedance and remai so with additional s. Normally leave CONST low until a new conversion needs to be started. CONST should be high for a maximum of to maintain the 8-bit accuracy of the Autozero Circuit. The acquisition time, tacq, starts immediately after the end of conversion and a new conversion can be started immediately after all data has been clocked out by toggling CONST high. Figure 8 shows a timing diagram for a conversion at the data rate of 4ksps. Typically 2 are necessary for the conversion to complete, 4 for reading the eight bits of data with a serial clock of 2MHz, and to complete the zero rail adjustment and acquisition. The conversion time is guaranteed to be less than 35, therefore the data rate should be limited to 25ksps unless the conversion time for the specific condition is known. Conversion time can be determined by measuring the time between CONST falling edge and rising edge with a full-scale input voltage. Applicatio Information Power-On Reset When power is first applied with SHDN high or connected to, the is in track mode. Conversion can be started by toggling CONST high to low as soon as the reference is settled when using the internal reference, or after 2 when an external reference is used. Powering up the with t CON 5/div Figure 8. 4ksps Timing Diagram CONST 5/div 5/div 5/div CONST low will not start a conversion. No conversio should be performed until the reference voltage (internal or external) has stabilized. Shutdown Operation Pulling SHDN low places the converter in low-current power-down mode. In this state the converter draws typically.5. In shutdown the analog biasing circuit and the internal bandgap reference are powered down, and goes high impedance. The conversion stops coincidentally with SHDN going low. If shutdown occurs during a conversion, power up, wait 35, and clock eight times. 3

14 When operating at speeds below the maximum sampling rate, the s power-down mode can save coiderable power by placing the converter in a low-current shutdown state between conversio. Pull SHDN low after the conversion byte has been read to shut down the device completely. CONST should remain low most of the time and toggled high for ( max) for the autozero adjustment. An external reference is recommended for best accuracy when using the shutdown feature. This requires only 2 for the internal biasing circuit to stabilize before starting a new conversion. Alternatively, the internal reference can be used, but additional time is required for the reference to stabilize (when bypassed by a µf capacitor; at data rates above ksps, the reference stabilizes within LSB in 2). If the reference is completely discharged it requires 2ms to settle. No conversio should be performed until the reference voltage has stabilized. Internal or External oltage Reference An external reference between and should be connected directly at the REFIN pin. To use the internal reference, connect REFOUT directly to REFIN and bypass REFOUT with a µf capacitor. The DC input impedance at REFIN is extremely high, coisting of leakage current only (typically na). During a conversion, the reference must be able to deliver up to 2 average load current and have an output impedance of kω or less at the conversion clock frequency. If the reference has higher output impedance or is noisy, bypass it close to the REFIN pin with a.µf capacitor. The internal reference is active as long as SHDN is high and powers down when SHDN is low. OUTPUT CODE FULL-SCALE TRANSITION (IN-) 2 3 INPUT OLTAGE (LSB) FS FS - LSB Figure 9. Input/Output Trafer Function FS = REFIN + IN- LSB = REFIN 256 Trafer Function Figure 9 depicts the input/output trafer function. Code traitio occur at integer LSB values. Output coding is binary; with a 2.48 reference LSB = 8m (REFIN / 256). For single-ended operation connect INto. Full-scale is achieved at IN+ = REFIN - LSB. For pseudo-differential operation the IN- voltage range is from to DD, where full-scale is achieved at IN+ = REFIN + IN- - LSB. IN+ should not be higher than DD + 5m. Negative input voltages are invalid and give a zero output code. oltages greater than fullscale give an all ones output code. 4

15 Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should eure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or run digital lines underneath the ADC package. Figure shows the recommended system-ground connectio. A single-point analog ground (star-ground point) should be established at the A/D ground. Connect all analog grounds to the star ground. No digital-system ground should be connected to this point. The ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the DD power supply may affect the comparator in the ADC. Bypass the supply to the star ground with.µf and µf capacitors close to the DD pin of the. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a Ω resistor can be connected to form a lowpass filter. IN- SYSTEM POWER SUPPLIES µf.µf MAX6 MAX7 Figure. Power-Supply Connectio Ω D +3/+5 DIGITAL CIRCUITRY TRANSISTOR COUNT: 2373 Chip Information 5

16 Package Information LUMAX.EPS Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 6 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.