REF+ 4-BIT FLASH ADC (4MSBs) 4-BIT DAC REF+ 4-BIT FLASH ADC (4LSBs) TIMING AND CONTROL A0 A1 A2 REF- PWRDN RD CS MODE INT WR/RDY

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1 9-83; Rev ; 8/96 +5, Msps, 4 & 8-Channel, General Description The are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital converters (ADCs). They operate from a single +5 supply and use a half-flash technique to achieve a 66 conversion time (Msps). A power-down (PWRDN) pin reduces current coumption typically to µa. The devices return from power-down mode to normal operating mode in less than 2, allowing large supplycurrent reductio in burst-mode applicatio (in burst mode, the ADC wakes up from a low-power state at specified intervals to sample the analog input signals). Both converters include a track/hold, enabling the ADC to digitize fast analog signals. Microprocessor (µp) interfaces are simplified because the ADC can appear as a memory location or I/O port without external interface logic. The data outputs use latched, three-state buffer circuitry for direct connection to an 8-bit parallel µp data bus or system input port. The input/reference configuration enables ratiometric operation. The 4-channel MAX4 is available in a 24-pin DIP or SSOP. The 8-channel is available in a 28-pin DIP or SSOP. For +3 applicatio, refer to the MAX3/MAX7 data sheet. Applicatio High-Speed DSP Portable Equipment Remote Data Acquisition Communicatio Systems Features Single +5 Supply Operation 4 (MAX4) or 8 () Analog Input Channels Low Power: 4mW (operating mode) 5µW (power-down mode) Total Unadjusted Error LSB Fast Conversion Time: 66 per Channel No External Clock Required Internal Track/Hold MHz Full-Power Bandwidth Internally Connected 8th Channel Monitors Reference oltage () Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX4CNG MAX4CAG MAX4C/D C to +7 C C to +7 C C to +7 C 24 Narrow Plastic DIP 24 SSOP Dice* MAX4ENG -4 C to +85 C 24 Narrow Plastic DIP MAX4EAG -4 C to +85 C 24 SSOP MAX4MRG -55 C to +25 C 24 Narrow CERDIP** Ordering Information continued on last page. *Dice are specified at T A = +25 C, DC parameters only. **Contact factory for availability. Pin Configuratio appear on last page. Functional Diagram *IN7 *IN6 *IN5 IN4 IN3 IN2 IN *IN8 MUX ADDRESS LATCH DECODE Σ 6 4-BIT DAC 4-BIT FLASH ADC (4MSBs) 4-BIT FLASH ADC (4LSBs) TIMING AND CONTROL THREE- STATE OUTPUT DRIERS D7 D6 D5 D4 D3 D2 D D * ONLY A A A2 PWRDN RD MODE INT WR/RDY Maxim Integrated Products For free samples & the latest literature: or phone

2 ABSOLUTE MAXIMUM RATINGS to GND to +7 Digital Input oltage to GND to ( +.3) Digital Output oltage to GND to ( +.3) to GND to ( +.3) to GND to ( +.3) IN_ to GND to ( +.3) Continuous Power Dissipation (T A = +7 C) 24-Pin Narrow Plastic DIP (derate 3.33mW/ C above +7 C)...8W 24-Pin SSOP (derate 8.mW/ C above +7 C)...64mW 24-Pin Narrow CERDIP (derate 2.5mW/ C above +7 C)...W 28-Pin Wide Plastic DIP (derate 4.29mW/ C above +7 C)...4W 28-Pin SSOP (derate 9.52mW/ C above +7 C)...762mW 28-Pin Wide CERDIP (derate 6.67mW/ C above +7 C)...33W Operating Temperature Ranges C... C to +7 C E...-4 C to +85 C M C to +25 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI ( = +5 ±5%, = 5, = GND, Read Mode (MODE = GND), T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY (Note ) Resolution N 8 Bits Total Unadjusted Error TUE ± LSB Differential Nonlinearity DNL No-missing-codes guaranteed ± LSB Zero-Code Error ± LSB Full-Scale Error ± LSB Channel-to-Channel Mismatch ±/4 LSB DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio SINAD MAX_C/E, f SAMPLE = MHz, f IN_ = 95.8kHz MAX_M, f SAMPLE = 74kHz, f IN_ = 95.7kHz db Total Harmonic Distortion THD MAX_C/E, f SAMPLE = MHz, f IN_ = 95.8kHz MAX_M, f SAMPLE = 74kHz, f IN_= 95.7kHz -5-5 db Spurious-Free Dynamic Range SFDR MAX_C/E, f SAMPLE = MHz, f IN_ = 95.8kHz MAX_M, f SAMPLE = 74kHz, f IN_ = 95.7kHz 5 5 db Input Full-Power Bandwidth IN_ = 5p-p MHz Input Slew Rate, Tracking 3. 5 /µs ANALOG INPUT Input oltage Range IN_ Input Leakage Current I IN_ GND < IN_ < ±3 µa Input Capacitance C IN_ 32 pf REFERENCE INPUT Reference Resistance R REF 2 4 kω Input oltage Range Input oltage Range GND 2

3 ELECTRICAL CHARACTERISTI (continued) ( = +5 ±5%, = 5, = GND, Read Mode (MODE = GND), T A = T MIN to T MAX, unless otherwise noted.) PARAMETER LOGIC INPUTS Input High oltage Input Low oltage Input High Current Input Low Current Input Capacitance (Note 2) LOGIC OUTPUTS Output Low oltage Output High oltage Three-State Current Three-State Capacitance (Note 2) POWER REQUIREMENTS Supply oltage Supply Current Power-Down Current Power-Supply Rejection SYMBOL INH INL I INH I INL C IN OL OH I LKG C OUT I DD PSR, WR, RD, PWRDN, A, A, A2 MODE, WR, RD, PWRDN, A, A, A2 MODE, RD, PWRDN, A, A, A2 WR MODE, WR, RD, PWRDN, MODE, A, A, A2, WR, RD, PWRDN, MODE, A, A, A2 I SINK =.6mA, INT, D D7 RDY, I SINK = 2.6mA I SOURCE = 36µA, INT, D D7 D D7, RDY, digital outputs = to D D7, RDY = RD =, PWRDN = CONDITIONS MAX_C MAX_E/M = RD =, PWRDN = (Note 3) = 4.75 to 5.25, REF = 4.75 MIN TYP MAX ± ±3 5 2 ± ± ±/6 ±/4 UNITS µa µa pf µa pf ma µa LSB Note 2: Note 3: Guaranteed by design. Power-down current increases if logic inputs are not driven to GND or. 3

4 TIMING CHARACTERISTI ( = +4.75, T A = +25 C, unless otherwise noted.) (Note 4) PARAMETER Conversion Time (WR-RD Mode) Conversion Time (RD Mode) Power-Up Time to RD, WR Setup Time to RD, WR Hold Time to RDY Delay Data-Access Time (RD Mode) RD to INT Delay (RD Mode) Data Hold Time Minimum Acquisition Time WR Pulse Width Delay Between WR and RD Pulses RD Pulse Width (WR-RD Mode) Data-Access Time (WR-RD Mode) RD to INT Delay WR to INT Delay RD Pulse Width (WR-RD Mode) Data-Access Time (WR-RD Mode) WR to INT Delay Data-Access Time after INT Multiplexer Address Hold Time T A = +25 C T A = T MIN to T MAX SYMBOL CONDITIONS ALL GRADES MAX_C/E MAX_M MIN TYP MAX MIN MAX MIN MAX t RD < t INTL, C L = 2pF 66 t CWR (Note 5) C L = pf t CRD t UP t S t H t RDY t ACC t INTH t DH t WR t RD t READ t ACC t RI t INTL t READ2 t ACC2 t IHWR t ID t AH C L = 5pF, R L = 5.kΩ to C L = pf (Note 5) C L = 5pF (Note 6) (Note 7) t RD < t INTL, determined by t ACC t RD < t INTL, C L = pf (Note 5) C L = 5pF t RD > t INTL, determined by t ACC2 t RD > t INTL, C L = pf (Note 5) Pipelined mode, C L = 5pF Pipelined mode, C L = pf t CRD t CRD t CRD Note 4: Input control signals are specified with t r = t f = 5, % to 9% of 5, and timed from a voltage level of.6. Note 5: See Figure for load circuit. Parameter defined as the time required for the output to cross.8 or 2.4. Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change.5. Note 7: Also defined as the Minimum Address-alid to Convert-Start Time UNITS µs µs 4

5 Typical Operating Characteristics ( = +5, T A = +25 C, unless otherwise noted.) tcrd (NORMALIZED TO ALUE AT DD = +5, +25 C) CONERSION TIME vs. AMBIENT TEMPERATURE = = +5 = TEMPERATURE ( C) MAX4/8- EFFECTIE NUMBER OF BITS EFFECTIE NUMBER OF BITS vs. INPUT FREQUENCY (WR-RD MODE) f SAMPLE = MHz IN = 4.96p-p k k k INPUT FREQUENCY (Hz) M MAX4/8-2 POWER DISSIPATION (mw) AERAGE POWER CONSUMPTION vs. SAMPLING RATE USING PWRDN MAX4/8-3 RATIO (db) SIGNAL-TO-NOISE RATIO = 4.75 INPUT FREQUENCY = 95.8ksps IN = 4.72p-p SAMPLE FREQUENCY = MHz SNR = 48.2dB MAX4/8-4 k k k M SAMPLING RATE (CONERSIONS/SEC) FREQUENCY (khz) TUE (LSB) TOTAL UNADJUSTED ERROR vs. POWER-UP TIME MAX4/8-6 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE (EXCLUDING REFERENCE CURRENT) MAX4/ POWER-UP TIME, t UP () TEMPERATURE ( C) 6 4 5

6 Pin Description PIN MAX , 8, ,, 2 NAME IN6 IN5 IN4 IN3 IN2 IN MODE D D, D2, D3 RD Analog Input Channel 6 Analog Input Channel 5 Analog Input Channel 4 Analog Input Channel 3 Analog Input Channel 2 Analog Input Channel FUNCTION Mode Selection Input. Internally pulled low with a 5µA current source. MODE = activates read mode; MODE = activates write-read mode (see Digital Interface Section). Three-State Data Output (LSB) Three-State Data Outputs Read Input. RD must be low to access data (see Digital Interface section). 3 INT GND Interrupt Output. INT goes low to indicate end of conversion (see Digital Interface section). Ground Lower Limit of Reference Span. sets the zero-code voltage. Range is GND <. 4 6 Upper Limit of Reference Span. sets the full-scale input voltage. Range is <. Internally hard-wired to IN8 (Table ). 5 7 WR/RDY Write-Control Input/Ready-Status Output (see Digital Interface section) 6 8 Chip-Select Input. must be low for the device to recognize WR or RD inputs. 7, 8, 9 9, 2, 2 D4, D5, D6 Three-State Data Outputs 2 22 D7 Three-State Data Output (MSB) 23 A2 Multiplexer Channel Address Input (MSB) 2 24 A Multiplexer Channel Address Input A Multiplexer Channel Address Input (LSB) PWRDN Power-Down Input. PWRDN reduces supply current when low Positive Supply, IN7 Analog Input Channel 7 6

7 Detailed Description Converter Operation The use a half-flash conversion technique (see Functional Diagram) in which two 4-bit flash ADC sectio achieve an 8-bit result. Using 5 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate both the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower four data bits (LSBs). An internal analog multiplexer enables the devices to read four (MAX4) or eight () different analog voltages under microprocessor (µp) control. One of the s analog channels, IN8, is internally hardwired and always reads when selected. DATA OUTPUTS R L = 3k C L DATA OUTPUTS R L = 3k a) HIGH-Z TO OH b) HIGH-Z TO OL Figure. Load Circuits for Data-Access Time Test DATA OUTPUTS 3k pf DATA OUTPUTS C L pf a) OH TO HIGH-Z b) OL TO HIGH-Z Figure 2. Load Circuits for Data-Hold Time Test 3k Power-Down Mode In burst-mode or low sample-rate applicatio, the can be shut down between conversio, reducing supply current to microamp levels (see Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to µa when powered from a single +5 supply. A logic high on PWRDN wakes up the, and the selected analog input enters the track mode. The signal is fully acquired after 36 (this includes both the power-up delay and the track/hold acquisition time), and a new conversion can be started. If the power-down feature is not required, connect PWRDN to DD. For minimum current coumption, keep digital inputs at the supply rails in power-down mode. Refer to the Reference section for information on reducing reference current during power-down. Digital Interface The have two basic interface modes, which are set by the MODE pin. When MODE is low, the converters are in read mode; when MODE is high, the converters are set up for write-read mode. The A, A, and A2 inputs control channel selection, as shown in Table. The address must be valid for a minimum time,, before the next conversion starts. Table. Truth Table for Input Channel Selection MAX4 A A A2 A A SELECTED CHANNEL IN IN2 IN3 IN4 IN5 IN6 IN7 IN8 (reads if selected) Read Mode (MODE = ) In read mode, conversio and data access are controlled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of. Initiate a conversion by driving and RD low. With µps that can be forced into a wait state, hold RD low until output data appears. The µp starts the conversion, waits, and then reads data with a single read itruction. 7

8 In read mode, WR/RDY is configured as a status output (RDY), so it can drive the ready or wait input of a µp. RDY is an open-collector output (no internal pull-up) that goes low after the falling edge of and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and retur high on the rising edge of or RD. Write-Read Mode (MODE = ) Figures 4 and 5 show the operating sequence for writeread mode. The comparator inputs track the analog input voltage for the duration of. The conversion is initiated by a falling edge of WR. When WR retur high, the result of the four-msbs flash is latched into the output buffers and the conversion of the four-lsbs flash starts. INT goes low, indicating conversion end, and the lower four data bits are latched into the output buffers. The data is then accessible after RD goes low (see Timing Characteristics). A minimum acquisition time () is required from INT going low to the start of another conversion (WR going low). Optio for reading data from the converter include using internal delay, reading before delay, and pipelined operation (discussed in the following sectio). Using Internal Delay The µp waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With low, data outputs D D7 can be accessed by pulling RD low. INT is then reset by the rising edge of or RD. Fastest Conversion: Reading Before Delay Figure 5 shows an external method of controlling the conversion time. The internally generated delay (tintl) varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the rising edge of WR, but before INT goes low. This completes the conversion and enables the output buffers that contain the conversion result (D D7). INT also goes low after the falling edge of RD and is reset on the rising edge of RD or. The total conversion time is therefore: twr + trd + tacc = 66. WR A A2 RD INT D D7 t S t AH ADDRESS ALID (N) t WR t H t INTL t RD t ACC2 t S ADDRESS ALID (N + ) t READ2 ALID DATA (N) t DH Figure 4. Write-Read Mode Timing (t RD > t INTL) (MODE = ) t H t INTH PWRDN RD A A2 RDY INT t UP t S ADDRESS ALID (N) ACQ WITH EXTERNAL t RDY PULL-UP t H ADDRESS ALID (N + ) t AH t INTH WR t S A A2 RD INT t WR t AH ADDRESS ALID (N) t H t RD t INTL t S t READ t RI ADDRESS ALID (N + ) t H D D7 t CRD t ACCO ALID DATA (N) t DH D D7 t ACC t CWR ALID DATA (N) t DH t INTH Figure 3. Read Mode Timing (MODE = ) Figure 5. Write-Read Mode Timing (t RD < t INTL) (MODE = ) 8

9 Pipelined Operation Besides the two standard write-read-mode optio, pipelined operation can be achieved by connecting WR to RD (Figure 6). With low, driving WR and RD low initiates a conversion and concurrently reads the result of the previous conversion. Analog Coideratio Reference Figures 7a, 7b, and 7c show typical reference connectio. The voltages at and set the ADC s analog input range (see Figure ). The voltage at REFdefines the input that produces an output code of all zeros, and the voltage at defines the input that produces an output code of all ones. The internal resistance from to can be as low as kω, and current will flow through it even when the are shut down. Figure 7d shows how an N-channel MOSFET can be connected to RD, WR A A2 INT D D7 t S t AH ADDRESS ALID (N) t WR OLD DATA (N - ) t H t IHWR t INTL ADDRESS ALID (N + ) NEW DATA (N) Figure 6. Pipelined Mode Timing (WR = RD) (MODE = ) t ID µF.µF IN+ IN- IN_ GND MAX µF.µF * CURRENT PATH MUST STILL EXIST FROM IN- TO GND IN- R* IN µF IN_ GND MAX4.µF Figure 7a. Power Supply as Reference Figure 7c. Input Not Referenced to GND µF.µF MX584 IN+ IN- C.µF IN_ GND MAX4 PWRDN +5 MAX874 N-FET*.µF C 3.3µF.µF MAX4 PWRDN * IRML242 Figure 7b. External Reference, 4.96 Full Scale Figure 7d. An N-channel MOSFET switches off the reference load during power-down 9

10 to break this current path during power-down. The FET should have an on-resistance of less than 2Ω with a 5 gate drive. When is switched, as in Figure 7d, a new conversion can be initiated after waiting a period of time equal to the power-up delay (tup) plus the N- channel FET s turn-on time. Although is frequently connected to DD, the circuit of Figure 7d uses a low-current, low-dropout, 4.96 voltage reference: the MAX874. Since the MAX874 cannot continuously furnish enough current for the reference resistance, this circuit is intended for applicatio where the are normally in standby and are turned on in order to make measurements at intervals greater than 65µs. C (the capacitor connected to ) is slowly charged by the MAX874 during the standby period, and furnishes the reference current during the short measurement period. C s 3.3µF value eures a voltage drop of less than /2LSB when performing four to eight successive conversio. Larger capacitors reduce the error still further. Use ceramic or tantalum capacitors for C. Initial Power-Up When power is first applied, perform a conversion to initialize the. Disregard the output data. Bypassing Use a 4.7µF electrolytic in parallel with a.µf ceramic capacitor to bypass DD to GND. Minimize capacitor lead lengths. Bypass the reference inputs with.µf capacitors, as shown in Figures 7a, 7b, and 7c. Analog Inputs Figure 8 shows the equivalent circuit of the MAX4/ input. When a conversion starts and WR is low, IN_ is connected to sixteen.6pf capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 22pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 32pF input capacitance allows source resistance as high as 8Ω without setup problems. For larger resistances, the acquisition time (tacq) must be increased. Internal protection diodes, which clamp the analog input to and GND, allow the channel input pi to swing from GND -.3 to +.3 without damage. However, for accurate conversio near full scale, the inputs must not exceed by more than 5m or be lower than GND by 5m. If the analog input exceeds 5m beyond the supplies, limit the input current to no more than 2mA, as excessive current will degrade the conversion accuracy of the on channel. Track/Hold The track/hold enters hold mode when a conversion starts (RD low or WR low). INT goes low at the end of the conversion, at which point the track/hold enters track mode. The next conversion can start after the minimum acquisition time, tacq. IN2 R IN MUX... MAX4 R ON T/H IN_ R IN IN 22pF 2k pf MAX4 Figure 8. Equivalent Input Circuit Figure 9. RC Network Equivalent Input Model

11 Trafer Function Figure shows the s nominal trafer function. Code traitio occur halfway between successive-integer LSB values. Output coding is binary with LSB = ( - ) / 256. Conversion Rate The maximum sampling rate (f MAX) for the MAX4/ is achieved in write-read mode (t RD < tintl), and is calculated as follows: f MAX = t WR + t RD + t RI + f MAX = f MAX =.23MHz where t WR = the write pulse width, trd = the delay between write and read pulses, t RI = RD to INT delay, and = minimum acquisition time. Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency s RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC s resolution: SNR = (6.2N +.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 5dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 95.8kHz sinusoid at a MHz rate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution (or effective number of bits ) the ADC provides can be measured by traposing the equation that converts resolution to SNR: N = (SINAD -.76) / 6.2 (see Typical Operating Characteristics). Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency OUTPUT CODE 2 3 Figure. Trafer Function band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: THD = 2log FULL-SCALE TRANSITION INPUT OLTAGE (LSBs) LSB = FS FS - LSB N where is the fundamental RMS amplitude, and 2 through N are the amplitudes of the 2nd through Nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC s noise floor. See the Signal-to- Noise Ratio graph in Typical Operating Characteristics.

12 Ordering Information (continued) PART CPI CAI C/D EPI EAI MJI TEMP. RANGE C to +7 C C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C -55 C to +25 C PIN-PACKAGE 28 Wide Plastic DIP 28 SSOP Dice* 28 Wide Plastic DIP 28 SSOP 28 Wide CERDIP** *Dice are specified at T A = +25 C, DC parameters only. **Contact factory for availability. Chip Information TRANSISTOR COUNT: 2 Pin Configuratio TOP IEW IN4 IN3 IN2 IN MODE D D D2 D3 RD INT GND MAX PWRDN A A D7 D6 D5 D4 WR/RDY IN6 IN5 2 IN4 3 IN3 4 IN2 5 IN 6 MODE 7 D 8 D 9 D2 D3 RD 2 INT IN7 PWRDN A A A2 D7 D6 D5 D4 WR/RDY DIP/SSOP GND 4 5 DIP/SSOP Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 2 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA 9486 (48) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

13 Mouser Electronics Authorized Distributor Click to iew Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX4CAG+ MAX4EAG+ CAI+ MAX4CAG+T MAX4CNG+ MAX4EAG+T MAX4ENG+ CAI+T CPI+ EAI+ EAI+T EPI+

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