Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface

Transcription

1 ; ev 1; 12/97 Low-Power, Dual, 12-Bit oltage-output DACs General Description The / low-power, serial, voltage-output, dual 12-bit digital-to-analog converters (DACs) coume only 5µA from a single +5 () or +3 () supply. These devices feature ail-to- ail output swing and are available in a space-saving 16-pin QSOP package. To maximize the dynamic range, the DAC output amplifiers are configured with an internal gain of +2/. The 3-wire serial interface is SPI /QSPI and Microwire compatible. Each DAC has a doublebuffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include programmable shutdown (2µA), hardware-shutdown lockout (PDL), a separate reference voltage input for each DAC that accepts AC and DC signals, and an active-low clear input (CL) that resets all registers and DACs to zero. These devices provide a programmable logic pin for added functionality, and a serial-data output pin for daisy chaining. Applicatio Industrial Process Control emote Industrial Controls Digital Offset and Gain Microprocessor- Adjustment Controlled Systems Motion Control Automatic Test Equipment (ATE) Features 12-Bit Dual DAC with Internal Gain of +2/ ail-to-ail Output Swing 12µs Settling Time Single-Supply Operation: +5 () +3 () Low Quiescent Current: 5µA (normal operation) 2µA (shutdown mode) SPI/QSPI and Microwire Compatible Available in Space-Saving 16-Pin QSOP Package Power-On eset Clears egisters and DACs to Zero Adjustable Output Offset Ordering Information Functional Diagram PAT ACPE BCPE ACEE BCEE TEMP. ANGE C to +7 C C to +7 C C to +7 C C to +7 C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP Ordering Information continued at end of data sheet. Pin Configuration appears at end of data sheet. INL (LSB) /2 /2 / DOUT CL PDL DGND DD EFA OSA DECODE CONTOL 16-BIT SHIFT EGISTE S CONTOL LOGIC OUTPUT INPUT EG A INPUT EG B DAC EG A DAC EG B DAC A DAC B OUTA OSB OUTB UPO EFB ail-to-ail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. Maxim Integrated Products 1 For free samples & the latest literature: or phone For small orders, phone ext

2 / ABSOLUTE MAXIMUM ATINGS DD to to +6 DD to DGND to +6 to DGND...±.3 OSA, OSB to...( - 4) to ( DD +.3) EF_, to to ( DD +.3) Digital Inputs (,,, CL, PDL) to DGND...(-.3 to +6) Digital Outputs (DOUT, UPO) to DGND to ( DD +.3) Maximum Current into Any Pin...±2mA Stresses beyond those listed under Absolute Maximum atings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTICAL CHAACTEISTI Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate 1.5mW/ C above +7 C)...842mW QSOP (derate 8.3mW/ C above +7 C)...667mW CEDIP (derate 1.mW/ C above +7 C)...8mW Operating Temperature anges MAX515 C_ E... C to +7 C MAX515 E_ E...-4C to +85 C MAX515 MJE C to +125 C Storage Temperature ange C to +15 C Lead Temperature (soldering, 1sec)...+3 C ( DD = +5 %, EFA = EFB = 2.48, L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C (OS_ tied to for a gain of +2/).) esolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error PAAMETE STATIC PEFOMANCE Gain-Error Tempco SYMBOL INL DNL os TCos (Note 1) Guaranteed monotonic Code = 6 Normalized to 2.48 Normalized to 2.48 CONDITIONS A B MIN TYP MAX /2 ±6 -.2 ±3 UNITS Bits LSB LSB m ppm/ C LSB ppm/ C DD Power-Supply ejection atio PS 4.5 DD µ/ EFEENCE INPUT eference Input ange EF DD eference Input esistance EF Minimum with code 1554 hex 14 2 kω MULTIPLYING-MODE PEFOMANCE eference 3dB Bandwidth Input code = 1FFE hex, EF_ =.67p-p at 2.5 DC 3 khz eference Feedthrough Input code = hex, EF_ = ( DD - 1.4p-p) at 1kHz -82 db Signal-to-Noise plus Distortion atio SINAD Input code = 1FFE hex, EF_ = 1p-p at 1.25 DC, f = 25kHz 75 db DIGITAL INPUTS Input High oltage Input Low oltage Input Hysteresis Input Leakage Current Input Capacitance IH IL HYS I IN C IN CL, PDL,,, CL, PDL,,, IN = to DD.1 µa m pf 2

3 ELECTICAL CHAACTEISTI (continued) ( DD = +5 %, EFA = EFB = 2.48, L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C (OS_ tied to for a gain of +2/).) PAAMETE SYMBOL DIGITAL OUTPUTS (DOUT, UPO) Output High oltage OH Output Low oltage OL DYNAMIC PEFOMANCE oltage Output Slew ate S Output Settling Time Output oltage Swing OSA or OSB Input esistance Time equired to Exit Shutdown Digital Feedthrough Digital Crosstalk POWE SUPPLIES Positive Supply oltage Power-Supply Current Power-Supply Current in Shutdown eference Current in Shutdown TIMING CHAACTEISTI Clock Period Pulse Width High Pulse Width Low Fall to ise Setup Time ise to ise Hold Time SDI Setup Time SDI Hold Time ise to DOUT alid Propagation Delay Fall to DOUT alid Propagation Delay ise to Fall Delay ise to ise Hold Pulse Width High OS_ DD I DD I DD(SHDN) t CP t CH t CL t S t H t DS t DH t DO1 t DO2 t t 1 t W I SOUCE = 2mA I SINK = 2mA To 1/2LSB of full-scale, STEP = 4 ail-to-rail (Note 2) = DD, f = 1kHz, = 5p-p (Note 3) (Note 3) (Note 4) C LOAD = 2pF C LOAD = 2pF CONDITIONS MIN TYP MAX DD to DD UNITS /µs µs kω µs n-s n-s ma µa µa / Note 1: Accuracy is specified from code 6 to code 495. Note 2: Accuracy is better than 1LSB for OUT _ greater than 6m and less than DD - 5m. Guaranteed by PS test at the end points. Note 3: Digital inputs are set to either DD or DGND, code = hex, L =. Note 4: minimum clock period includes the rise and fall times. 3

4 / ELECTICAL CHAACTEISTI ( DD = +2.7 to +3.6, EFA = EFB = 1.25, L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C (OS_ pi tied to for a gain of +2/).) esolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error PAAMETE STATIC PEFOMANCE Gain-Error Tempco DD Power-Supply ejection atio EFEENCE INPUT (EF) eference Input ange eference Input esistance eference 3dB Bandwidth SYMBOL INL DNL os TCos PS EF EF MULTIPLYING-MODE PEFOMANCE (Note 5) Guaranteed monotonic Code = 1 Normalized to 1.25 Normalized to DD 3.6 CONDITIONS Minimum with code 1554 hex A B Input code = 1FFE hex, EF_ =.67p-p at.75 DC MIN TYP MAX ±2 ±6 -.2 ± DD UNITS Bits LSB LSB m ppm/ C LSB ppm/ C µ/ kω khz eference Feedthrough Input code = hex, EF_ = ( DD - 1.4)p-p at 1kHz -82 db Signal-to-Noise plus Distortion atio DIGITAL INPUTS Input High oltage Input Low oltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS (DOUT, UPO) Output High oltage Output Low oltage DYNAMIC PEFOMANCE oltage Output Slew ate Output Settling Time Output oltage Swing OSA or OSB Input esistance Time equired for alid Operation after Shutdown Digital Feedthrough Digital Crosstalk SINAD IH IL HYS IIN C IN OH OL S OS_ Input code = 1FFE hex, EF_ = 1p-p at 1 DC, f = 15kHz CL, PDL,,, CL, PDL,,, IN = to DD µa I SOUCE = 2mA I SINK = 2mA ail-to-rail (Note 6) = DD, f = 1kHz, = 3p-p 2.2 DD to DD To 1/2LSB of full-scale, STEP = µs db m pf /µs kω µs n-s n-s 4

5 ELECTICAL CHAACTEISTI (continued) ( DD = +2.7 to +3.6, EFA = EFB = 1.25, L = 1kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C (OS_ pi tied to for a gain of +2/).) PAAMETE POWE SUPPLIES Positive Supply oltage Power-Supply Current Power-Supply Current in Shutdown eference Current in Shutdown TIMING CHAACTEISTI Clock Period Pulse Width High Pulse Width Low Fall to ise Setup Time ise to ise Hold Time SDI Setup Time SDI Hold Time ise to DOUT alid Propagation Delay SYMBOL DD I DD I DD (SHDN) t CP t CH t CL t S t H t DS t DH t DO1 (Note 7) CONDITIONS MIN TYP MAX.45.6 UNITS (Note 7) 1 8 µa (Note 4) C LOAD = 2pF ma µa / Fall to DOUT alid Propagation Delay t DO2 C LOAD = 2pF 12 ise to Fall Delay t 1 ise to ise Hold t 1 4 Pulse Width High t W 1 Note 5: Accuracy is specified from code 1 to code 495. Note 6: Accuracy is better than 1LSB for OUT greater than 6m and less than DD - 8m. Guaranteed by PS test at the end points. Note 7: Digital inputs are set to either DD or DGND, code = hex, L =. 5

6 / Typical Operating Characteristics ( DD = +5, L = 1kΩ, C L = 1pF, OS_ pi tied to, T A = +25 C, unless otherwise noted.) ELATIE OUTPUT (db) EFEENCE OLTAGE INPUT FEQUENCY ESPONSE EF 2.5 DC FEQUENCY (khz) /5155toc1 SUPPLY CUENT (µa) SUPPLY CUENT vs. TEMPEATUE TEMPEATUE ( C) CODE = (HEX) EF = 2.48 L = /5155 toc2 THD + NOISE (db) TOTAL HAMONIC DISTOTION PLUS NOISE vs. FEQUENCY EF = 2.5 DC FEQUENCY (khz) /5155 toc3 FULL-SCALE EO (LSB) FULL-SCALE EO vs. ESISTIE LOAD EF = 2.48 /5155 toc4 ELATIE OUTPUT (db) EFEENCE FEEDTHOUGH AT 1kHz EF = 1.88 DC CODE = (HEX) /5155 toc5 SHUTDOWN CUENT (µa) EF = 1 SHUTDOWN CUENT vs. TEMPEATUE /5155 toc L (kω) FEQUENCY (khz) TEMPEATUE ( C) ELATIE OUTPUT (db) OUTPUT FFT PLOT EF = DC f = 1kHz NOTE: ELATIE TO FULL-SCALE /5155 toc7 DYNAMIC ESPONSE ISE TIME /5155 toc8 5/div 1/div DYNAMIC ESPONSE FALL TIME /5155 toc9 5/div 1/div FEQUENCY (khz) EF = µs/div EF = µs/div 6

7 Typical Operating Characteristics (continued) ( DD = +3, L = 1kΩ, C L = 1pF, OS_pi tied to, T A = +25 C, unless otherwise noted.) ELATIE OUTPUT (db) EFEENCE OLTAGE INPUT FEQUENCY ESPONSE EF DC CODE = 1FFE FEQUENCY (khz) /5155 toc1 SUPPLY CUENT (µa) SUPPLY CUENT vs. TEMPEATUE EF = 1 L = TEMPEATUE ( C) CODE = (HEX) /5155 toc11 THD + NOISE (db) TOTAL HAMONIC DISTOTION PLUS NOISE vs. FEQUENCY EF = 1 DC FEQUENCY (khz) /5155 toc12 / FULL-SCALE EO (LSB) FULL-SCALE EO vs. ESISTIE LOAD EF = L (kω) /5155 toc13 ELATIE OUTPUT (db) EFEENCE FEEDTHOUGH AT 1kHz EF = DC CODE = (HEX) FEQUENCY (khz) /5155 toc14 SHUTDOWN CUENT (µa) EF = 1 L = SHUTDOWN CUENT vs. TEMPEATUE TEMPEATUE ( C) /5155 toc15 ELATIE OUTPUT (db) OUTPUT FFT PLOT EF = DC f = 1kHz /5155toc16 DYNAMIC ESPONSE ISE TIME /5155 toc17 2/div 5m/div DYNAMIC ESPONSE FALL TIME /5155 toc18 2/div 5m/div FEQUENCY (khz) EF = µs/div EF = µs/div 7

8 / Typical Operating Characteristics (continued) ( DD = +5 (), DD = +3 (), L = 1kΩ, C L = 1pF, OS_ pi tied to, unless otherwise noted.) SUPPLY CUENT (ma) SUPPLY CUENT vs. SUPPLY OLTAGE CODE = OOOO (HEX) SUPPLY OLTAGE () /5155toc19 / SUPPLY CUENT (ma) SUPPLY CUENT vs. SUPPLY OLTAGE CODE = OOOO (HEX) SUPPLY OLTAGE () /5155toc2 MAJO-CAY TANSITION /5155 toc21 2/div 5m/div AC COUPLED ANALOG COSSTALK 5µs/div TANSITION FOM 1 (HEX) TO FFE (HEX) DIGITAL FEEDTHOUGH /5155 toc22 OUTA 5/div /5155 toc23 5/div OUTB 2µ/div AC COUPLED OUTA 5µ/div AC COUPLED 25µs/div EF = 2.48, GAIN = +2/, CODE = 1FFE HEX 2.5µs/div 8

9 Pin Description PIN NAME OUTA OSA EFA CL DGND DOUT UPO PDL EFB Analog Ground eference for DAC A Active-Low Clear Input. esets all registers to zero. DAC outputs go to. Chip-Select Input Serial-Data Input Serial Clock Input Digital Ground Serial-Data Output FUNCTION DAC A Output oltage DAC A Offset Adjustment User-Programmable Output Power-Down Lockout. The device cannot be powered down when PDL is low. eference for DAC B 14 OSB DAC B Offset Adjustment 15 OUTB DAC B Output oltage 16 DD Positive Power Supply Detailed Description The / dual, 12-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition, trimmed internal resistors produce an internal gain of +2/ that maximizes output voltage swing. The amplifier s offset-adjust pin allows for a DC shift in the DAC s output. Both DACs use an inverted -2 ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent full-scale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs. eference Inputs The reference inputs accept both AC and DC values with a voltage range extending from to ( DD - 1.4). Determine the output voltage using the following equation (OS_ = ): EF_ SHOWN FO ALL 1s ON DAC D D9 D1 D11 Figure 1. Simplified DAC Circuit Diagram OUT = ( EF x NB / 496) x 2 where NB is the numeric value of the DAC s binary input code ( to 495) and EF is the reference voltage. The reference input impedance ranges from 14kΩ (1554 hex) to several giga ohms (with an input code of hex). The reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 5pF with a full-scale input code. Output Amplifier The output amplifiers on the / have internal resistors that provide for a gain of +2/ when OS_ is connected to. These resistors are trimmed to minimize gain error. The output amplifiers have a typical slew rate of.75/µs and settle to 1/2LSB within 15µs, with a load of 1kΩ in parallel with 1pF. Loads less than 2kΩ degrade performance. The OS_ pin can be used to produce an adjustable offset voltage at the output. For itance, to achieve a 1 offset, apply -1 to the OS_ pin to produce an output range from 1 to (1 + EF x 2). Note that the DAC s output range is still limited by the maximum output voltage specification. Power-Down Mode The / feature a software-programmable shutdown mode that reduces the typical supply current to 2µA. The two DACs can be shutdown independently, or simultaneously using the appropriate programming command. Enter shutdown mode by writing the appropriate input-control word (Table 1). In shutdown mode, the reference inputs and amplifier outputs become high impedance, and the serial interface remai active. Data in the input registers is OS_ / 9

10 / Table 1. Serial-Interface Programming Commands A C1 C 16-BIT SEIAL WOD D11...D (MSB) (LSB) FUNCTION 1 12-bit DAC data Load input register A; DAC registers are unchanged bit DAC data Load input register B; DAC registers are unchanged bit DAC data Load input register A; all DAC registers are updated bit DAC data Load input register B; all DAC registers are updated bit DAC data 1 xxxxxxxxxxxx 1 x xxxxxxxx 1 1 x xxxxxxxx Load all DAC registers from the shift register (start up both DACs with new data.). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers) xxxxxxxxxxxx Shut down both DACs (provided PDL = 1). Update DAC register A from input register A (start up DAC A with data previously stored in input register A). Update DAC register B from input register B (start up DAC B with data previously stored in input register B). 1 1 x xxxxxxxx Shut down DAC A (provided PDL = 1). S x xxxxxxxx Shut down DAC B (provided PDL = 1). 1 x xxxxxxxx UPO goes low (default). 1 1 x xxxxxxxx UPO goes high. 1 1 xxxxxxxx Mode 1, DOUT clocked out on s rising edge. 1 xxxxxxxx Mode, DOUT clocked out on s falling edge (default). x xxxxxxxx No operation (NOP). x = Don t care Note: D11, D1, D9, and D8 become control bits when A, C1, and C =. S is a sub bit, always zero. Figure 2. Connectio for Microwire SK SO I/O MICOWIE POT saved, allowing the / to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting shutdown), wait 2µs for output stabilization. Serial Interface The / 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word coists of an address bit, two control bits, 12 bits of data (MSB to LSB), and one sub bit as shown in Figure 4. The address and control bits determine the / s respoe, as outlined in Table 1. 1

11 Figure 3. Connectio for SPI/QSPI MOSI SCK I/O +5 SS SPI/QSPI POT CPOL =, CPHA = MSB...LSB Address Bits A 1 Address/2 Control Bits Figure 4. Serial-Data Format 16 Bits of Serial Data Control Bits C1, C MSB...DataBits...LSB D11...D 12 Data Bits SUB BIT S The / s digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, Microwire), with low during this period. The address and control bits determine which register will be updated, and the state of the registers when exiting shutdown. The 3-bit address/control determines the following: registers to be updated clock edge on which data is to be clocked out via the serial-data output (DOUT) state of the user-programmable logic output configuration of the device after shutdown. The general timing diagram of Figure 5 illustrates how data is acquired. Driving low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With low, data at is clocked into the register on the rising edge of. As goes high, data is latched into the input and/or DAC registers depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 1MHz. Figure 6 depicts a more detailed timing diagram of the serial interface. / COMMAND EXECUTED A C1 C D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D S Figure 5. Serial-Interface Timing Diagram 11

12 / t O t S t CL t CH t CP t DS tdh Figure 6. Detailed Serial-Interface Timing Diagram t H t 1 t W DOUT DOUT DOUT TO OTHE SEIAL DEICES Figure 7. Daisy Chaining /s TO OTHE SEIAL DEICES Figure 8. Multiple /s Sharing a Common Line 12

13 Serial-Data Output The serial-data output, DOUT, is the internal shift register s output. DOUT allows for daisy chaining of devices and data readback. The / can be programmed to shift data out of DOUT on s falling edge (Mode ) or on the rising edge (Mode 1). Mode provides a lag of 16 clock cycles, which maintai compatibility with SPI/QSPI and Microwire interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode. User-Programmable Logic Output (UPO) UPO allows an external device to be controlled through the serial interface (Table 1), thereby reducing the number of microcontroller I/O pi required. On powerup, UPO is low. Power-Down Lockout Input (PDL) The power-down lockout pin (PDL) disables software shutdown when low. When in shutdown, traitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to asynchronously wake up the device. Daisy Chaining Devices Any number of /s can be daisy chained by connecting the DOUT pin of one device to the pin of the following device in the chain (Figure 7). Since the / s DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. efer to the digital output OH and OL specificatio in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several /s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input () is required for each IC. Applicatio Information Unipolar Output Figure 9 shows the / configured for unipolar, rail-to-rail operation with a gain of +2/. The can produce a to 4.96 output with 2.48 reference (Figure 9), while the can produce a range of to 2.5 with a 1.25 reference. Table 2 lists the unipolar output codes. An offset to the output can be achieved by connecting a voltage to OS_, as shown in Figure 1. By applying OS _ = -1, the output values will range between 1 and (1 + EF x 2). EF_ GAIN = +2/ DAC_ +5/+3 DGND Table 2. Unipolar Code Table (Gain = +2) DD Figure 9. Unipolar Output Circuit (ail-to-ail) EF_ DAC _ DAC CONTENTS MSB LSB () 1 1 () 1 () () 1 () +5/+3 DD Figure 1. Setting OS_ for Output Offset DGND OS_ OS_ OS ANALOG OUTPUT x 2 EF x 2 EF x 2 = EF 496 EF x 2 EF x 2 EF 496 () Note: ( ) are for the sub bit. / 13

14 / Table 3. Bipolar Code Table DAC CONTENTS MSB LSB () 1 1 () ANALOG OUTPUT 1 () () 1 () () EF EF EF EF EF = - EF / +3 AC 26k EFEENCE INPUT 5mp-p 1k +5/+3 DAC_ MAX495 EF Figure 12. AC eference Input Circuit DD DGND OS_ Note: ( ) are for the sub bit. + EF_ DAC _ +5/+3 DD DGND OS_ 1k 1k + 1k 1k - OUT µp EF_ DAC _ +5/+3 DD DGND OS_ PHOTODIODE + OUT - PULLDOWN Figure 11. Bipolar Output Circuit Bipolar Output The / can be configured for a bipolar output, as shown in Figure 11. The output voltage is given by the equation (OS_ = ): OUT = EF [((2 x NB) / 496) - 1] where NB represents the numeric value of the DAC s binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11 s circuit. Figure 13. Digital Calibration Using an AC eference In applicatio where the reference has an AC signal component, the / have multiplying capabilities within the reference input voltage range specificatio. Figure 12 shows a technique for applying a sinusoidal input to EF_, where the AC signal is offset before being applied to the reference input. Harmonic Distortion and Noise The total harmonic distortion plus noise (THD+N) is typically less than -78dB at full scale with a 1p-p input swing at 5kHz. The typical -3dB frequency is 3kHz for both devices, as shown in the Typical Operating Characteristics. Digital Calibration and Threshold Selection Figure 13 shows the / in a digital calibration application. With a bright light value applied to the photodiode (on), the DAC is digitally ramped until 14

15 IN EF EFA EFB SHIFT EGISTE INPUT EG A INPUT EG B DAC EG A DAC EG B DD DACA DACB DGND OSA OUTA OUTB OSB GAIN [ OFFSET] 2NA OUT OUT = [ ] = 4 2NB 4 [( IN )( )( 1+ )] [( EF )( )] NA IS THE NUMEIC ALUE OF THE INPUT CODE FO DACA. NB IS THE NUMEIC ALUE OF THE INPUT CODE FO DACB / Figure 14. Digital Control of Gain and Offset it trips the comparator. The microprocessor (µp) stores this high calibration value. epeat the process with a dim light (off) to obtain the dark current calibration. The µp then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applicatio include tachometers, motion seing, automatic readers, and liquid clarity analysis. Digital Control of Gain and Offset The two DACs can be used to control the offset and gain for curve-fitting nonlinear functio, such as traducer linearization or analog compression/expaion applicatio. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by 1, 2, 3, and 4 (Figure 14). Power-Supply Coideratio On power-up, the input and DAC registers clear (set to zero code). For rated performance, EF_ should be at least 1.4 below DD. Bypass the power supply with a 4.7µF capacitor in parallel with a.1µf capacitor to. Minimize lead lengths to reduce lead inductance. Grounding and Layout Coideratio Digital and AC traient signals on can create noise at the output. Connect to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. 15

16 / Pin Configuration TOP IEW OUTA OSA EFA CL Chip Information TANSISTO COUNT: 353 SUBSTATE CONNECTED TO DIP/QSOP 16 DD 15 OUTB 14 OSB 13 EFB 12 PDL 11 UPO 1 DOUT 9 DGND _Ordering Information (continued) PAT AEPE BEPE AEEE BEEE BMJE ACPE BCPE ACEE BCEE AEPE BEPE AEEE BEEE BMJE TEMP. ANGE -4 C to +85 C -4 C to +85 C -4 C to +85 C -4 C to +85 C -55 C to +125 C C to +7 C C to +7 C C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C -4 C to +85 C -4 C to +85 C -55 C to +125 C *Contact factory for availability. PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CEDIP* 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CEDIP* INL (LSB) /2 /2 ±2 ±2 ±2 ±2 ±2 Package Information QSOP.EPS Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 16 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.