Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS

Transcription

1 DAC7800 DAC780 DAC780 Dual Monolithic CMOS -Bit Multiplying DIGITAL-TO-ANALOG CONVETES FEATUES TWO D/As IN A 0." WIDE PACKAGE SINGLE SUPPLY HIGH SPEED DIGITAL INTEFACE: Serial DAC Bit Parallel DAC780 -Bit Parallel DAC780 MONOTONIC OVE TEMPEATUE LOW COSSTALK: 9dB min FULLY SPECIFIED OVE 0 O C TO 8 O C DESCIPTION The DAC7800, DAC780 and DAC780 are members of a new family of monolithic dual -bit CMOS multiplying digital-to-analog converters. The digital interface speed and the AC multiplying performance are achieved by using an advanced CMOS process optimized for data conversion circuits. High stability on-chip resistors provide true -bit integral and differential linearity over the wide industrial temperature range of 0 o C to 8 o C. DAC7800 features a serial interface capable of clocking-in data at a rate of at least 0MHz. Serial data is clocked (edge triggered) MSB first into a -bit shift register and then latched into each D/A separately or simultaneously as required by the application. An asynchronous CLEA control is provided for poweron reset or system calibration functions. It is packaged in a -pin 0." wide plastic DIP. DAC780 has a -byte (8 ) double-buffered interface. Data is first loaded (level transferred) into the input registers in two steps for each D/A. Then both D/As are updated simultaneously. DAC780 features an asynchronous CLEA control. DAC780 is packaged in a -pin 0." wide plastic DIP. APPLICATIONS POCESS CONTOL OUTPUTS ATE PIN ELECTONI LEVEL SETTING POGAMMABLE FILTES POGAMMABLE GAIN CICUITS AUTO-CALIBATION CICUITS DAC780 has a single-buffered -bit data word interface. Parallel data is loaded (edge triggered) into the single D/A register for each D/A. DAC780 is packaged in a -pin 0." wide plastic DIP. 8 Serial DAC780 -Bit Interface DAC780 8-Bit Interface 8 Bits Bits CL W UPD A0 DAC7800 Serial Interface CLK W A UPD A UPD B CL B VEF A -Bit MDAC VEF B -Bit MDAC FB A FB B International Airport Industrial Park Mailing Address: PO Box 00 Tucson, AZ 87 Street Address: 70 S. Tucson Blvd. Tucson, AZ 870 Tel: (0) 7- Twx: Cable: BBCOP Telex: 0-9 FAX: (0) Immediate Product Info: (800) 8- DAC7800/0/0 990 Burr-Brown Corporation PDS-079E Printed in U.S.A. August, 99

2 SPECIFICATIONS ELECTICAL At = DC, V EF A = V EF B =, T A = 0 C to 8 C unless otherwise noted. DAC7800/780/780K DAC7800/780/780L PAAMETE CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ACCUACY esolution * Bits elative Accuracy ± ±/ LSB Differential Nonlinearity ± * LSB Gain Error Measured Using FB A and FB B. ± ± LSB All egisters Loaded with All s. Gain Temperature Coefficient () * * ppm/ C Output Leakage Current T A = C * * na T A = 0 C to 8 C 0 * * na EFEENCE INPUT Input esistance 0 * * * kω Input esistance Match 0. * % DIGITAL INPUTS V IH (Input High Voltage) * V V IL (Input Low Voltage) 0.8 * V I IN (Input Current) T A = C ± * µa T A = 0 C to 8 C ±0 * µa C IN (Input Capacitance) * * pf POWE SUPPLY.. * * V I DD 0. * * ma Power Supply ejection from. to * %/% * Same specification as for DAC7800/780/780K. AC PEFOMANCE OUTPUT OP AMP IS OPA0. At = DC, V EF A = V EF B =, T A = C unless otherwise noted. These specifications are fully characterized but not subject to test. DAC7800/780/780K DAC7800/780/780L PAAMETE CONDITIONS MIN TYP MAX MIN TYP MAX UNITS OUTPUT CUENT SETTLING TIME To 0.0% of Full Scale * * µs L = 00Ω, C L = pf DIGITAL-TO-ANALOG GLITCH IMPULSE V EF A = V EF B = 0.9 * nv-s L = 00Ω, C L = pf AC FEEDTHOUGH f VEF = 0kHz 7 7 * * db OUTPUT CAPACITANCE DAC Loaded with All 0s 0 0 * * pf DAC Loaded with All s * * pf CHANNEL-TO-CHANNEL ISOLATION V EF A to f VEF A = 0kHz 90 9 * * db V EF B =, Both DACs Loaded with s V EF B to f VEF B = 0kHz 90 0 * * db V EF A =, Both DACs Loaded with s DIGITAL COSSTALK Full Scale Transition 0.9 * nv-s L = 00Ω, C L = pf NOTE: () Guaranteed but not tested. The information provided herein is believed to be reliable; however, BU-BOWN assumes no responsibility for inaccuracies or omissions. BU-BOWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BU-BOWN does not authorize or warrant any BU-BOWN product for use in life support devices and/or systems. DAC7800/0/0

3 ABSOLUTE MAXIMUM ATINGS At T A = C unless otherwise noted. to AGND..., 7V to..., 7V AGND to... 0., Digital Input to... 0., 0. V EF A, V EF B to AGND... ± V EF A, V EF B to... ±, to AGND... 0., Storage Temperature ange... C to C Operating Temperature ange... 0 C to 8 C Lead Temperature (soldering, 0s) C Junction Temperature... 7 C ELECTOSTATIC DISCHAGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. Digital Inputs: All digital inputs of the DAC780X family incorporate on-chip ESD protection circuitry. This protection is designed and has been tested to withstand five 0 PACKAGE INFOMATION PACKAGE DAWING MODEL PACKAGE NUMBE () DAC7800KP -Pin PDIP 80 DAC7800LP -Pin PDIP 80 DAC7800KU -Pin SOIC DAC7800LU -Pin SOIC DAC780KP -Pin DIP DAC780LP -Pin DIP DAC780KU -Pin SOIC 9 DAC780LU -Pin SOIC 9 DAC780KP -Pin DIP DAC780LP -Pin DIP DAC780KU -Pin SOIC 9 DAC780LU -Pin SOIC 9 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. positive and negative discharges (00pF in series with 00Ω) applied to each digital input. Analog Pins: Each analog pin has been tested to Burr- Brown s analog ESD test consisting of five 00 positive and negative discharges (00pF in series with 00Ω) applied to each pin. AGND, I OUT, and FB show some sensitivity. Failure to observe ESD handling procedures could result in catastrophic device failure. ODEING INFOMATION MODEL ELATIVE ACCUACY GAIN EO PACKAGE DAC7800KP ±LSB ±LSB -Pin DIP DAC7800KU () -Lead SO DAC7800LP ±/LSB ±LSB -Pin DIP DAC7800LU -Lead SO DAC780KP ±LSB ±LSB -Pin DIP DAC780KU -Lead SO DAC780LP ±/LSB ±LSB -Pin DIP DAC780LU -Lead SO DAC780KP ±LSB ±LSB -Pin DIP DAC780KU () -Lead SO DAC780LP ±/LSB ±LSB -Pin DIP DAC780LU -Lead SO NOTE: () Available with Tape and eel. Add "-T" to basic model number. DAC7800/0/0

4 DICE INFOMATION DAC7800 DIE TOPOGAPHY DAC780 DIE TOPOGAPHY MECHANICAL INFOMATION DAC7800 MILS (0.00") MILLIMETES Die Size x ±. x.07 ±0. Die Thickness 0 ± 0. ±0.08 Min. Pad Size x 0.0 x 0.0 Metalization Aluminum Substrate Bias: DAC780 MILS (0.00") MILLIMETES Die Size x ±. x.07 ±0. Die Thickness 0 ± 0. ±0.08 Min. Pad Size x 0.0 x 0.0 Metallization Aluminum Substrate Bias: DAC780 DIE TOPOGAPHY DAC780 MILS (0.00") MILLIMETES Die Size x ±. x.07 ±0. Die Thickness 0 ± 0. ±0.08 Min. Pad Size x 0.0 x 0.0 Metalization Aluminum Substrate Bias: DAC7800/0/0

5 DAC7800 BLOCK DIAGAM PIN CONFIGUATION DAC7800 Control Logic and Shift egister Bit 0 Bit Bit Bit egister egister 0 UPD B FB B V EF B VEF A FB A IOUT A FB A VEF A CLK UPD A Data In 7 8 DAC7800 Top View DIP 0 9 IOUT B FB B VEF B VDD CL UPD B UPD A CLK Data In CL LOGIC TUTH TABLE CLK UPD A UPD B CL FUNCTION X X X X 0 All register contents set to 0 s (asynchronous). X X X X No data transfer. X X 0 Input data is clocked into input register (location Bit ) and previous data shifts. X 0 0 Input register bits (LSB) (MSB) are loaded into. X 0 0 Input register bits (LSB) 0 (MSB) are loaded into. X Input register bits (LSB) (MSB) are loaded into, and input register bits (LSB) 0 (MSB) are loaded into. X = Don t care. means falling edge triggered. DATA INPUT FOMAT UPD B DAC7800 Digital Interface Block Diagram UPD A LSB egister MSB LSB egister MSB CLK Data In Bit Bit -Bit Shift egister Bit Bit 0 CLK DAC7800 Data Input Sequence Data In Bit 0 Bit Bit Bit Bit Bit Bit Bit 7 Bit 8 Bit 9 Bit 0 Bit Bit Bit Bit Bit Bit Bit 7 Bit 8 Bit 9 Bit 0 Bit Bit Bit MSB LSB MSB LSB DAC7800/0/0

6 DAC7800 (CONT) TIMING CHAACTEISTI =, V EF A = V EF B =, T A = 0 C to 8 C. PAAMETE t Data Setup Time t Data Hold Time t Chip Select to CLK, Update, Data Setup Time t Chip Select to CLK, Update, Data Hold Time t CLK Pulse Width t Clear Pulse Width t 7 Update Pulse Width t 8 CLK Edge to UPD A or UPD B DAC780 BLOCK DIAGAM MINIMUM ns ns ns 0ns 0ns 0ns 0ns ns CLK DATA UPD A UPD B CL t t t t t 8 t 7 t NOTES: () All input signal rise and fall times are measured from 0% to 90% of. t = t = ns. () Timing measurement reference level is V V F IH IL. PIN CONFIGUATION t 0 IOUT A IOUT B UPD A0 W CL DAC780 Control Logic MS Input eg 8 egister LS Input eg egister 8 IOUT A FB A VEF A VEF B FB B IOUT B FB A VEF A DB0 DB DB DB DB DB DAC780 Top View DIP FB B VEF B VDD UPD W CL A0 DB7 DB MS Input eg LS Input eg DB7DB0 LOGIC TUTH TABLE CL UPD W A0 FUNCTION X X X No Data Transfer X X X No Data Transfer 0 X X X X X All egisters Cleared LS Input egister Loaded with DB7DB0 (LSB) MS Input egister Loaded with DB (MSB)DB LS Input egister Loaded with DB7DB0 (LSB) 0 0 MS Input egister Loaded with DB (MSB)DB0 0 0 X X, egisters Updated Simultaneously from Input egisters X X, egisters are Transparent X = Don t care. DAC7800/0/0

7 DAC780 (CONT) TIMING CHAACTEISTI =, V EF A = V EF B =, T A = 0 C to 8 C. PAAMETE t Address Valid to Write Setup Time t Address Valid to Write Hold Time t Data Setup Time t Data Hold Time t Chip Select or Update to Write Setup Time t Chip Select or Update to Write Hold Time t 7 Write Pulse Width t 8 Clear Pulse Width MINIMUM 0ns 0ns 0ns 0ns 0ns 0ns 0ns 0ns A0, UPD NOTES: () All input signal rise and fall times are measured from 0% to 90% of. t = t F = ns. () Timing measurement reference level is V IH V IL. DATA W CL t t t 7 t t t t t 8 DAC780 BLOCK DIAGAM PIN CONFIGUATION AGND DAC780 CK egister FB A FB B V EF B A B 0 W 9 CK egister IOUT A FB A VEF A VEF B FB B IOUT B AGND V EF A A (LSB) DB0 DB DB DB DB DB DAC780 Top View DIP B W DB (MSB) DB0 DB9 DB8 DB7 DB 8 DBDB0 LOGIC TUTH TABLE A B W FUNCTION X X No Data Transfer X No Data Transfer 0 A ising Edge on A or B Loads Data to the espective DAC 0 egister Loaded from Data Bus 0 egister Loaded from Data Bus 0 0 and egisters Loaded from Data Bus X = Don t care. means rising edge triggered. TIMING CHAACTEISTI At =, and T A = 0 o C to 8 o C. PAAMETE MINIMUM t - Data Setup Time 0ns t - Data Hold Time ns t - Chip Select to Write Setup Time 0ns t - Chip Select to Write Hold Time 0ns t - Write Pulse Width 0ns t t DATA t t A, B t W NOTES: () All input signal rise and fall times are measured from 0% to 90% of. t = t F = ns. () Timing measurement reference level V IH V IL is. 7 DAC7800/0/0

8 TYPICAL PEFOMANCE CUVES OUTPUT OP AMP IS OPA0. T A = C, =. µ OUTPUT LEAKAGE CUENT vs TEMPEATUE 0 THD NOISE vs FEQUENCY Output Leakage Current (A) 00n 0n n 00p 0p THD Noise (db) Vrms Vrms Vrms p Temperature ( C) k 0k 00k Frequency (Hz) Crosstalk (db) CHANNEL-TO-CHANNEL ISOLATION vs FEQUENCY k 0k 00k M 0M Feedthrough (db) FEEDTHOUGH vs FEQUENCY k 0k 00k M 0M Frequency (Hz) Frequency (Hz) 0 FEQUENCY ESPONSE 70 PS vs FEQUENCY 0 C F = 0pF C F = pf 0 Gain (db) C F = PS (db) DAC Loaded w/0s DAC Loaded w/s 0 k 0k 00k M 0M Frequency (Hz) 0 k 0k 00k M Frequency (Hz) DAC7800/0/0 8

9 DISCUSSION OF SPECIFICATIONS ELATIVE ACCUACY This term, also known as end point linearity or integral linearity, describes the transfer function of analog output to digital input code. elative accuracy describes the deviation from a straight line, after zero and full scale errors have been adjusted to zero. DIFFEENTIAL NONLINEAITY Differential nonlinearity is the deviation from an ideal LSB change in the output when the input code changes by LSB. A differential nonlinearity specification of LSB maximum guarantees monotonicity. GAIN EO Gain error is the difference between the full-scale DAC output and the ideal value. The ideal full scale output value for the DAC780X is (09/09)V EF. Gain error may be adjusted to zero using external trims as shown in Figures and 7. OUTPUT LEAKAGE CUENT The current which appears at and with the DAC loaded with all zeros. OUTPUT CAPACITANCE The parasitic capacitance measured from or to AGND. CHANNEL-TO-CHANNEL ISOLATION The AC output error due to capacitive coupling from to or to. MULTIPLYING FEEDTHOUGH EO The AC output error due to capacitive coupling from V EF to I OUT with the DAC loaded with all zeros. OUTPUT CUENT SETTLING TIME The time required for the output current to settle to within 0.0% of final value for a full scale step. DIGITAL-TO-ANALOG GLITCH ENEGY The integrated area of the glitch pulse measured in nanovoltseconds. The key contributor to digital-to-analog glitch is charge injected by digital logic switching transients. DIGITAL COSSTALK Glitch impulse measured at the output of one DAC but caused by a full scale transition on the other DAC. The integrated area of the glitch pulse is measured in nanovoltseconds. CICUIT DESCIPTION Figure shows a simplified schematic of one half of a DAC780X. The current from the V EF A pin is switched between and AGND by single-pole double-throw CMOS switches. This maintains a constant current in each leg of the ladder regardless of the input code. The input resistance at V EF is therefore constant and can be driven by either a voltage or current, AC or DC, positive or negative polarity, and have a voltage range up to ±. V EF A DB (MSB) DB0 DB9 DB0 (LSB) FIGUE. Simplified Circuit Diagram for. FB A AGND A CMOS switch transistor, included in series with the ladder terminating resistor and in series with the feedback resistor, FB A, compensates for the temperature drift of the ON resistance of the ladder switches. Figure shows an equivalent circuit for. C OUT is the output capacitance due to the N-channel switches and varies from about 0pF to 70pF with digital input code. The current source I LKG is the combination of surface and junction leakages to the substrate. I LKG approximately doubles every 0 C. O is the equivalent output resistance of the D/A and it varies with input code. V EF A D IN 09 x V EF FIGUE. Equivalent Circuit for. INSTALLATION O I LKG COUT FB A ESD POTECTION All digital inputs of the DAC780X incorporate on-chip ESD protection circuitry. This protection is designed to withstand.kv (using the Human Body Model, 00pF and 00Ω). However, industry standard ESD protection methods should be used when handling or storing these components. When not in use, devices should be stored in conductive foam or rails. The foam or rails should be discharged to the destination socket potential before devices are removed. POWE SUPPLY CONNECTIONS The DAC780X are designed to operate on = 0%. For optimum performance and noise rejection, power supply decoupling capacitors C D should be added as shown in the application circuits. These capacitors (µf tantalum recommended) should be located close to the D/A. AGND and 9 DAC7800/0/0

10 should be connected together at one point only, preferably at the power supply ground point. Separate returns minimize current flow in low-level signal paths if properly connected. Output op amp analog common ( input) should be connected as near to the AGND pins of the DAC780X as possible. WIING PECAUTIONS To minimize AC feedthrough when designing a PC board, care should be taken to minimize capacitive coupling between the V EF lines and the I OUT lines. Similarly, capacitive coupling between DACs may compromise the channel-tochannel isolation. Coupling from any of the digital control or data lines might degrade the glitch and digital crosstalk performance. Solder the DAC780X directly into the PC board without a socket. Sockets add parasitic capacitance (which can degrade AC performance). AMPLIFIE OFFSET VOLTAGE The output amplifier used with the DAC780X should have low input offset voltage to preserve the transfer function linearity. The voltage output of the amplifier has an error component which is the offset voltage of the op amp multiplied by the noise gain of the circuit. This noise gain is equal to ( F / O ) where O is the output impedance of the D/A I OUT terminal and F is the feedback network impedance. The nonlinearity occurs due to the output impedance varying with code. If the 0 code case is excluded (where O = infinity), the O will vary from to providing a noise gain variation between / and. In addition, the variation of O is nonlinear with code, and the largest steps in O occur at major code transitions where the worst differential nonlinearity is also likely to be experienced. The nonlinearity seen at the amplifier output is V OS V OS / = V OS /. Thus, to maintain good nonlinearity the op amp offset should be much less than /LSB. UNIPOLA CONFIGUATION Figure shows DAC780X in a typical unipolar (two-quadrant) multiplying configuration. The analog output values versus digital input code are listed in Table II. The operational amplifiers used in this circuit can be single amplifiers such as the OPA0, or a dual amplifier such as the OP07. C and C provide phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. If an application requires the D/A to have zero gain error, the circuit shown in Figure may be used. esistors and induce a positive gain error greater than worst-case initial negative gain error. Trim resistors and provide a variable negative gain error and have sufficient trim range to correct for the worst-case initial positive gain error plus the error produced by and. BIPOLA CONFIGUATION Figure shows the DAC780X in a typical bipolar (fourquadrant) multiplying configuration. The analog output values versus digital input code are listed in Table III. DATA INPUT ANALOG OUTPUT MSB LSB V EF (09/09) V EF (08/09) = /V EF V EF (/09) Volts TABLE II. Unipolar Output Code. C D µf V EF A DAC780X V EF B FB A FB B FIGUE. Unipolar Configuration. C D µf DAC780X V IN A 00 Ω V EF A V EF B 00 Ω V IN B C C A V OUT A V OUT B, A OPA0 or / OP07. DAC780 has a single analog common, AGND. FB A The operational amplifiers used in this circuit can be single amplifiers such as the OPA0, a dual amplifier such as the OP07, or a quad amplifier like the OPA0. C and C provide phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. The bipolar offset resistors 7 and 80 should be ratio-matched to 0.0% to ensure the specified gain error performance. 7Ω FB B 7Ω C C A V OUT A V OUT B, A OPA0 or / OP07. DAC780 has a single analog common, AGND. FIGUE. Unipolar Configuration with Gain Trim. DAC7800/0/0 0

11 If an application requires the D/A to have zero gain error, the circuit shown in Figure may be used. esistors and induce a positive gain error greater than worst-case initial negative gain error. Trim resistors and provide a variable negative gain error and have sufficient trim range to correct for the worst-case initial positive gain error plus the error produced by and. DATA INPUT ANALOG OUTPUT MSB LSB V EF (07/08) V EF (/08) Volts 0 V EF (/08) V EF (08/08) TABLE III. Bipolar Output Code. V EF A Ω 0k C D µf Ω 0k 0kΩ A V OUT A FB A DAC780X C DAC780 has a single analog common, AGND. A, OPA0 or / OP07. FB B V EF B Ω 0k C A 0k Ω Ω 0k A V OUT B FIGUE. Bipolar Configuration. APPLICATIONS -BIT PLUS SIGN DA For a bipolar DAC with bits of resolution, two solutions are possible. As shown in Figure 7, the addition of a precision difference amplifier and a high speed JFET switch provides a -bit plus sign voltage-output DAC. When the switch selects the op amp output, the difference amplifier serves as a non-inverting output buffer. If the analog ground side of the switch is selected, the output of the difference amplifier is inverted. Another option, shown in Figure 8, also produces a -bit plus sign output without the additional switch and digital control line. DIGITALLY POGAMMABLE ACTIVE FILTE DAC780X are shown in Figure 9 in a digitally programmable active filter application. The design is based on the statevariable filter, Burr-Brown UAF, an active filter topology that offers stable and repeatable filter characteristics. DAC and DAC can be updated in parallel with a single word to set the center frequency of the filter. DAC, which makes use of the uncommitted op amp in UAF, sets the Q of the filter. DAC sets the gain of the filter transfer function without changing the Q of the filter. The reverse is also true. The center frequency is determined by f C = /πc where is the ladder resistance of the D/A (typical value, 0kΩ) and C the internal capacitor value (000pF) of the UAF. External capacitors can be added to lower the center frequency of the filter. But the highest center frequency for this circuit will be about khz because the effective series resistance of the D/A cannot be less than 0kΩ. Note that the ladder resistance of the D/A may vary from device to device. Thus, for best tracking, DAC and DAC should be in the same package. Some calibration may be necessary from one filter to another. DAC7800/0/0

12 C D µf V IN A 00 Ω V EF A FB A Ω 0k Ω 7 7 0kΩ Ω 0k A V OUT A DAC780 FB B Ω 7 C DAC780 has a single analog common, AGND. A, OPA0 or / OP07. VIN B V EF B 00 Ω 0Ω 0k C A 9 0kΩ Ω 8Ω 0k A V OUT B FIGUE. Bipolar Configuration with Gain Trim. EF0 C D µf V EF A FB A DAC780X C ± Bits Sign Control DG88 IN0 V EF B DAC780 has a single analog common, AGND. OPA0 or / OP07. FIGUE 7. -Bit Plus Sign DAC. DAC7800/0/0

13 EF0 C D µf V EF A FB A DAC780X FB B C ± Bits C A IN0 V EF B DAC780 has a single analog common, AGND. OPA0 or / OP07. FIGUE 8. -Bit Bipolar DAC. Q Adjust V EF DAC I OUT V EF FB I OUT AGND DAC AGND f C Adjust V EF I OUT / DAC780X DAC AGND DAC780X High-Pass Out Band-Pass Out Low-Pass Out Filter Input V EF IOUT 8 7 DAC AGND C C / DAC780X Gain Adjust = 0k Ω ±0.% C = 000pF ±0.% UAF FIGUE 9. Digitally Programmable Universal Active Filter. DAC7800/0/0