CMOS Dual 8-Bit Buffered Multiplying DAC AD7528

Transcription

1 a FEATUES On-Chip Latches for Both DACs +5 V to +15 V Operation DACs Matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible Latch Free (Protection Schottkys not equired) APPLICATIONS Digital Control of: Gain/Attenuation Filter Parameters Stereo Audio Circuits X-Y Graphics / CMOS Dual 8-Bit Buffered Multiplying DAC FUNCTIONAL BLOCK DIAGAM INPUT BUFFE CONTOL V EF A FB B V EF B GENEAL DESCIPTION The is a monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. It is available in skinny." wide -lead DIPs and in -lead surface mount packages. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input / determines which DAC is to be loaded. The s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors, including 68, 88, 885, Z8. The device operates from a +5 V to +15 V power supply, dissipating only mw of power. Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC. PODUCT HIGHLIGHTS 1. DAC-to-DAC matching: since both of the DACs are fabricated at the same time on the same chip, precise matching and tracking between and is inherent. The s matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas.. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a / select line has allowed the to be packaged in either a small -lead DIP, SOIC or PLCC. ODEING GUIDE 1 Temperature elative Gain Package Model anges Accuracy Error Options JN 4 C to +85 C ±1 LSB ±4 LSB N- KN 4 C to +85 C ±1/ LSB ± LSB N- LN 4 C to +85 C ±1/ LSB ±1 LSB N- JP 4 C to +85 C ±1 LSB ±4 LSB P-A KP 4 C to +85 C ±1/ LSB ± LSB P-A LP 4 C to +85 C ±1/ LSB ±1 LSB P-A J 4 C to +85 C ±1 LSB ±4 LSB - K 4 C to +85 C ±1/ LSB ± LSB - L 4 C to +85 C ±1/ LSB ±1 LSB - AQ 4 C to +85 C ±1 LSB ±4 LSB Q- BQ 4 C to +85 C ±1/ LSB ± LSB Q- CQ 4 C to +85 C ±1/ LSB ±1 LSB Q- SQ 55 C to +15 C ±1 LSB ±4 LSB Q- TQ 55 C to +15 C ±1/ LSB ± LSB Q- UQ 55 C to +15 C ±1/ LSB ±1 LSB Q- NOTES 1 Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator Q. Processing to MIL-STD-88C, Class B is available. To order, add suffix /88B to part number. For further information, see Analog Devices 199 Military Products Databook. N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; = SOIC. EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 916, Norwood, MA 6-916, U.S.A. Tel: 781/9-47 World Wide Web Site: Fax: 781/6-87 Analog Devices, Inc., 1998

2 SPECIFICATIONS (V EF A = V EF B = +1 V; = = O V unless otherwise noted) = +5 V = +15 V Parameter Version 1 T A = +5 C T MIN, T MAX T A = +5 C T MIN, T MAX Units Test Conditions/Comments STATIC PEFOMANCE esolution All Bits elative Accuracy J, A, S ± 1 ± 1 ± 1 ± 1 LSB max This is an Endpoint Linearity Specification K, B, T ± 1/ ± 1/ ± 1/ ± 1/ LSB max L, C, U ± 1/ ± 1/ ± 1/ ± 1/ LSB max Differential Nonlinearity All ± 1 ± 1 ± 1 ± 1 LSB max All Grades Guaranteed Monotonic Over Full Operating Temperature ange Gain Error J, A, S ± 4 ± 6 ± 4 ± 5 LSB max Measured Using Internal and FB B K, B, T ± ± 4 ± ± LSB max Both DAC Latches Loaded with L, C, U ± 1 ± ± 1 ± 1 LSB max Gain Error is Adjustable Using Circuits of Figures 4 and 5 Gain Temperature Coefficient Gain/ Temperature All ±.7 ±.7 ±.5 ±.5 %/ C max Output Leakage Current (Pin ) All ± 5 ± 4 ± 5 ± na max DAC Latches Loaded with (Pin ) All ± 5 ± 4 ± 5 ± na max Input esistance (V EF A, V EF B) All kω min Input esistance TC = ppm/ C, Typical kω max Input esistance is 11 kω V EF A/V EF B Input esistance Match All ± 1 ± 1 ± 1 ± 1 % max DIGITAL 4 Input High Voltage V IH All V min Input Low Voltage V IL All V max Input Current I IN All ± 1 ± 1 ± 1 ± 1 µa max V IN = or Input Capacitance All pf max,, / All pf max SWITCHING CHAACTEISTI See Timing Diagram Chip Select to Write Set Up Time t All ns min Chip Select to Write Hold Time t CH All 1 15 ns min DAC Select to Write Set Up Time t AS All ns min DAC Select to Write Hold Time t AH All 1 15 ns min Data Valid to Write Set Up Time t DS All ns min Data Valid to Write Hold Time t DH All ns min Write Pulsewidth t All ns min POWE SUPPLY See Figure I DD All ma max All Digital Inputs V IL or V IH All µa max All Digital Inputs V or AC PEFOMANCE CHAACTEISTI 5 = +5 V (Measured Using ecommended P.C. Board Layout (Figure 7) and AD644 as Output Amplifiers) = +15 V Parameter Version 1 T A = +5 C T MIN, T MAX T A = +5 C T MIN, T MAX Units Test Conditions/Comments DC SUPPLY EJECTION ( GAIN/ ) All % per % max = ± 5% CUENT SETTLING TIME All ns max To 1/ LSB. / Load = 1 Ω. = = V. = V to or to V POPAGATION DELAY (From Digital In- V EF A = V EF B = +1 V put to 9% of Final Analog Output Current) All ns max, Load = 1 Ω C EXT = 1 pf = = V = V to or to V DIGITAL-TO-ANALOG GLITCH IMPULSE All nv sec typ For Code Transition to OUTPUT CAPACITANCE C All pf max DAC Latches Loaded with C pf max C pf max DAC Latches Loaded with C pf max AC FEEDTHOUGH 6 V EF A to All db max V EF A, V EF B = V p-p Sine Wave V EF B to db 1 khz EV. B

3 = +5 V = +15 V Parameter Version 1 T A = +5 C T MIN, T MAX T A = +5 C T MIN, T MAX Units Test Conditions/Comments CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with V EF A to All db typ V EF A = V p-p Sine 1 khz V EF B = V see Figure 6. V EF B to db typ V EF A = V p-p Sine 1 khz V EF A = V see Figure 6. DIGITAL COSSTALK All 6 nv sec typ Measured for Code Transition to HAMONIC DISTOTlON All db typ V IN = 6 V 1 khz NOTES 1 Temperature anges are J, K, L Versions: 4 C to +85 C A, B, C Versions: 4 C to +85 C S, T, U Versions: 55 C to +15 C Specifications applies to both DACs in. Guaranteed by design but not production tested. 4 Logic inputs are MOS Gates. Typical input current (+5 C) is less than 1 na. 5 These characteristics are for design guidance only and are not subject to test. 6 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix D) to. Specifications subject to change without notice. ABSOLUTE MAXIMUM ATINGS (T A = +5 C unless otherwise noted) to V, +17 V to V, +17 V to V to V Digital Input Voltage to V, +. V V PIN, V PIN to V, +. V V EF A, V EF B to ± 5 V V FB A, V FB B to ± 5 V Power Dissipation (Any Package) to +75 C mw Derates above +75 C by mw/ C Operating Temperature ange Commercial (J, K, L) Grades C to +85 C Industrial (A, B, C) Grades C to +85 C Extended (S, T, U) Grades C to +15 C Storage Temperature C to +15 C Lead Temperature (Soldering, 1 secs) C CAUTION: 1. ESD sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts.. Do not insert this device into powered sockets. emove power before insertion or removal. TEMINOLOGY elative Accuracy elative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For the, ideal maximum output is V EF 1 LSB. Gain error of both DACs is adjustable to zero with external resistance. Output Capacitance Capacitance from or to. Digital to Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pa-secs or nv-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with V EF A, V EF B =. Propagation Delay This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 9% of its final value. Channel-to-Channel Isolation The proportion of input signal from one DAC s reference input which appears at the output of the other DAC, expressed as a ratio in db. Digital Crosstalk The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Specified in nv secs. V EF A 4 5 / 6 (MSB) 7 DB6 8 PIN CONFIGUATIONS PLCC FB B 1 19 PIN 1 IDENTIFIE TOP VIEW (Not to Scale) DB5 DB4 DB DB DB1 18 V EF B (LSB) DIP, SOIC 1 V EF A FB B 18 V EF B / (MSB) DB6 DB5 DB TOP VIEW 15 (Not to Scale) 14 (LSB) 1 DB1 1 DB 11 DB EV. B

4 INTEFACE INFOMATION DAC Selection: Both DAC latches share a common 8-bit input port. The control input / selects which DAC can accept data from the input port. Mode Selection: Inputs and control the operating mode of the selected DAC. See Mode Selection Table below. Write Mode: When and are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on. Hold Mode: The selected DAC latch retains the data which was present on just prior to or assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. Mode Selection Table / L L L ITE HOLD H L L HOLD ITE X H X HOLD HOLD X X H HOLD HOLD L = Low State; H = High State; X = Don t Care. ITE CYCLE TIMING DIAGAM CHIP SELECT / ITE IN ( ) V IH V IL t t AS t t DS IN STABLE t CH t AH t DH NOTES: 1. ALL INPUT SIGNAL ISE AND FALL TIMES MEASUED FOM 1% TO 9% OF. = +5V, t r = t f = ns; = +15V, t r = t f = 4ns;. TIMING MEASUEMENT EFEENCE LEVEL IS V IH + V IL CICUIT INFOMATION D/A SECTION The contains two identical 8-bit multiplying D/A converters, and. Each DAC consists of a highly stable thin film - ladder and eight N-channel current steering switches. A simplified D/A circuit for is shown in V EF A S1 S S ES AND DIVES S8 Figure 1. Simplified Functional Circuit for Figure 1. An inverted - ladder structure is used, that is, binary weighted currents are switched between the DAC output and thus maintaining fixed currents in each ladder leg independent of switch state. EQUIVALENT CICUIT ANALYSIS Figure shows an approximate equivalent circuit for one of the s D/A converters, in this case. A similar equivalent circuit can be drawn for. Note that (Pin 1) is common for both and. The current source I LEAKAGE is composed of surface and junction leakages and, as with most semiconductor devices, approximately doubles every 1 C. The resistor O as shown in Figure is the equivalent output resistance of the device which varies with input code (excluding all s code) from.8 to. is typically 11 kω. C OUT is the capacitance due to the N-channel switches and varies from about 5 pf to 1 pf depending upon the digital input. g(v EF A, N) is the Thevenin equivalent voltage generator due to the reference input voltage V EF A and the transfer function of the - ladder. O g(v EF A, N) I LKG C OUT Figure. Equivalent Analog Output Circuit of CICUIT INFOMATION DIGITAL SECTION The input buffers are simple CMOS inverters designed such that when the is operated with = 5 V, the buffer converts TTL input levels (.4 V and.8 V) into CMOS logic levels. When V IN is in the region of. volts to.5 volts the input buffers operate in their linear region and pass a quiescent current, see Figure. To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails ( and ) as is practically possible. The may be operated with any supply voltage in the range 5 15 volts. With = +15 V the input logic levels are CMOS compatible only, i.e., 1.5 V and 1.5 V. I DD A ( = +5V) 8 = +15V = +5V 1 T A = +5 C ALL DIGITAL TIED TOGETHE V IN Volts Figure. Typical Plots of Supply Current, I DD vs. Logic Input Voltage V IN, for = +5 V and +15 V I DD ma ( = +15V) 4 EV. B

5 / INPUT BUFFE CONTOL V IN A (± 1V) FB B V IN B (± 1V) NOTES: 1 1, AND, 4 USED ONLY IF GAIN ADJUSTMENT IS EQUIED. SEE TABLE III FO ECOMMENDED VALUES. C1, C PHASE COMPENSATION (1pF 15pF) IS EQUIED WHEN USING HIGH SPEED AMPLIFIES TO PEVENT INGING O OSCILLATION C1 C V V Table I. Unipolar Binary Code Table DAC Latch Contents Analog Output MSB LSB ( or ) = V IN = 56 Note: 1 LSB = ( 8 )( V IN )= 1 ( 56 V IN ) Figure 4. Dual DAC Unipolar Binary Operation ( Quadrant Multiplication); See Table I / INPUT BUFFE CONTOL V IN A (± 1V) FB B 6 k 7 1k C1 A1 C A 9 1k 1 k 5 k A 11 5k 8 k A4 V V Table II. Bipolar (Offset Binary) Code Table DAC Latch Contents Analog Output MSB LSB ( or ) V IN V IN B (± 1V) NOTES: 1 1, AND, 4 USED ONLY IF GAIN ADJUSTMENT IS EQUIED. SEE TABLE III FO ECOMMENDED VALUES. ADJUST 1 FO V = V WITH CODE 1 IN. ADJUST FO V = V WITH CODE 1 IN. MATCHING AND TACKING IS ESSENTIAL FO ESISTO PAIS 6, 7 AND 9, 1. C1, C PHASE COMPENSATION (1pF 15pF) MAY BE EQUIED IF A1/A IS A HIGH SPEED AMPLIFIE. Figure 5. Dual ipolar Operation (4 Quadrant Multiplication); See Table II 1 5k Note: 1 LSB = ( 7 )( V IN )= 1 ( 18 V IN ) Table III. ecommended Trim esistor Values vs. Grade Trim esistor J/A/S K/B/T L/C/U 1; 1 k 5 ; EV. B 5

6 APPLICATIONS INFOMATION Application Hints To ensure system performance consistent with specifications, careful attention must be given to the following points: 1. GENEAL GOUND MANAGEMENT: AC or transient voltages between the and can cause noise injection into the analog output. The simplest method of ensuring that voltages at and are equal is to tie and together at the. In more complex systems where the intertie is on the backplane, it is recommended that diodes be connected in inverse parallel between the and pins (1N914 or equivalent).. OUTPUT AMPLIFIE OFFSET: CMOS DACs exhibit a code-dependent output resistance which in turn causes a code-dependent amplifier noise gain. The effect is a codedependent differential nonlinearity term at the amplifier output which depends on V OS (V OS is amplifier input offset voltage). This differential nonlinearity term adds to the / differential nonlinearity. To maintain monotonic operation, it is recommended that amplifier V OS be no greater than 1% of 1 LSB over the temperature range of interest.. HIGH FEQUENCY CONSIDEATIONS: The output capacitance of a CMOS DAC works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. DYNAMIC PEFOMANCE The dynamic performance of the two DACs in the will depend upon the gain and phase characteristics of the output amplifiers together with the optimum choice of the PC board layout and decoupling components. Figure 6 shows the relation ISOLATION db T A = +5 C = +15V V IN = V PEAK TO PEAK k 5k 1k k 5k 1M INPUT FEQUENCY Hz Figure 6. Channel-to-Channel Isolation ship between input frequency and channel to channel isolation. Figure 7 shows a printed circuit layout for the and the AD644 dual op amp which minimizes feedthrough and crosstalk. SINGLE SUPPLY APPLICATIONS The DAC - ladder termination resistors are connected to within the device. This arrangement is particularly convenient for single supply operation because may be biased at any voltage between and. Figure 8 shows a circuit which provides two +5 V to +8 V analog outputs by biasing +5 V up from. The two DAC reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant and matched impedances of the and reference inputs. Current flows through the two DAC - ladders into 1 and 1 is adjusted until the V EF A and V EF B inputs are at + V. The two analog output voltages range from +5 V to +8 V for DAC codes to / VOLTS 1 1k 1k = +15V SUGGESTED OP AMP: AD644 AD584J GND V = +5V TO +8V V = +5V TO +8V Figure 8. Single Supply Operation Figure 9 shows of the connected in a positive reference, voltage switching mode. This configuration is useful in that V OUT is the same polarity as V IN allowing single supply operation. However, to retain specified linearity, V IN must be in the range V to +.5 V and the output buffered or loaded with a high impedance, see Figure 1. Note that the input voltage is connected to the DAC and the output voltage is taken from the DAC V EF A pin. V IN (V TO +.5V) +15V V EF A V OUT Figure 9. in Single Supply, Voltage Switching Mode AD644 PIN 8 OF TO-5 CAN (AD644) V+ T A = +5 C = +15V C1 LOCATION V EF B* LSB V PIN 1 C LOCATION V EF A* / MSB *NOTE INPUT SCEENS TO EDUCE FEEDTHOUGH. LAYOUT SHOWS COPPE SIDE (i.e., BOTTOM VIEW). Figure 7. Suggested PC Board Layout for with AD644 Dual Op Amp EO LSB 1.5 NONLINEAITY DIFFEENTIAL NONLINEAITY V IN A Volts Figure 1. Typical Performance in Single Supply Voltage Switching Mode (K/B/T, L/C/U Grades) 6 EV. B

7 MICOPOCESSO INTEFACE A8 A15 ADDESS BUS A A15 V MA CPU 68 D D7 ADDESS DECODE A** A + 1** ADDESS BUS BUS / * *ANALOG CICUITY HAS BEEN OMITTED FO CLAITY **A = DECODED 758 ADD A + 1 = DECODED 758 ADD CPU 885 ALE ADDESS DECODE 81 A** A + 1** / * AD AD7 ADD/ BUS *ANALOG CICUITY HAS BEEN OMITTED FO CLAITY **A = DECODED 758 ADD A + 1 = DECODED 758 ADD NOTE: 885 INSTUCTION SHLD (STOE H & L DIECT) CAN UPDATE BOTH DACs WITH FOM H AND L EGISTES Figure 11. Dual DAC to 68 CPU Interface Figure 1. Dual DAC to 885 CPU Interface POGAMMABLE WINDOW COMPAATO TEST INPUT TO V EF / +V EF V EF A V EF B FB B 7 AD11 COMPAATO 7 AD11 COMPAATO V CC 1k PASS/ FAIL OUTPUT In the circuit of Figure 1 the is used to implement a programmable window comparator. DACs A and B are loaded with the required upper and lower voltage limits for the test, respectively. If the test input is not within the programmed limits, the pass/fail output will indicate a fail (logic zero). Figure 1. Digitally Programmable Window Comparator (Upper and Lower Limit Detector) POGAMMABLE STATE VAIABLE FILTE In this state variable or universal filter configuration (Figure 14) DACs A1 and B1 control the gain and Q of the filter characteristic while DACs A and B control the cutoff frequency, f C. DACs A and B must track accurately for the simple expression for f C to hold. This is readily accomplished by the. Op amps are AD644. C compensates for the effects of op amp gain bandwidth limitations. The filter provides low pass, high pass and band pass outputs and is ideally suited for applications where microprocessor control of filter parameters is required, e.g., equalizer, tone controls, etc. Programmable range for component values shown is f C = khz to 15 khz and Q =. to 4.5. V IN 1 S A1 1 F 1k 4 k A 5 k C 47pF HIGH PASS OUTPUT 1 C1 1pF A BAND PASS OUTPUT C 1pF A4 LOW PASS OUTPUT CICUIT EQUATIONS C1= C, 1=, 4= 5 1 fc = π C 1 1 Q F = FBB F AO = 4 1 S 1 / / Figure 14. Digitally Controlled State Variable Filter NOTE DAC Equivalent esistance Equals 56 ( DAC Ladder esistance) DAC Digital Code EV. B 7

8 DIGITALLY CONTOLLED DUAL TELEPHONE ATTENUATO In this configuration the functions as a -channel digitally controlled attenuator. Ideal for stereo audio and telephone signal level control applications. Table IV gives input codes vs. attenuation for a db to 15.5 db range. Input Code = 56 1 exp Attenuation, db V IN A V A A1 BUS V / V IN B SUGGESTED OP AMP: AD644 Figure 15. Digitally Controlled Dual Telephone Attenuator Table IV. Attenuation vs., Code for the Circuit of Figure 15 Attn. DAC Input Code In Attn. DAC Input Code In db Code Decimal db Code Decimal For further applications information the reader is referred to Analog Devices Application Note on the. C681e 9/98 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). PIN 1. (5.).14 (.56).15 (.8).15 (.18) -Lead Cerdip (Q-) (4.64).95 (.75) 11.8 (7.11).4 (6.1).14 (.56).15 (.17) SEATING PLANE. (8.18).9 (7.66).7 (1.78). (.5).11 (.79) 15.5 (1.7).16 (.41).9 (.8) LEAD NO. 1 IDENTIFIED BY DOT O NOTCH LEADS AE SOLDE O TIN-PLATED KOVA O ALLOY 4.11 (.8).9 (.).145 (.68) MIN.15 (.175) MIN.1 (.5).15 (.81) -Lead Plastic DIP (N-) PIN (7.18) MAX.55 (6.477).45 (6.).15 (.49).15 (.17) SEATING.11 (.79).65 (1.66) PLANE.9 (.8).45 (1.15). (8.18). (7.6) 15 LEAD NO. 1 IDENTIFIED BY DOT O NOTCH LEADS AE SOLDE O TIN-PLATED KOVA O ALLOY 4.11 (.8).9 (.) 1 PIN (.).4 (.1).5118 (1.).4961 (1.6).5 (1.7) BSC -Lead SOIC (-).19 (.49).18 (.5) (7.6).914 (7.4).419 (1.65) 1.97 (1.).14 (.65).96 (.5) SEATING PLANE.15 (.).91 (.).91 (.74) (.5) 8.5 (1.7).157 (.4) -Lead Plastic Leaded Chip Carrier (P-A).48 (1.1).4 (1.7) 8. (.51) 9 MAX. (.51) MAX.95 (1.).85 (9.78) SQ.56 (9.4).5 (8.89) SQ 19 4 PIN 1 IDENTIFIE 18 TOP VIEW (PINS DOWN) (1.7) BSC.18 (4.47).165 (4.19).1 (.5).9 (.9). (.51) MIN.1 (.5).1 (.). (.81).6 (.66).5 (.64) MIN.6 (1.5) MIN PINTED IN U.S.A. 8 EV. B