Matched Monolithic Quad Transistor MAT14

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1 Matched Monolithic Quad Transistor MAT4 FEATUES Low offset voltage: 400 µv maximum High current gain: 300 minimum Excellent current gain match: 4% maximum Low voltage noise density at 00 Hz, ma 3 nv/ Hz maximum Excellent log conformance Bulk resistance (r BE ) = 0.6 Ω maximum Guaranteed matching for all transistors APPLICATIONS Low noise op amp front end Current mirror and current sink/source Low noise instrumentation amplifiers Voltage controlled attenuators Log amplifiers GENEAL DESCIPTION The MAT4 is a quad monolithic NPN transistor that offers excellent parametric matching for precision amplifier and nonlinear circuit applications. Performance characteristics of the MAT4 include high gain (300 minimum) over a wide range of collector current, low noise (3 nv/ Hz maximum at 00 Hz, I C = ma), and excellent logarithmic conformance. The MAT4 also features a low offset voltage of 00 µv typical and tight current gain matching to within 4%. Each transistor of the MAT4 is individually tested to data sheet specifications. For matching parameters (offset voltage, input offset current, and gain match), each of the dual transistor combinations are PIN CONFIGUATION C 4 C 4 B 2 3 B 4 E 3 MAT4 2 E 4 SUB 4 TOP VIEW SUB E 2 5 (Not to Scale) 0 E 3 B B 3 C C 3 Figure. verified to meet stated limits. Device performance is guaranteed at an ambient temperature of 25 C and over the industrial temperature range. The long-term stability of matching parameters is guaranteed by the protection diodes across the base emitter junction of each transistor. These diodes prevent degradation of beta and matching characteristics due to reverse bias, base emitter current. The superior logarithmic conformance and accurate matching characteristics of the MAT4 make it an excellent choice for use in log and antilog circuits. The MAT4 is an ideal choice in applications where low noise and high gain are required ev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Pin Configuration... General Description... evision History... 2 Specifications... 3 Electrical Characteristics... 3 Absolute Maximum atings... 4 Thermal esistance...4 ESD Caution...4 Typical Performance Characteristics...5 Theory of Operation...8 Applications Information...8 Outline Dimensions...9 Ordering Guide...9 EVISION HISTOY 2/0 ev. 0 to ev. A Changes to General Description... Changes to Operating Temperature ange in Table Updated Outline Dimensions... 9 Changes to Ordering Guide /0 evision 0: Initial Version ev. A Page 2 of 2

3 SPECIFICATIONS ELECTICAL CHAACTEISTICS T A = 25 C, unless otherwise specified. Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DC AND AC CHAACTEISTICS Current Gain h FE 0 µa I C ma 0 V V CB 30 V C T A +85 C Current Gain Match Δh FE I C = 00 µa 2 4 % 0 V V CB 30 V Noise Voltage Density e N I C = ma, V CB = 0 3 f O = 0 Hz 2 4 nv/ Hz f O = 00 Hz.8 3 nv/ Hz f O = khz.8 3 nv/ Hz Offset Voltage V OS 0 µa I C ma 4 0 V V CB 30 V µv 40 C T A +85 C μv Offset Voltage Change vs. V CB Change ΔV OS /ΔV CB 0 V V CB 30 V 4 0 µa I C ma µv Offset Voltage Change vs. I C Change ΔV OS /ΔI C 0 µa I C ma 4, V CB = 0 V 0 50 µv Offset Voltage Drift ΔV OS /ΔT 40 C T A +85 C I C = 00 µa, V CB = 0 V µv/ C Breakdown Voltage BV CEO I C = 0 µa 40 V 40 C T A +85 C 40 V Gain-Bandwidth Product f T I C = ma, V CE = 0 V 300 MHz Collector Leakage Current Base I CBO V CB = 40 V 5 pa 40 C T A +85 C 0.5 na Substrate I CS V CS = 40 V 0.5 na 40 C T A +85 C 0.7 na Emitter I CES V CE = 40 V 3 na 40 C T A +85 C 5 na Input Current Bias I B I C = 00 µa, 0 V V CB 30 V na 40 C T A +85 C na Offset I OS I C = 00 µa, V CB = 0 V 2 3 na 40 C T A +85 C 8 40 na Offset Drift ΔI OS /ΔT I C = 00 µa 40 C T A +85 C 00 pa/ C Collector Saturation Voltage V CE(SAT) I C = ma, I B = 00 µa V Output Capacitance C OBO 5 V CB = 5 V, I E = 0, f = MHz 0 pf Bulk esistance r BE 0 µa I C 0 ma,v CB = 0 V Ω Input Capacitance C EBO V CB = 5 V, I E = 0, f = MHz 40 pf Current gain measured at I C = 0 µa, 00 µa, and ma. 2 Current gain match (Δh FE ) defined as: Δh FE = (00(ΔI B )(h FE min )/I C ). 3 Sample tested. 4 Measured at I C = 0 µa and guaranteed by design over the specified range of I C. 5 See Table 2 for the emitter current rating. 6 Guaranteed by design. ev. A Page 3 of 2

4 ABSOLUTE MAXIMUM ATINGS Table 2. Parameter Voltage Collector-to-Base Voltage (BV CBO ) Collector-to-Emitter Voltage (BV CEO ) Collector-to-Collector Voltage (BV CC ) Emitter-to-Emitter Voltage (BV EE ) Current Collector Current (I C ) Emitter Current (I E ) Temperature Storage Temperature ange Operating Temperature ange Junction Temperature ange ating 40 V 40 V 40 V 40 V 30 ma 30 ma 65 C to +50 C 40 C to +85 C 65 C to +50 C THEMAL ESISTANCE θ JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal esistance Package Type θ JA θ JC Unit 4-Lead SOIC 5 36 C/W ESD CAUTION Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ev. A Page 4 of 2

5 TYPICAL PEFOMANCE CHAACTEISTICS CUENT GAIN (β) T A = 25 C T A = 85 C T A = 25 C COLLECTO CUENT (ma) Figure 2. Current Gain vs. Collector Current BASE EMITTE-ON-VOLTAGE (V) COLLECTO CUENT (ma) Figure 5. Base Emitter-On-Voltage vs. Collector Current CUENT GAIN (β) V CB = 20V V CB = 0V TEMPEATUE ( C) Figure 3. Current Gain vs. Temperature INPUT ESISTANCE (MΩ) COLLECTO CUENT (ma) Figure 6. Small Signal Input esistance vs. Collector Current m VOLTAGE NOISE DENSITY (nv/srthz) NOISE = 00Hz NOISE = 0Hz CONDUCTANCE ( ) 0.m 0.0m µ 0.µ COLLECTO CUENT (I C ) Figure 4. Voltage Noise Density vs. Collector Current µ µ 0.0m 0.m m COLLECTO CUENT (A) Figure 7. Small Signal Output Conductance vs. Collector Current ev. A Page 5 of 2

6 SATUATION VOLTAGE (V) 0. T A = 25 C T A = 85 C T A = 25 C COLLECTO CUENT (ma) TOTAL NOISE (nv/ Hz) 20 00kΩ kΩ kω COLLECTO CUENT (ma) Figure 8. Saturation Voltage vs. Collector Current Figure 0. Total Noise vs. Collector Current NOISE DENSITY (nv Hz) 0 0µA ma COLLECTO-TO-BASE CAPACITANCE (pf) k 0k FEQUENCY (Hz) Figure 9. Noise Voltage Density vs. Frequency COLLECTO-TO-BASE VOLTAGE (V) Figure. Collector-to-Base Capacitance vs. Collector-to-Base Voltage ev. A Page 6 of 2

7 COLLECTO-TO-SUBSTATE CAPACITANCE (pf) COLLECTO-TO-SUBSTATE VOLTAGE (V) Figure 2. Collector-to-Substrate Capacitance vs. Collector-to-Substrate Voltage I CC CUENT (na) TEMPEATUE ( C) Figure 4. Collector-to-Collector Leakage vs. Temperature I CBO CUENT (na) TEMPEATUE ( C) Figure 3. Collector-to-Base Leakage vs. Temperature ev. A Page 7 of 2

8 THEOY OF OPEATION APPLICATIONS INFOMATION To minimize coupling between devices, tie one of the substrate pins (Pin 4 or Pin ) to the most negative circuit potential. Note that Pin 4 and Pin are internally connected. Applications Current Sources MAT4 can be used to implement a variety of high impedance current mirrors as shown in Figure 5, Figure 6, and Figure 7. These current mirrors can be used as biasing elements and load devices for amplifier stages. I EF I OUT = I EF these mirrors is reduced from that of the unity-gain source due to base current errors but remains better than 2%. Q2 I EF I OUT = 2(I EF ) V Q3 Q Q4 Figure 6. Current Mirror, I OUT = 2(l EF ) Q Q2 I EF I OUT = /2(I EF ) Q3 Q4 Q V Q2 Q3 Q4 Figure 5. Unity-Gain Current Mirror, I OUT = I EF The unity-gain current mirror shown in Figure 5 has an accuracy of better than % and an output impedance of more than 00 MΩ at 00 μa. Figure 6 and Figure 7 each show a modified current mirror; Figure 6 is designed for a current gain of two (2), and Figure 7 is designed for a current gain of one-half (½). The accuracy of V Figure 7. Current Mirror, I OUT = ½(I EF ) Figure 8 is a temperature independent current sink that has an accuracy of better than % at an output current of 00 μa to ma. A Schottky diode acts as a clamp to ensure correct circuit startup at power-on. Use % metal film type resistors in this circuit V 2 AD0 6 I OUT = 0V 4 I OUT I OUT I OUT 00pF OP MAT4 HP V Figure 8. Temperature Independent Current Sink, I OUT = 0 V/ ev. A Page 8 of 2

9 OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.575) 3.80 (0.496) (0.244) 5.80 (0.2283) 0.25 (0.0098) 0.0 (0.0039) COPLANAITY (0.0500) BSC 0.5 (0.020) 0.3 (0.022).75 (0.0689).35 (0.053) SEATING PLANE (0.0098) 0.7 (0.0067) 0.50 (0.097) 0.25 (0.0098).27 (0.0500) 0.40 (0.057) 45 COMPLIANT TO JEDEC STANDADS MS-02-AB CONTOLLING DIMENSIONS AE IN MILLIMETES; INCH DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF MILLIMETE EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. Figure 9. 4-Lead Standard Small Outline Package [SOIC_N] Narrow Body (-4) Dimensions shown in millimeters and (inches) ODEING GUIDE Model Temperature ange Package Description Package Option MAT4AZ 40 C to +85 C 4-Lead Standard Small Outline Package [SOIC_N] -4 MAT4AZ-7 40 C to +85 C 4-Lead Standard Small Outline Package [SOIC_N] -4 MAT4AZ-L 40 C to +85 C 4-Lead Standard Small Outline Package [SOIC_N] -4 Z = ohs Compliant Part A ev. A Page 9 of 2

10 NOTES ev. A Page 0 of 2

11 NOTES ev. A Page of 2

Matched Monolithic Quad Transistor MAT04

Matched Monolithic Quad Transistor MAT04 a FEATURES Low Offset Voltage: 200 V max High Current Gain: 400 min Excellent Current Gain Match: 2% max Low Noise Voltage at 100 Hz, 1 ma: 2.5 nv/ Hz max Excellent Log Conformance: rbe = 0.6 max Matching